Display device

Abstract

A display device includes: a pixel; a signal line electrically connected to the pixel; and a signal pad connected to the signal line. The signal pad includes: a first conductive pattern disposed on the pad portion; a second conductive pattern disposed on the first conductive pattern; and an insulating pattern disposed between the pad portion of the signal line and the second conductive pattern in a cross-sectional view, and overlapping the second conductive pattern in a plan view. The insulating pattern passes through the first conductive pattern via a hole defined in the first conductive pattern and overlapping the insulating pattern in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0121630 filed on September 13, 2023 and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure herein relates to a display device, and more particularly, to a pad area of ​​a display device. Background Art

[0004] The display device includes a display area that is activated in response to an electrical signal. The display device can detect an input applied from the outside through the display area, and can also display various images to provide information to a user.

[0005] The display device includes a display panel and a circuit board. The display panel can be connected to the main board through the circuit board. The driver chip can be mounted on the display panel. Summary of the invention

[0006] The present disclosure provides a display device having improved bonding reliability.

[0007] An embodiment of the present invention provides a display device, including a display module, wherein the display module includes: a pixel; a signal line, including a line portion and a pad portion extending from one end of the line portion and electrically connected to the pixel; and a signal pad connected to the signal line, the signal pad including a first conductive pattern arranged on the pad portion, a second conductive pattern arranged on the first conductive pattern, and an insulating pattern arranged between the pad portion and the second conductive pattern in a cross-sectional view and overlapping with the second conductive pattern in a plan view, a hole overlapping with the insulating pattern in the plan view is defined in the first conductive pattern, and the insulating pattern passes through the first conductive pattern via the above-mentioned hole.

[0008] In an embodiment, a portion of a side surface of the insulation pattern may contact the first conductive pattern.

[0009] In an embodiment, the insulating pattern may protrude from the first conductive pattern toward a direction away from the pad portion.

[0010] In an embodiment, the first conductive pattern may have a multi-layer structure.

[0011] In an embodiment, the second conductive pattern may contact at least a portion of an upper surface of the first conductive pattern and a portion of the insulating pattern exposed from the first conductive pattern.

[0012] In an embodiment, in a cross-sectional view, the second conductive pattern may further contact a portion of an outer side surface of the first conductive pattern opposite to an inner side surface defining the hole.

[0013] In an embodiment, the display module may further include a first group of insulating layers arranged between the pad portion of the signal line and the first conductive pattern, a lower hole overlapping the above-mentioned hole in a plan view may be defined in the first group of insulating layers, and the insulating pattern may pass through the first group of insulating layers via the lower hole.

[0014] In an embodiment, the insulation pattern may contact a portion of the pad portion of the signal line that overlaps the lower hole in a plan view.

[0015] In an embodiment, the display module may further include a first group of insulating layers arranged between a pad portion of the signal line and the first conductive pattern, a first contact hole overlapping with the pad portion of the signal line and spaced apart from the insulating pattern in a plan view may be defined in the first group of insulating layers, and the first conductive pattern may contact the pad portion of the signal line via the first contact hole.

[0016] In an embodiment, the first conductive pattern may include a contact portion and a recessed portion having a width in one direction smaller than that of the contact portion, the first contact hole may overlap the contact portion in a plan view, and the hole may be defined in the recessed portion.

[0017] In an embodiment, the display module may further include a second group of insulating layers disposed between the first conductive pattern and the second conductive pattern and having a second contact hole, the second contact hole being defined in the second group of insulating layers, and in a plan view, the first contact hole and the insulating pattern may be disposed within the second contact hole.

[0018] In an embodiment, a pixel may include: a light emitting element; a transistor electrically connected to the light emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern; an upper electrode disposed on the gate; and a plurality of connecting electrodes electrically connected to the transistor and disposed in different layers, a pad portion of the signal line may include the same material as that of the gate or the upper electrode, and the first conductive pattern may include the same material as that of at least one of the plurality of connecting electrodes.

[0019] In an embodiment, the display module may further include: a lower insulating layer, arranged between the gate and the upper electrode; an intermediate insulating layer, arranged between the upper electrode and a plurality of connecting electrodes; and an upper insulating layer, arranged between the plurality of connecting electrodes, and the first group of insulating layers may include a lower insulating layer, an intermediate insulating layer and an upper insulating layer.

[0020] In an embodiment, the display module may further include: a thin film encapsulation layer disposed on the pixel; and a sensing electrode disposed on the thin film encapsulation layer, and the second conductive pattern may include the same material as that of the sensing electrode.

[0021] In an embodiment, the display module may further include a second group of insulating layers disposed between the first conductive pattern and the second conductive pattern, and the second conductive pattern and the sensing electrode may contact the second group of insulating layers.

[0022] In an embodiment, the insulating pattern may be provided in plurality, a plurality of holes may be provided in the first conductive pattern, and in a plan view, the plurality of holes may respectively overlap with the plurality of insulating patterns.

[0023] In embodiments, the insulating pattern may include a polymer.

[0024] In an embodiment, the display device may further include: an electronic component electrically connected to the display module; and an adhesive layer disposed between the display module and the electronic component, and a portion of the second conductive pattern overlapping the insulating pattern may contact the electronic component.

[0025] In an embodiment, the electronic component may include a substrate and a bump electrode disposed under the substrate, and the portion of the second conductive pattern overlapping the insulating pattern may contact the bump electrode.

[0026] In an embodiment, the electronic component may include a driver chip or a circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and together with the description are used to explain the principles of the inventive concept. In the accompanying drawings:

[0028] Figure 1 is a perspective view of an embodiment of a display device according to the inventive concept;

[0029] Figure 2A and Figure 2B is an exploded perspective view of an embodiment of a display device according to the inventive concept;

[0030] Figure 3 is a cross-sectional view of an embodiment of a display module according to the inventive concept;

[0031] Figure 4 is a plan view of an embodiment of a display panel according to the inventive concept;

[0032] Figure 5 is a cross-sectional view of an embodiment of a pixel according to the inventive concept;

[0033] Fig. 6A is a cross-sectional view of an embodiment of an input sensor according to the present inventive concept;

[0034] Figure 6B is a plan view of an embodiment of an input sensor according to the present invention;

[0035] Figure 6C According to the present invention, Figure 6B A cross-sectional view of an embodiment of a bridge pattern of an input sensor taken along line XX';

[0036] Figure 7 is an enlarged exploded perspective view of an embodiment of a pad area of ​​a display device according to the inventive concept;

[0037] Fig. 8A is a schematic plan view of an embodiment of a pad area according to the inventive concept;

[0038] FIG. 8B to FIG. 8E is a plan view showing an embodiment of some components within a pad region according to the inventive concept;

[0039] 9A to 9D Along the Fig. 8A A cross-sectional view of the pad area taken along line AA', line BB', line CC' and line DD';

[0040] Fig.10 is a cross-sectional view showing an embodiment of a combined structure of a display device according to the inventive concept;

[0041] FIG. 11A to FIG. 11C is a cross-sectional view illustrating an embodiment of some operations of a method of manufacturing a display device according to the inventive concept;

[0042] Fig. 12A is a schematic plan view of an embodiment of a pad area according to the inventive concept;

[0043] Fig. 12B is a plan view showing an embodiment of some components within a pad region according to the inventive concept; and

[0044] Fig.13 It is along Fig. 12A A cross-sectional view of the pad area taken along line EE'. DETAILED DESCRIPTION

[0045] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another element, the element can be directly set on, directly connected or coupled to the other element, or an intervening element can be set between the element and the other element.

[0046] The same reference numerals or symbols always refer to the same elements. In addition, in the drawings, the thickness, proportion and size of the elements are exaggerated for the effective description of the technical content. The term "and / or" includes all combinations of one or more of the related listed elements.

[0047] Although the terms "first", "second", etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element without departing from the scope of the present invention. The singular includes the plural unless the context clearly indicates otherwise.

[0048] In addition, terms such as "below", "lower", "above", and "upper" may be used to describe the relationship of elements shown in the drawings. It will be understood that these terms have relative concepts and are described based on the orientations depicted in the drawings.

[0049] It will be understood that when used in this specification, the terms “include” or “comprising” indicate the presence of stated features, integers, steps, operations, elements, parts or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts or combinations thereof.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0051] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0052] Figure 1 is a perspective view of an embodiment of a display device DD according to the inventive concept. Figure 2A and Figure 2B is an exploded perspective view of an embodiment of a display device DD according to the inventive concept.

[0053] For example, Figure 2B It shows Figure 2AThe bending area BA shown in FIG. 1 is in a bent state.

[0054] refer to Figure 1 In this specification, the display device DD is shown as a cellular phone terminal. The display device DD according to the present invention can be applied to small and medium-sized electronic devices such as tablet computers, car navigation systems, game consoles, and smart watches, as well as large electronic devices such as televisions and monitors.

[0055] The display device DD may have a quadrilateral shape (e.g., a rectangular shape) with long sides extending in a first direction DR1 and short sides extending in a second direction DR2 crossing the first direction DR1 in a plan view. However, the inventive concept is not limited thereto, and the display device DD may have various shapes such as a circular shape or other polygonal shapes in a plan view.

[0056] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, the wording "in a plan view" may refer to a view viewed in the third direction DR3.

[0057] The display device DD may be rigid or flexible. The term "flexible" refers to a bendable property and may include all of a fully foldable structure and a structure that can be bent at a few nanometers level. In an embodiment, for example, a flexible display device DD may include a curved display device, a rollable display device, or a foldable display device.

[0058] The display device DD may display an image IM through a display surface DD-IS. An icon image is shown as the image IM. The display surface DD-IS may be parallel to a surface defined by the first direction DR1 and the second direction DR2.

[0059] The display surface DD-IS may include a display area DD-DA in which the image IM is displayed and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area in which no image is displayed. However, the inventive concept is not limited thereto, and the non-display area DD-NDA may be adjacent to any side of the display area DD-DA or may be omitted.

[0060] refer to Figure 2A and Figure 2B , the display device DD may include a window WM, a display module DM and a receiving member BC.

[0061] The window WM may be disposed above the display module DM and transmit an image provided from the display module DM to the outside. The window WM may include a transmission area TA and a non-transmission area NTA. The transmission area TA may be connected to the display module DM. Figure 1The display area DD-DA shown in the figure overlaps, and may have a shape corresponding to the shape of the display area DD-DA. Although not shown, the window WM may include a base layer and a functional layer disposed on the base layer. The functional layer may include a protective layer or an anti-fingerprint layer, etc. The base layer of the window WM may include glass, sapphire or plastic, etc., or may be composed of glass, sapphire or plastic, etc. The base layer of the window WM may include an optically transparent insulating material. In an embodiment, for example, the base layer of the window WM may include a glass substrate or a plastic film, or may include a glass substrate and a plastic film bonded via an adhesive.

[0062] The non-transmitting area NTA can be Figure 1 The non-display area DD-NDA shown in FIG. 1 overlaps and may have a shape corresponding to the shape of the non-display area DD-NDA. The non-transmission area NTA may be an area having a relatively lower transmittance than the transmittance of the transmission area TA. The non-transmission area NTA may be defined by setting a frame pattern in a partial area of ​​the base layer of the window WM, and the transmission area TA may be defined as an area in which the frame pattern is not set. However, the inventive concept is not limited thereto, and the non-transmission area NTA may be omitted.

[0063] Although not shown, an anti-reflection layer may be provided between the window WM and the display module DM. The anti-reflection layer may reduce the reflection of external light incident from the outside of the display device DD. The anti-reflection layer may include a color filter. The color filter may have a predetermined arrangement. In an embodiment, for example, the color filter may be provided in consideration of the emission color of the pixel included in the display panel DP to be described later. In addition, the anti-reflection layer may further include a black matrix adjacent to the color filter.

[0064] In an embodiment of the inventive concept, the display module DM may include a display panel DP and an input sensor ISU.

[0065] The display panel DP may be any one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system ("MEMS") display panel, an electrowetting display panel, an organic light emitting display panel, an inorganic light emitting display panel, and a quantum dot light emitting display panel. However, embodiments of the present inventive concept may not be particularly limited thereto. Hereinafter, the display panel DP is described as an organic light emitting display panel.

[0066] The input sensor ISU may be any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensor ISU may be formed on the display panel DP through a continuous process, or may be separately manufactured and then attached to the upper side of the display panel DP via an adhesive layer, but is not limited to a specific embodiment.

[0067] The display device DD may further include a driver chip DC disposed on the display panel DP. The display device DD may further include a circuit board PB disposed on the display panel DP. In this embodiment, the circuit board PB may be a flexible circuit board, but is not limited thereto. In an embodiment, for example, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP and the main circuit board.

[0068] The driver chip DC may include driving elements (eg, data driving circuits) for driving the pixels of the display panel DP. Figure 2A A structure in which a driver chip DC is disposed (e.g., mounted) on a display panel DP is shown, but the inventive concept is not limited thereto. In an embodiment, for example, a driver chip DC may also be disposed (e.g., mounted) on a circuit board PB. In this embodiment, a driver chip DC and a circuit board PB directly disposed (e.g., mounted) on a display panel DP may be collectively referred to as electronic components. Hereinafter, the description of the combined structure of a display panel DP and a circuit board PB may also be similarly applied to other electronic components such as a driver chip DC other than the circuit board PB.

[0069] The display panel DP may include a bending area BA and first and second non-bending areas NBA1 and NBA2 spaced apart from each other in a first direction DR1, wherein the bending area BA is located between the first and second non-bending areas NBA1 and NBA2.

[0070] The bending area BA may be defined as an area in which the display panel DP is bent relative to an imaginary bending axis BX extending in the second direction DR2. The first non-bending area NBA1 may be defined as an area overlapping the transmission area TA, and the second non-bending area NBA2 may be defined as an area to which the circuit board PB is connected. When the bending area BA is bent relative to the bending axis BX, the circuit board PB and the driver chip DC may be bent toward the rear surface of the display panel DP and may be disposed below the rear surface of the display panel DP. Although not shown, additional components may be provided to compensate for the step caused by the bending area BA and formed between the circuit board PB and the rear surface of the display panel DP.

[0071] In an embodiment, in the second direction DR2, the width of the first non-bending area NBA1 may be greater than the width of the bending area BA and the width of the second non-bending area NBA2. However, the inventive concept is not limited thereto, and the bending area BA may be provided in a shape such that the width of the bending area BA in the second direction DR2 becomes narrower from the first non-bending area NBA1 toward the second non-bending area NBA2. The bending area BA is not limited to a specific embodiment.

[0072] like Figure 2BAs shown in FIG. 1 , a portion of the display panel DP is bent so that a circuit board PB electrically coupled to the display panel DP may be disposed on the rear surface of the display panel DP.

[0073] The receiving member BC may receive the display module DM and may be coupled to the window WM. The circuit board PB may be disposed at one end of the display panel DP and may be electrically connected to the display module DM. Figure 3 Although not shown, the display device DD may further include a main board, a camera module, a power module, or an electronic module disposed (eg, mounted) on the main board, etc.

[0074] The above-mentioned display device DD is shown as a cellular phone terminal, but in the present specification, the display device DD may be any device constituted by including two or more electronic components that are combined. The display panel DP and the driver chip DC disposed (e.g., installed) on the display panel DP correspond to different electronic components, respectively, and the display device DD may be constituted only by these components. The display panel DP and the circuit board PB disposed (e.g., installed) on the display panel DP correspond to different electronic components, respectively, and the display device DD may be constituted only by these components. In addition, the display device DD may be constituted only by a main board and an electronic module disposed (e.g., installed) on the main board. Hereinafter, the following description of the display device DD according to the present invention will mainly focus on the combination structure of the display panel DP and the driver chip DC disposed (e.g., installed) on the display panel DP.

[0075] Figure 3 is a cross-sectional view of an embodiment of a display module DM according to the inventive concept.

[0076] refer to Figure 3 The display panel DP may include a base layer BL, and a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL disposed on the base layer BL. The input sensor ISU may be disposed on the upper insulating layer TFL.

[0077] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may be Figure 1 The display area DD-DA or Figure 2A The transmission area TA shown in FIG. 1 corresponds to the transmission area TA, and the non-display area DP-NDA may correspond to the transmission area TA shown in FIG. Figure 1 The non-display area DD-NDA or Figure 2A Corresponding to the non-transmitting area NTA shown in .

[0078] The base layer BL may include at least one plastic film. As a flexible substrate, the base layer BL may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0079] The circuit element layer DP-CL may include a circuit element and at least one intermediate insulating layer. The intermediate insulating layer may include at least one intermediate inorganic layer or at least one intermediate organic layer. The circuit element may include a signal line or a pixel driving circuit, etc. The insulating layer, the semiconductor layer and the conductive layer are formed by a coating process or a deposition process, etc. Thereafter, the insulating layer, the semiconductor layer and the conductive layer may be selectively patterned by performing a photolithography process and an etching process. With this process, semiconductor patterns, conductive patterns, signal lines, etc. are formed. The patterns set in the same layer are formed by the same process. In the following, the wording "the pattern is formed by the same process" means that the pattern includes the same material and has the same stacking structure.

[0080] The display element layer DP-OLED may include a plurality of light emitting elements. The display element layer DP-OLED may further include an organic layer such as a pixel defining layer.

[0081] The upper insulating layer TFL may seal the display element layer DP-OLED. The upper insulating layer TFL may be disposed on the display element layer DP-OLED. The upper insulating layer TFL may overlap the display area DP-DA and the non-display area DP-NDA. The upper insulating layer TFL may overlap at least a portion of the non-display area DP-NDA. In an embodiment, for example, the upper insulating layer TFL may include a thin film encapsulation layer. The thin film encapsulation layer may have a stacked structure of an inorganic layer / organic layer / inorganic layer. The upper insulating layer TFL may protect the display element layer DP-OLED from moisture, oxygen, and foreign matter such as dust particles. However, the inventive concept is not limited thereto, and in addition to the thin film encapsulation layer, the upper insulating layer TFL may further include an additional insulating layer. In an embodiment, for example, an optical insulating layer for controlling a refractive index may be further included.

[0082] In an embodiment of the present inventive concept, a package substrate may be provided instead of the upper insulating layer TFL. In this case, the package substrate may face the base layer BL, and the circuit element layer DP-CL and the display element layer DP-OLED may be disposed between the package substrate and the base layer BL.

[0083] The input sensor ISU may be directly disposed on the display panel DP. In the present specification, the wording "component A is directly disposed on component B" means that no additional layer is disposed between component A and component B. In this embodiment, the input sensor ISU and the display panel DP may be manufactured by a continuous process. However, the idea of ​​the inventive concept is not limited thereto, and the input sensor ISU may be provided as a separate panel and coupled to the display panel DP via an adhesive layer. In an embodiment, the input sensor ISU may be omitted.

[0084] Figure 4 is a plan view of an embodiment of a display panel DP according to the inventive concept.

[0085] refer to Figure 4 , the display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, and a plurality of signal pads DP-PD.

[0086] The pixels PX may be arranged in the display area DP-DA. The pixels PX each include a light emitting element and a pixel driving circuit connected to the light emitting element. In an embodiment, the light emitting element may be an organic light emitting element. The gate driving circuit GDC sequentially outputs a gate signal to a plurality of gate lines GL to be described later. The transistors of the gate driving circuit GDC may be formed by the same process as the transistors of the pixels PX (e.g., a low temperature polycrystalline silicon ("LTPS") process or a low temperature polycrystalline oxide ("LTPO") process). The display panel DP may further include another driving circuit that provides a light emitting control signal to the pixels PX.

[0087] The signal line SGL may include a plurality of gate lines GL, a plurality of data lines DL, a power line PL, and a control signal line CSL. The plurality of gate lines GL may be connected to corresponding pixels PX among the pixels PX, and the plurality of data lines DL may be connected to corresponding pixels PX among the pixels PX, respectively. The power line PL may be connected to the pixel PX. The control signal line CSL may provide a control signal to the gate drive circuit GDC.

[0088] The signal line SGL may overlap the display area DP-DA and the non-display area DP-NDA. The signal lines SGL may each include a line portion LP. Although not shown, the signal line SGL may further include a pad portion. The line portion LP may overlap the display area DP-DA and the non-display area DP-NDA. The pad portion may be connected to a terminal of the line portion LP. In an alternative embodiment, the pad portion may extend from one end of the line portion LP. Fig. 8A The connection of the pad portion and the line portion LP is described in more detail in FIG.

[0089] The plurality of signal pads DP-PD may include first, second and third pads PD1, PD2 and PD3. A region where the first and second pads PD1 and PD2 are disposed may be defined as a first pad region PA1, and a region where the third pad PD3 is disposed may be defined as a second pad region PA2.

[0090] The first pad area PA1 may be Figure 2A The first pad area PA1 may include a first area B1 in which a first pad PD1 is disposed and a second area B2 in which a second pad PD2 is disposed. The first pad area PA1 and the second pad area PA2 may be disposed in the non-display area DP-NDA. The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in the first direction DR1. It is shown that one pad row is disposed in the first pad area PA1, but the inventive concept is not limited thereto. A plurality of pad rows may be disposed in the first pad area PA1.

[0091] The plurality of first pads PD1 may be respectively connected to corresponding data lines DL among the plurality of data lines DL. Although not shown, the first pad PD1 and the second pad PD2 may be electrically connected to each other. The second pad PD2 may be connected to the third pad PD3 via a connection signal line SCLn.

[0092] The circuit board PB may include a plurality of substrate bump electrodes PB-BP. The substrate bump electrodes PB-BP may be arranged along the second direction DR2. The substrate bump electrodes PB-BP of the circuit board PB may be connected to contact the third pads PD3 in the second pad area PA2.

[0093] Figure 5 is a cross-sectional view of an embodiment of one pixel PX according to the inventive concept.

[0094] refer to Figure 5 , the display area DP-DA may include a light emitting area PXA and a non-light emitting area NPXA. The pixels PX may each include a light emitting element OLED and a pixel driving circuit connected to the light emitting element OLED. In an embodiment, the pixel PX may include a transistor TR and an organic light emitting element (e.g., an organic light emitting diode) OLED.

[0095] Figure 5 One transistor TR is shown, but the present invention is not limited thereto. The pixel PX in the embodiment may include seven transistors and at least one capacitor, and the seven transistors and the capacitor may be electrically connected to each other. However, the number of transistors and the number of capacitors constituting the pixel PX are not limited to a specific embodiment.

[0096] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns or signal lines, etc. The insulating layers, semiconductor layers and conductive layers are formed by a coating process or a deposition process, etc. Thereafter, the insulating layers, semiconductor layers and conductive layers may be selectively patterned by performing a photolithography process and an etching process. In this way, semiconductor patterns, conductive patterns and signal lines included in the circuit element layer DP-CL and the display element layer DP-OLED are formed.

[0097] The base layer BL may include a synthetic resin film. The base layer BL may have a multilayer structure. In an embodiment, for example, the base layer BL may also have a three-layer structure of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc.

[0098] In embodiments, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, first to sixth insulating layers 10 to 60 , a transistor TR, a connection signal line SCLd, an upper electrode UE, a first connection electrode CNE1 , and a second connection electrode CNE2 .

[0099] At least one inorganic layer is disposed on the upper surface of the base layer BL. The inorganic layer may be formed into multiple layers. The barrier layer BRL may be disposed on the base layer BL. The buffer layer BFL may be disposed on the barrier layer BRL. The barrier layer BRL and the buffer layer BFL may be inorganic layers.

[0100] The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the semiconductor pattern is not limited thereto and may include amorphous silicon or metal oxide.

[0101] Figure 5 Only a portion of the semiconductor pattern is shown, but in the plan view, the semiconductor pattern may be further disposed in other regions of the pixel PX. The semiconductor pattern may be disposed across the pixel PX according to a predetermined pattern. The electrical characteristics of the semiconductor pattern vary depending on whether it is doped. The semiconductor pattern may include a first region and a second region. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant.

[0102] The first region has a higher conductivity than the conductivity of the second region and is basically used as an electrode or a signal line. The second region may have a lower doping concentration or may be a non-doped region. Basically, the second region corresponds to the active portion (or channel) of the transistor. That is, a portion of the semiconductor pattern may be the active portion of the transistor, another portion of the semiconductor pattern may be the source or drain of the transistor, and another portion of the semiconductor pattern may be a connecting electrode or a connecting signal line.

[0103] like Figure 5 As shown in FIG. 1 , the source S, the active portion A, and the drain D of the transistor TR are formed by a semiconductor pattern.

[0104] Figure 5 A portion of a connection signal line SCLd formed of a semiconductor pattern is shown. In an embodiment, the connection signal line SCLd may be electrically connected to a drain of any one transistor among transistors within the pixel PX.

[0105] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 may cover the semiconductor pattern. The first insulating layer 10 may overlap with the plurality of pixels PX in common. The gate G is disposed on the first insulating layer 10. The gate G may be a part of the metal pattern. The gate G may overlap with the active portion A. The gate G may be used as a mask during the process of doping the semiconductor pattern.

[0106] A second insulating layer 20 covering the gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may overlap with the plurality of pixels PX in common. An upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the gate G of the transistor TR. The upper electrode UE may be a portion of a metal pattern. A portion of the gate G and the upper electrode UE overlapping the portion may define a capacitor.

[0107] The third insulating layer 30 covering the upper electrode UE may be disposed on the second insulating layer 20. The first connection electrode CNE1 disposed on the third insulating layer 30 may be connected to the connection signal line SCLd via a contact hole CNT-1 passing through the first to third insulating layers 10 to 30.

[0108] A fourth insulating layer 40 covering the first connection electrode CNE1 may be disposed on the third insulating layer 30. The first to fourth insulating layers 10 to 40 may each be an inorganic layer and / or an organic layer, and may each have a single layer structure or a multi-layer structure.

[0109] In an alternative embodiment, the first connection electrode CNE1 may be disposed on the fourth insulating layer 40 and may be covered by the fifth insulating layer 50. In an alternative embodiment, in an embodiment of the present inventive concept, both of the first connection electrode disposed on the third insulating layer 30 and covered by the fourth insulating layer 40 and the first connection electrode disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50 may be included.

[0110] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0111] A sixth insulating layer 60 covering the second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CNE2 via a contact hole CNT-3 passing through the sixth insulating layer 60.

[0112] The circuit element layer DP-CL may include a plurality of connection electrodes connected to the transistor, and some of the plurality of connection electrodes may be disposed in different layers. Although not shown, the first connection electrode CNE1 may extend to be connected to the transistor TR. The positions of the plurality of connection electrodes are not limited to a specific embodiment.

[0113] The display element layer DP-OLED may include a pixel defining layer PDL and a light emitting element OLED. A pixel opening OPN may be defined in the pixel defining layer PDL. The pixel opening OPN of the pixel defining layer PDL may expose at least a portion of the first electrode AE. In an embodiment, the light emitting area PXA may be defined to correspond to some areas of the first electrode AE ​​exposed by the pixel opening OPN.

[0114] The hole control layer HCL may be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. The hole control layer HCL may include a hole transport layer, and may further include a hole injection layer. The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in an area corresponding to the pixel opening OPN. That is, the light emitting layer EML may be separately formed in each of the plurality of pixels PX. However, the inventive concept is not limited thereto, and the light emitting layer EML may be commonly formed in the plurality of pixels PX through an opening mask.

[0115] The electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly formed in a plurality of pixels PX through an open mask. The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an integral shape and may be commonly disposed in a plurality of pixels PX. The upper insulating layer TFL may be disposed on the second electrode CE. The upper insulating layer TFL may include a plurality of thin films.

[0116] Fig. 6A is a cross-sectional view of an embodiment of an input sensor ISU according to the inventive concept. Figure 6B is a plan view of an embodiment of an input sensor ISU according to the inventive concept. Figure 6C According to the present invention, Figure 6B FIG. 2 is a cross-sectional view of an embodiment of the bridge pattern CP2 of the input sensor ISU taken along line XX′.

[0117] The input sensor ISU may include a first insulating layer IS-IL1 (hereinafter, a first sensing insulating layer), a first conductive pattern layer IS-CL1, a second insulating layer IS-IL2 (hereinafter, a second sensing insulating layer), a second conductive pattern layer IS-CL2, and a third insulating layer IS-IL3 (hereinafter, a third sensing insulating layer). The first sensing insulating layer IS-IL1 may be directly disposed on the upper insulating layer TFL.

[0118] In an embodiment of the inventive concept, the first sensing insulating layer IS-IL1 and / or the third sensing insulating layer IS-IL3 may be omitted. When the first sensing insulating layer IS-IL1 is omitted, the first conductive pattern layer IS-CL1 may be disposed on the uppermost insulating layer of the upper insulating layer TFL. The third sensing insulating layer IS-IL3 may be replaced with an insulating layer of an anti-reflection member disposed on the adhesive layer or the input sensor ISU.

[0119] The first conductive pattern layer IS-CL1 may include a first conductive pattern, and the second conductive pattern layer IS-CL2 may include a second conductive pattern. Hereinafter, the same reference numerals or symbols are used for the first conductive pattern layer IS-CL1 and the first conductive pattern, and the same reference numerals or symbols are used for the second conductive pattern layer IS-CL2 and the second conductive pattern.

[0120] The first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 may each have a single-layer structure or a multilayer structure in which each layer is stacked along a third direction DR3. The conductive pattern having a multilayer structure may include at least two of a transparent conductive layer and a metal layer. The conductive pattern having a multilayer structure may include a metal layer containing different metals. The transparent conductive layer may include indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), indium tin zinc oxide ("ITZO"), poly (3,4-ethylenedioxythiophene) ("PEDOT"), metal nanowires and / or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum and / or any alloy thereof. A detailed description of the stacking structure of each of the first conductive pattern layer IS-CL1 and the second conductive pattern layer IS-CL2 will be provided later.

[0121] In this embodiment, the first to third sensing insulating layers IS-IL1, IS-IL2 and IS-IL3 may each include an inorganic layer or an organic layer. In this embodiment, the first to third sensing insulating layers IS-IL1, IS-IL2 and IS-IL3 may include an inorganic layer. The inorganic layer may include silicon oxide, silicon nitride or silicon oxynitride.

[0122] In an embodiment of the present inventive concept, at least one of the first to third sensing insulating layers IS-IL1, IS-IL2, and IS-IL3 may include an organic layer. In an embodiment, for example, the third sensing insulating layer IS-IL3 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0123] refer to Figure 6B and Figure 6C The input sensor ISU includes a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA may be respectively Figure 4 The display area DP-DA and the non-display area DP-NDA shown in the figure correspond to each other.

[0124] The input sensor ISU includes a plurality of sensing electrodes disposed in a sensing area IS-DA. The sensing electrodes may include first sensing electrodes E1-1 to E1-5 (hereinafter, first electrodes) and second sensing electrodes E2-1 to E2-4 (hereinafter, second electrodes) that cross each other and are insulated from each other. The input sensor ISU further includes a first signal line SL1 electrically connected to the first electrodes E1-1 to E1-5 disposed in a non-sensing area IS-NDA and a second signal line SL2 electrically connected to the second electrodes E2-1 to E2-4 disposed in the non-sensing area IS-NDA. The first electrodes E1-1 to E1-5, the second electrodes E2-1 to E2-4, the first signal line SL1 and the second signal line SL2 may be defined as reference electrodes. Fig. 6A A combination of the first conductive pattern IS-CL1 and the second conductive pattern IS-CL2 is described.

[0125] The first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include a plurality of conductive lines that cross each other and are insulated from each other. The plurality of conductive lines may define a plurality of openings, and the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may each have a mesh shape. The plurality of openings may be defined as being respectively connected to Figure 5 This corresponds to the plurality of pixel openings OPN of the pixel defining layer PDL shown in FIG.

[0126] Any one of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have an integral shape. In this embodiment, the first electrodes E1-1 to E1-5 having an integral shape are shown. The first electrodes E1-1 to E1-5 may include a sensing portion SP1 and a middle portion CP1. A portion of the second conductive pattern IS-CL2 may correspond to the first electrodes E1-1 to E1-5.

[0127] The second electrodes E2-1 to E2-4 may include a sensing pattern SP2 and a bridge pattern CP2 (or a connection pattern), respectively. Figure 6B and Figure 6C As shown in FIG. 1 , two adjacent sensing patterns SP2 may be connected to two bridge patterns CP2 via a contact hole CH-1 passing through the second sensing insulating layer IS-IL2, but the number of bridge patterns CP2 is not limited. A portion of the second conductive pattern IS-CL2 may correspond to the sensing pattern SP2. A portion of the first conductive pattern IS-CL1 may correspond to the bridge pattern CP2.

[0128] In this embodiment, the bridge pattern CP2 is described as being composed of Fig. 6A The first conductive pattern IS-CL1 shown in FIG. 1 is formed, and the first electrodes E1-1 to E1-5 and the sensing pattern SP2 are formed by Fig. 6AHowever, the present inventive concept is not limited thereto. In an embodiment, for example, the first electrodes E1-1 to E1-5 and the sensing pattern SP2 may be formed by Fig. 6A The first conductive pattern IS-CL1 shown in FIG. 1 is formed and the bridge pattern CP2 may be formed by Fig. 6A The second conductive pattern IS-CL2 shown in FIG. 1 is formed.

[0129] Any one of the first signal line SL1 and the second signal line SL2 receives a transmission signal for detecting an external input from an external circuit, and the remaining one of the first signal line SL1 and the second signal line SL2 transmits the capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 as a reception signal to the external circuit.

[0130] A portion of the second conductive pattern IS-CL2 may correspond to the first signal line SL1 and the second signal line SL2. The first signal line SL1 and the second signal line SL2 may have a multi-layer structure and may include a first layer line formed by the first conductive pattern IS-CL1 and a second layer line formed by the second conductive pattern IS-CL2. The first layer line and the second layer line may pass through the second sensing insulating layer IS-IL2 (reference Fig. 6A ) contact hole connection.

[0131] Figure 7 is an enlarged exploded perspective view of an embodiment of pad areas PA1 and PA2 of a display device DD according to the inventive concept. In an embodiment, for example, Figure 7 It is shown that the driver chip DC and the circuit board PB are decomposed from the display panel DP. Figure 7 The first pad PD1, the second pad PD2, the connection signal line SCLn and the third pad PD3 shown in FIG. Figure 4 The first pad PD1, the second pad PD2, the connection signal line SCLn, and the third pad PD3 shown in FIG. 1 are the same or similar, and therefore, descriptions thereof will be omitted or abbreviated.

[0132] refer to Figure 4 and Figure 7 , the driver chip DC may be bonded to the first pad area PA1 via the first adhesive layer CF1. The circuit board PB may be bonded to the second pad area PA2 via the second adhesive layer CF2. The first adhesive layer CF1 and the second adhesive layer CF2 may include a synthetic resin having adhesiveness. According to this embodiment, the first adhesive layer CF1 and the second adhesive layer CF2 may not include the conductive balls and may include only the synthetic resin having adhesiveness.

[0133] The driver chip DC may include a driver integrated circuit D-IC and a chip bump electrode DC-BP disposed (e.g., mounted) in the driver chip DC. The driver integrated circuit D-IC may include an upper surface DC-US and a lower surface DC-DS, and the lower surface DC-DS may be a surface facing the first pad PD1 and the second pad PD2. The chip bump electrode DC-BP may be disposed on the lower surface DC-DS of the driver integrated circuit D-IC.

[0134] The chip bump electrode DC-BP may include a first bump BP1 electrically connected to the corresponding first pad PD1 and a second bump BP2 electrically connected to the corresponding second pad PD2. The first bump BP1 may be disposed along the second direction DR2, and the second bump BP2 may be spaced apart from the first bump BP1 in the first direction DR1 and may be disposed along the second direction DR2.

[0135] The driver chip DC may receive a first signal from the outside via the second pad PD2 and the second bump BP2. The driver chip DC may provide a second signal generated based on the first signal to the first pad PD1 via the first bump BP1. In an embodiment, for example, the driver chip DC may include a data driving circuit. The first signal may be an image signal as a digital signal applied from the outside, and the second signal may be a data signal as an analog signal. The driver chip DC may generate an analog voltage corresponding to the grayscale value of the image signal. The data signal may be transmitted via the first pad PD2. Figure 4 The data line DL shown in FIG. 1 is provided to the pixel PX (refer to FIG. 1 ). Figure 4 ).

[0136] Although not shown, the first bump BP1 and the second bump BP2 may each have a shape protruding from the lower surface DC-DS of the driving integrated circuit D-IC and may be exposed to the outside. When the first adhesive layer CF1 is cured, the first pad PD1 and the first bump BP1 may be fixed while in contact with each other, and the second pad PD2 and the second bump BP2 may be fixed while in contact with each other.

[0137] The circuit board PB may include a base layer P-BS and a substrate bump electrode PB-BP disposed (e.g., mounted) in the circuit board PB. The base layer P-BS may include an upper surface PB-US and a lower surface PB-DS, and the lower surface PB-DS may be a surface facing the third pad PD3. The substrate bump electrode PB-BP may be disposed on the lower surface PB-DS of the base layer P-BS. The substrate bump electrodes PB-BP may be electrically connected to the third pad PD3, respectively. The substrate bump electrodes PB-BP may be arranged along the second direction DR2. The circuit board PB may provide video signals, driving voltages, and other control signals to the driver chip DC.

[0138] Although not shown, the substrate bump electrode PB-BP may have a shape protruding from the lower surface PB-DS of the base layer P-BS and may be exposed to the outside. When the second adhesive layer CF2 is cured, the third pad PD3 and the substrate bump electrode PB-BP may be fixed in a state of contacting each other.

[0139] The electronic component may include a substrate and a bump electrode disposed on the lower side of the substrate. When the electronic component corresponds to a driver chip DC, the substrate may correspond to a driver integrated circuit D-IC of the driver chip DC, and the bump electrode may correspond to a chip bump electrode DC-BP. In an alternative embodiment, when the electronic component corresponds to a circuit board PB, the substrate may correspond to a base layer P-BS of the circuit board PB, and the bump electrode may correspond to a substrate bump electrode PB-BP.

[0140] Fig. 8A is a schematic plan view of an embodiment of pad areas PA1 and PA2 according to the inventive concept. FIG. 8B to FIG. 8E is a plan view illustrating an embodiment of some components within the pad areas PA1 and PA2 according to the inventive concept.

[0141] Fig. 8A The signal pad DP-PD (or signal pad structure) shown in FIG. Figure 4 and Figure 7 Any one of the described first to third pads PD1 to PD3. Fig. 8A The data line DL including the pad portion DL-E and the line portion DL-S having different widths is shown as an embodiment of the signal line, but the inventive concept is not limited thereto. The signal line may be other signal lines other than the data line DL, and the pad portion DL-E and the line portion DL-S may each have a uniform width.

[0142] refer to FIG. 8A to FIG. 8E , the signal pad DP-PD may include a first conductive pattern CL1 connected to the data line DL, a second conductive pattern CL2 connected to the first conductive pattern CL1, and at least one insulating pattern SP overlapping the second conductive pattern CL2 in a plan view. FIG. 8A to FIG. 8E The signal pads DP-PD including four insulating patterns SP are shown. The first conductive pattern CL1 may be connected to the pad portion DL-E of the data line DL.

[0143] The pad portion DL-E, the first conductive pattern CL1, and the second conductive pattern CL2 may be separated depending on whether an insulating layer is disposed therebetween or whether they are connected via contact holes OP1c and OP2c. In this specification, the insulating layer disposed between the pad portion DL-E and the first conductive pattern CL1 is also referred to as a first group of insulating layers IG1, and the insulating layer disposed between the first conductive pattern CL1 and the second conductive pattern CL2 is also referred to as a second group of insulating layers IG2.

[0144] The insulating patterns SP may be disposed to overlap the pad portion DL-E. The insulating patterns SP may each include a polymer. The insulating patterns SP may each include a thermosetting polymer. However, the inventive concept is not limited thereto, and the insulating patterns SP may each include a thermoplastic polymer.

[0145] The insulation patterns SP may be aligned in the first direction DR1. FIG. 8A to FIG. 8E It is shown that the insulation patterns SP are aligned in columns (or rows), but the inventive concept is not limited thereto. In an embodiment, for example, the insulation patterns SP may have an arrangement form such that the insulation patterns SP are aligned in both the first direction DR1 and the second direction DR2.

[0146] FIG. 8A to FIG. 8E The insulating pattern SP having a square shape in a plan view is shown, but the inventive concept is not limited thereto. The shape of the insulating pattern SP may be changed to a circular shape or an elliptical shape, etc. In addition, the insulating pattern SP may have other quadrilateral shapes (e.g., a rectangular shape extending in one direction) or other polygonal shapes. In addition, the insulating patterns SP are not limited to all having the same shape.

[0147] Figure 8B It is shown for describing the first group of insulating layers IG1 , and for convenience of description, the data lines DL and the insulating patterns SP are also shown together.

[0148] like Figure 8B As shown in FIG. 1 , at least one first contact hole OP1c and at least one lower hole OP1r may be defined in the first group insulating layer IG1. The first contact hole OP1c may also be referred to as a first contact opening. The lower hole OP1r may also be referred to as a first reinforcement hole, a first reinforcement opening, or a first compensation hole. Figure 8B It is shown that three first contact holes OP1c and four lower holes OP1r are defined in the first group insulating layer IG1.

[0149] The first contact hole OP1c may overlap a partial area of ​​the pad portion DL-E. The first group insulating layer IG1 may expose a partial area of ​​the pad portion DL-E through the first contact hole OP1c. The first contact hole OP1c may be spaced apart from the insulating pattern SP. That is, in a plan view, the insulating pattern SP may be disposed outside the first contact hole OP1c.

[0150] The pad portion DL-E may extend in the first direction DR1, and the first contact holes OP1c may be aligned in the first direction DR1. In this embodiment, an insulating pattern SP may be disposed between the first contact holes OP1c. FIG. 8A to FIG. 8E It is shown that two insulating patterns SP aligned in the first direction DR1 are disposed between adjacent first contact holes OP1c. However, the arrangement of the insulating patterns SP and the first contact holes OP1c is not limited thereto. In an embodiment, for example, the first contact holes OP1c may be disposed on one side in the first direction DR1, and the insulating patterns SP may be disposed on the opposite side in the first direction DR1. In addition, the number of the first contact holes OP1c and also the number of the insulating patterns SP are not limited to a specific embodiment.

[0151] The lower holes OP1r may overlap the insulating patterns SP, respectively. In a plan view, the lower holes OP1r may be defined to have a shape corresponding to the shape of the insulating pattern SP. For ease of description, Figure 8B It is shown that the inner edge of the lower hole OP1r of the first group insulation layer IG1 is spaced apart from the insulation pattern SP. However, the insulation pattern SP may be substantially in contact with the inner edge of the lower hole OP1r of the first group insulation layer IG1. The lower hole OP1r and the insulation pattern SP corresponding to each other may have substantially the same plane area. The insulation patterns SP may each be surrounded by the first group insulation layer IG1.

[0152] Figure 8C It is shown for describing the second group insulating layer IG2, and for the convenience of description, the data line DL and the insulating pattern SP are also shown together. In addition, for the convenience of description, the first contact hole OP1c and the lower hole OP1r are also shown together.

[0153] like Figure 8C As shown in FIG. 1 , the second contact hole OP2c may be defined in the second group insulating layer IG2. The second contact hole OP2c may also be referred to as a second contact opening. The second contact hole OP2c may overlap at least a portion of the pad portion DL-E. Figure 8CThe second contact hole OP2c is shown to overlap the entirety of the pad portion DL-E, but the inventive concept is not limited thereto. In an embodiment, for example, the second group insulating layer IG2 may be disposed to overlap the outer portion of the pad portion DL-E, and the second contact hole OP2c may be defined to overlap the inner portion of the pad portion DL-E.

[0154] In a plan view, the first contact hole OP1c may be disposed within the second contact hole OP2c. In a plan view, the insulating pattern SP may be disposed within the second contact hole OP2c.

[0155] Fig.8D The first conductive pattern CL1 is shown for the purpose of describing the first conductive pattern CL1, and for the convenience of description, the data line DL and the insulating pattern SP are also shown together. In addition, for the convenience of description, the first contact hole OP1c and the second contact hole OP2c are also shown together.

[0156] like Fig.8D As shown in FIG. 1 , at least one hole OP2r may be defined in the first conductive pattern CL1. The hole OP2r may also be referred to as a second reinforcement hole, a second reinforcement opening, or a second compensation hole. Fig.8D It is shown that four holes OP2r are defined in the first conductive pattern CL1.

[0157] The holes OP2r may overlap the insulating patterns SP, respectively. In a plan view, the holes OP2r may be defined to have a shape corresponding to the shape of the insulating patterns SP. For ease of description, Fig.8D It is shown that the inner edge of the defining hole OP2r of the first conductive pattern CL1 is spaced apart from the insulating pattern SP. However, the insulating pattern SP may be substantially in contact with the inner edge of the defining hole OP2r of the first conductive pattern CL1. The hole OP2r and the insulating pattern SP corresponding to each other may have substantially the same plane area. The insulating patterns SP may each be surrounded by the first conductive pattern CL1. The hole OP2r may overlap with the lower hole OP1r of the first group insulating layer IG1, respectively.

[0158] The first conductive pattern CL1 may overlap the first contact hole OP1c. The first conductive pattern CL1 may be connected to the pad portion DL-E via the first contact hole OP1c.

[0159] Fig. 8E The second conductive pattern CL2 is shown for describing the second conductive pattern CL2, and for the convenience of description, the data line DL and the insulating pattern SP are also shown together. In addition, for the convenience of description, the first and second contact holes OP1c and OP2c, the lower hole OP1r, and the hole OP2r are also shown together.

[0160] like Fig. 8EAs shown in FIG. 1 , the second conductive pattern CL2 may overlap the second contact hole OP2c. The second conductive pattern CL2 may be connected to the first conductive pattern CL1 via the second contact hole OP2c.

[0161] The second conductive pattern CL2 may overlap the insulating pattern SP, the lower hole OP1r, and the hole OP2r. The second conductive pattern CL2 may cover the insulating pattern SP.

[0162] 9A to 9D Along the Fig. 8A 2 is a cross-sectional view of the pad areas PA1 and PA2 taken along the lines AA′, BB′, CC′, and DD′. Fig.10 is a cross-sectional view illustrating a coupling structure of a display device DD according to the inventive concept. Fig.9A It is along Fig. 8A A cross-sectional view of the pad areas PA1 and PA2 taken along the line AA', Fig. 9B It is along Fig. 8A A cross-sectional view of the pad areas PA1 and PA2 taken along the line BB', Fig. 9C It is along Fig. 8A A cross-sectional view of the pad areas PA1 and PA2 taken along line CC', and Fig.9D It is along Fig. 8A The same / similar reference numerals or symbols are used for the cross-sectional view of the pad areas PA1 and PA2 taken along the line DD'. Figures 1 to 8E The same / similar parts as those described in the drawings will be omitted, and the following description will mainly focus on the differences.

[0163] refer to 8A to 9D The pad portion DL-E may be disposed on the first insulating layer 10. The pad portion DL-E may be Figure 5 The gate G shown in FIG. 1 is arranged in the same layer. The pad portion DL-E and the gate G (refer to Figure 5 ) can be formed by the same process. The pad portion DL-E may include the same material as that of the gate G.

[0164] However, the position of the pad portion DL-E is not limited thereto. Figure 5 The upper electrode UE shown in the figure may be arranged in the same layer, may include the same material and also have the same stacking structure. A portion of the plurality of signal lines may be connected to the gate G (reference Figure 5 ) can be formed by the same process as the process of the upper electrode UE (reference Figure 5 ) is formed by the same process as the process of FIG.

[0165] The data line DL may be disposed in one layer and may have an integral shape, but the inventive concept is not limited thereto. One data line DL may include a plurality of portions disposed in different layers. In an embodiment, for example, the line portion DL-S may include two or more portions.

[0166] The first conductive pattern CL1 may be disposed on the fourth insulating layer 40. The first conductive pattern CL1 may be connected to the pad portion DL-E via a first contact hole OP1c passing through the second to fourth insulating layers 20, 30, and 40. Figure 5 The second to fourth insulating layers 20, 30 and 40 of the display area DP-DA shown in FIG. 1 are formed by the same process as the process of forming the second to fourth insulating layers 20, 30 and 40 of the display area DP-DA shown in FIG. 1 . In this embodiment, the second to fourth insulating layers 20, 30 and 40 may be defined as a first group of insulating layers IG1. The second insulating layer 20 may also be referred to as a lower insulating layer, the third insulating layer 30 may also be referred to as an intermediate insulating layer, and the fourth insulating layer 40 may also be referred to as an upper insulating layer. The stacking structure of the first group of insulating layers IG1 may be based on the circuit element layer DP-CL (reference Figure 5 In an embodiment, the first contact holes OP1c may be defined in an insulating layer whose number is greater or less than that of the second to fourth insulating layers 20, 30, and 40.

[0167] The first conductive pattern CL1 and the pad portion DL-E may be separated by a first group of insulating layers IG1 (eg, second to fourth insulating layers 20 , 30 , and 40 ) disposed therebetween.

[0168] The first conductive pattern CL1 may include a first layer CL11 and a second layer CL12. The first layer CL11 and the second layer CL12 may be defined as one conductive pattern because an insulating layer is not disposed between the first layer CL11 and the second layer CL12. The first layer CL11 and the second layer CL12 are not connected via a contact hole. 9A to 9D 1 shows an embodiment in which the first conductive pattern CL1 is disposed on the fourth insulating layer 40. In an embodiment, the first conductive pattern CL1 may be disposed on the third insulating layer 30. In this case, the first layer CL11 may be connected to the first connection electrode CNE1 (refer to FIG. 1 ) by Figure 5 ) is formed by the same process as that of the second connection electrode CNE2 (reference Figure 5 ) is formed by the same process as the process of the first layer CL11 and the first connection electrode CNE1 (reference Figure 5 ) may include the same material, and the second layer CL12 and the second connection electrode CNE2 (reference Figure 5 ) may include the same material. The fourth insulating layer 40 may not be provided in the pad areas PA1 and PA2. Figure 5 The fifth insulating layer 50 and the sixth insulating layer 60 shown in FIG. 1 may not be provided in the pad areas PA1 and PA2. In an embodiment of the inventive concept, any one of the first layer CL11 and the second layer CL12 may be omitted. In an embodiment of the inventive concept, the first conductive pattern CL1 may be omitted.

[0169] 9A to 9C It is shown that the edge of the second layer CL12 is disposed outside the edge of the first layer CL11 and covers the edge of the first layer CL11, but the inventive concept is not limited thereto. In an embodiment, for example, the first layer CL11 and the second layer CL12 may have substantially the same planar area, and the edge of the second layer CL12 may also be substantially aligned with the edge of the first layer CL11.

[0170] The second conductive pattern CL2 may be provided in the input sensor ISU (refer to Fig. 6A The second conductive pattern CL2 may be formed by contacting the second sensing insulating layer IS-IL2. Fig. 6A The second conductive pattern layer IS-CL2 and Figure 6C The sensing portion SP1 and the sensing pattern SP2 are formed by the same process. Fig. 8A It is shown that the second conductive pattern CL2 has a larger plane area than the first conductive pattern CL1, and 9A to 9C It is shown that the edge of the second conductive pattern CL2 is disposed outside the edge of the first conductive pattern CL1. However, the inventive concept is not limited thereto. In an embodiment, for example, the second conductive pattern CL2 and the first conductive pattern CL1 may have substantially the same planar area, and the edge of the second conductive pattern CL2 and the edge of the first conductive pattern CL1 may also be aligned.

[0171] The second conductive pattern CL2 may pass through the input sensor ISU (refer to Fig. 6A ) of the first sensing insulating layer IS-IL1 and the input sensor ISU (reference Fig. 6A ) is connected to the first conductive pattern CL1 by the second contact hole OP2c of the second sensing insulating layer IS-IL2. In this embodiment, the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be defined as a second group insulating layer IG2. The first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be connected to the first conductive pattern CL1. Figure 6B 1 and 2. The sensing area IS-DA and the non-sensing area IS-NDA shown in FIG. 1 overlap. Accordingly, the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may overlap the pad areas PA1 and PA2.

[0172] The second conductive pattern CL2 and the first conductive pattern CL1 may be separated by a second group insulating layer IG2 (e.g., a first sensing insulating layer IS-IL1 and a second sensing insulating layer IS-IL2) disposed therebetween. In an embodiment of the inventive concept, any one of the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be omitted.

[0173] like Fig.9A and Fig.9D As shown in FIG. 1 , the first conductive pattern CL1 may contact the pad portion DL-E via the first contact hole OP1c. The area of ​​the first contact hole OP1c may determine the contact area between the first conductive pattern CL1 and the pad portion DL-E. 9A to 9D As shown in FIG. 2 , a portion of the first conductive pattern CL1 that does not overlap the first contact hole OP1 c may be disposed on the first group insulating layer IG1 (eg, the fourth insulating layer 40 ).

[0174] like 9A to 9D As shown in FIG. 1 , a portion of the second conductive pattern CL2 overlapping with the second contact hole OP2c may be disposed on the first conductive pattern CL1. The second conductive pattern CL2 may contact the first conductive pattern CL1 via the second contact hole OP2c. A portion of the second conductive pattern CL2 not overlapping with the second contact hole OP2c may be disposed on the second group insulating layer IG2 (e.g., the second sensing insulating layer IS-IL2). The second group insulating layer IG2 (e.g., the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2) may be disposed between a portion of the second conductive pattern CL2 not overlapping with the second contact hole OP2c and a portion of the first conductive pattern CL1.

[0175] like Fig. 9C and Fig.9D As shown in FIG. 1 , the portion of the second conductive pattern CL2 overlapping the second contact hole OP2c may include a portion overlapping the insulating pattern SP (or the first compensation hole OP1r and the second compensation hole OP2r). In the cross-sectional view, the insulating pattern SP may be disposed between the pad portion DL-E and the second conductive pattern CL2. The portion of the second conductive pattern CL2 overlapping the insulating pattern SP may not contact the first conductive pattern CL1 and may be spaced apart from the first conductive pattern CL1.

[0176] The insulating pattern SP may be directly disposed on the pad portion DL-E. Fig.9DAs shown in FIG. 1 , a portion of the pad portion DL-E overlapping with the first contact hole OP1c may contact the first conductive pattern CL1. A portion of the pad portion DL-E not overlapping with the first contact hole OP1c and overlapping with the lower hole OP1r and the hole OP2r may contact the insulating pattern SP, and a portion of the pad portion DL-E not overlapping with the first contact hole OP1c, the lower hole OP1r, and the hole OP2r may contact the first group insulating layer IG1.

[0177] The insulating pattern SP can be Figure 5 The insulating pattern SP may be formed by the same process as that of at least any one of the sixth insulating layer 60 and the pixel defining layer PDL shown in FIG. Figure 5 According to this embodiment, an additional process for forming the insulating pattern SP is not required.

[0178] In this embodiment, the lower hole OP1r defined in the first group insulation layer IG1 may include a first lower hole OP11r defined in the second insulation layer 20, a second lower hole OP12r defined in the third insulation layer 30, and a third lower hole OP13r defined in the fourth insulation layer 40. The first to third lower holes OP11r, OP12r, and OP13r may define an integral open space. The first to third lower holes OP11r, OP12r, and OP13r may be defined by the inner side surfaces of the second to fourth insulation layers 20, 30, and 40, respectively, and the inner side surfaces of the second to fourth insulation layers 20, 30, and 40 may be substantially aligned. The insulation pattern SP may be disposed to pass through the first group insulation layer IG1 via the lower hole OP1r.

[0179] In this embodiment, the hole OP2r defined in the first conductive pattern CL1 may include a first hole OP21r defined in the first layer CL11 and a second hole OP22r defined in the second layer CL12. The first hole OP21r and the second hole OP22r may define an integral open space. The first hole OP21r and the second hole OP22r may be defined by the inner side surfaces of the first layer CL11 and the second layer CL12, respectively, and the inner side surfaces of the first layer CL11 and the second layer CL12 may be substantially aligned. The hole OP2r and the lower hole OP1r may define an integral open space. The plane area of ​​the hole OP2r may be substantially the same as the plane area of ​​the lower hole OP1r. The insulating pattern SP may be disposed to pass through the first conductive pattern CL1 via the hole OP2r.

[0180] A portion of the side surface SP-SS of the insulating pattern SP may be surrounded by the first group insulating layer IG1 and the first conductive pattern CL1. A portion of the side surface SP-SS of the insulating pattern SP may contact the first group insulating layer IG1 and the first conductive pattern CL1. The remaining portion of the side surface SP-SS of the insulating pattern SP and the upper surface SP-US of the insulating pattern SP may be surrounded by the second conductive pattern CL2. The remaining portion of the side surface SP-SS of the insulating pattern SP and the upper surface SP-US of the insulating pattern SP may contact the second conductive pattern CL2.

[0181] In a cross-sectional view, the insulating pattern SP may have a quadrangular shape (eg, a rectangular shape). However, the inventive concept is not limited thereto, and the insulating pattern SP may have a trapezoidal shape having an inclined side surface.

[0182] exist Fig.10 , a driver chip DC is shown as an electronic component. Fig.10 The chip bump electrode DC-BP of the driver chip DC is shown (reference Figure 7 ) contacts the contact portion CL2-C of the second conductive pattern CL2. The contact portion CL2-C of the second conductive pattern CL2 may protrude from the second sensing insulating layer IS-IL2 due to the insulating pattern SP compared to other portions of the second conductive pattern CL2. The contact portion CL2-C of the second conductive pattern CL2 may protrude from the first conductive pattern CL1 toward a direction away from the pad portion DL-E.

[0183] Due to the bonding pressure, the first bump BP1 of the driver chip DC may pass through the first adhesive layer CF1 to contact the contact portion CL2-C of the second conductive pattern CL2. The first adhesive layer CF1 before being cured may have a viscosity lower than that of the anisotropic conductive film. In order to facilitate alignment of the conductive balls, the anisotropic conductive film has a relatively high viscosity.

[0184] Since the contact portion CL2-C of the second conductive pattern CL2 protrudes toward the first bump BP1, the contact portion CL2-C and the first bump BP1 may be in close contact with each other, and thus, the contact resistance between the contact portion CL2-C and the first bump BP1 may be reduced. The conductive ball is omitted, and the proximity between the signal pad DP-PD and the first bump BP1 is improved. Thus, the bonding pressure may be reduced. Due to the reduced bonding pressure, the damage to the display panel DP (reference) during the bonding process may be reduced. Figure 7 ) or physical damage to electronic components.

[0185] In an embodiment, a portion of the insulating pattern SP may be surrounded by the first conductive pattern CL1 and the first group of insulating layers IG1, and during the process of applying the bonding pressure, the side portion of a portion of the insulating pattern SP may be reinforced via the first conductive pattern CL1 and the first group of insulating layers IG1. More specifically, in the portion of the insulating pattern SP surrounded by the first conductive pattern CL1 and the first group of insulating layers IG1, the degree of deformation caused by the bonding pressure may be relatively small. Accordingly, the bonding pressure may be centrally transmitted to the portion of the insulating pattern SP protruding from the first conductive pattern CL1. In this way, the adhesion between the second conductive pattern CL2 and the insulating pattern SP is improved, and therefore, the second conductive pattern CL2 may further be in close contact with the bump electrode (e.g., the first bump BP1). In addition, the protruding portion of the insulating pattern SP may be greatly deformed due to the bonding pressure, and therefore, the contact area between the second conductive pattern CL2 and the bump electrode may be increased. Therefore, a display device DD in which bonding defects and contact resistance are reduced may be provided.

[0186] When the insulating pattern has a height of a predetermined level or less when the side portion of a part of the insulating pattern is not reinforced, the bonding pressure is transmitted more centrally, and therefore, the second conductive pattern can be in close contact with the bump electrode, so that the contact area between the second conductive pattern and the bump electrode can become sufficient. When the insulating pattern has a height greater than a predetermined level when the side portion of a part of the insulating pattern is not reinforced, during the process of applying the bonding pressure, the central portion may be deformed due to the insufficient supporting force of the insulating pattern. In this case, for example, the insulating pattern may not only be pressed vertically, but also be bent laterally. In this case, the adhesion between the insulating pattern and the second conductive pattern is reduced, and therefore, bonding defects may occur. In addition, the contact area between the second conductive pattern and the bump electrode becomes insufficient, resulting in an increase in contact resistance. In this case, for example, the height of the predetermined level may be about 1 micron. However, since precise manufacturing of the insulating pattern is required to meet the predetermined level or lower height, there may be difficulties in performing the process.

[0187] According to the inventive concept, although the insulating pattern SP has a first height h1, the portion to which the bonding pressure is substantially transmitted may have a second height h2 that is smaller than the first height h1. Therefore, when the second height h2 satisfies a predetermined level or a lower height, a bonding structure with reduced bonding defects and contact resistance may be achieved. In addition, when the insulating pattern SP is manufactured to have a first height h1 that is greater than the second height h2, problems generated during the process may be overcome. In an embodiment, the first height h1 may be approximately three times the second height h2. Therefore, not only may difficulties in performing the process be resolved, but a display device DD having improved bonding reliability may also be provided.

[0188] FIG. 11A to FIG. 11C is a cross-sectional view illustrating an embodiment of some operations of a method for manufacturing a display device according to the inventive concept. The same / similar reference numerals or symbols are used to FIG. 8A to FIG. 10 The same / similar parts as those described in the drawings will be omitted, and the following description will mainly focus on the differences.

[0189] refer to Fig.11A , the method of manufacturing a display device in an embodiment of the inventive concept may include depositing a first group insulating layer IG1 and depositing a first preliminary conductive pattern CL1 -I.

[0190] The first insulating layer group IG1 may be disposed on the first insulating layer 10. The first insulating layer group IG1 may be formed to cover the pad portion DL-E. In this embodiment, the deposition of the first insulating layer group IG1 may include depositing the second insulating layer 20, depositing the third insulating layer 30 on the second insulating layer 20, and depositing the fourth insulating layer 40 on the third insulating layer 30.

[0191] The first preliminary conductive pattern CL1-I may be deposited on the first group insulating layer IG1. The first preliminary conductive pattern CL1-I may be a conductive layer. In this embodiment, the deposition of the first preliminary conductive pattern CL1-I may include depositing a first layer CL11 and depositing a second layer CL12 on the first layer CL11.

[0192] refer to Fig.11A and Fig. 11B , the method of manufacturing a display device in an embodiment of the inventive concept may include forming a first conductive pattern CL1 having a hole OP2r defined therein by patterning the first preliminary conductive pattern CL1-I. The formation of the first conductive pattern CL1 may be performed by a photolithography process and an etching process.

[0193] In this embodiment, the first conductive pattern CL1 may include a first layer CL11 and a second layer CL12. The first hole OP21r may be defined in the first layer CL11, the second hole OP22r may be defined in the second layer CL12, and the first hole OP21r and the second hole OP22r may define an integral open space. In this embodiment, the hole OP2r may correspond to the integral open space defined by the first hole OP21r and the second hole OP22r.

[0194] Furthermore, the method of manufacturing a display device in the embodiment of the inventive concept may include forming a lower hole OP1r in the first group insulating layer IG1.

[0195] The first lower hole OP11r may be defined in the second insulating layer 20, the second lower hole OP12r may be defined in the third insulating layer 30, the third lower hole OP13r may be defined in the fourth insulating layer 40, and the first to third lower holes OP11r, OP12r, and OP13r may define an integrated open space. In this embodiment, the lower hole OP1r may correspond to the integrated open space defined by the first to third lower holes OP11r, OP12r, and OP13r. In addition, the lower hole OP1r and the hole OP2r may define an integrated open space. The formation of the lower hole OP1r may be performed by a photolithography process and an etching process.

[0196] Since a relatively large hole and a relatively small pattern may be formed due to equipment tolerance in an actual process, the hole may be designed to be smaller than the set target width value, and the pattern may be designed to be larger than the set target width value. Considering the above situation, when it is set to manufacture the insulating pattern SP having the first width (reference Fig. 11C ), the lower hole OP1r and the hole OP2r may each be set to have a second width that is approximately 0.1 μm to approximately 1.0 μm smaller than the first width.

[0197] refer to Fig. 11C , the method of manufacturing a display device in an embodiment of the inventive concept may include forming an insulating pattern SP.

[0198] In this embodiment, the formation of the insulating pattern SP may be performed after the first conductive pattern CL1 is formed. A portion of the insulating pattern SP may be disposed in the lower hole OP1r and the hole OP2r. The insulating pattern SP may be disposed in the lower hole OP1r and the hole OP2r, and may pass through the first group insulating layer IG1 and the first conductive pattern CL1. In addition, the insulating pattern SP may be formed to protrude further to the upper side from the first conductive pattern CL1. The portion of the insulating pattern SP protruding from the first conductive pattern CL1 may provide a second conductive pattern CL2 (reference pattern CL2) to be formed later. Fig.10 ) contact part CL2-C (reference Fig.10 ).

[0199] Fig. 12A is a schematic plan view of an embodiment of pad areas PA1 and PA2 according to the inventive concept. Fig. 12B is a plan view illustrating an embodiment of some components within the pad areas PA1 and PA2 according to the inventive concept. Fig. 12B The first conductive pattern CL1 -A is shown for describing the first conductive pattern CL1 -A, and for convenience of description, the data line DL, the insulating pattern SP, the first contact hole OP1 c and the second contact hole OP2 c are also shown together. Fig.13 It is along Fig. 12A The same / similar reference numerals or symbols are used for the cross-sectional view of the pad areas PA1 and PA2 taken along the line EE'. Figures 1 to 11C The same / similar parts as those described in the drawings will be omitted, and the following description will mainly focus on the differences.

[0200] refer to Fig. 12A and Fig. 12B , the signal pad DP-PDA may include a first conductive pattern CL1-A, a second conductive pattern CL2, and at least one insulating pattern SP. The first conductive pattern CL1-A according to this embodiment may include at least one contact portion TP and at least one recess portion RP. Fig. 12A and Fig. 12B It is shown that two contact portions TP and one recessed portion RP are included.

[0201] The contact portions TP may each be a portion overlapping at least a portion of the first contact hole OP1c. In an embodiment, the contact portion TP may include a first contact portion TP1 and a second contact portion TP2. The first contact portion TP1 may be a portion overlapping the first contact hole OP1c disposed on one side in the first direction DR1 among the first contact holes OP1c, and the second contact portion TP2 may be a portion overlapping the first contact hole OP1c disposed on the opposite side in the first direction DR1 among the first contact holes OP1c.

[0202] The recessed portion RP may be a portion overlapping the insulating pattern SP. In an embodiment, the recessed portion RP may be disposed between the first contact portion TP1 and the second contact portion TP2, and the first contact portion TP1 and the second contact portion TP2 may be spaced apart from each other in the first direction DR1 with the recessed portion RP therebetween. The recessed portion RP may extend from the first contact portion TP1 to the second contact portion TP2 in the first direction DR1.

[0203] Fig. 12A and Fig. 12BIt is shown that the first conductive pattern CL1-A includes one recessed portion RP, and the recessed portion RP overlaps the first contact hole OP1c disposed between the insulating patterns SP. The insulating patterns SP may be each surrounded by the recessed portion RP. However, the inventive concept is not limited thereto, and the first conductive pattern CL1-A may further include an additional contact portion overlapping the first contact hole OP1c disposed between the insulating patterns SP. The recessed portion RP may be provided in plurality.

[0204] In this embodiment, a width w-RP of the recess portion RP in the second direction DR2 may be smaller than a width w-TP of the contact portion TP in the second direction DR2. The recess portion RP and the contact portion TP may be distinguished by the width in the second direction DR2.

[0205] A width w-TP of each of the contact portions TP in the second direction DR2 may be greater than a width w-DLE of the pad portion DL-E in the second direction DR2, and a width w-RP of the recess portion RP in the second direction DR2 may be less than a width w-DLE of the pad portion DL-E in the second direction DR2. In a plan view, a portion of the pad portion DL-E may not overlap with the first conductive pattern CL1-A.

[0206] The width w-RP of the recess portion RP in the second direction DR2 may be smaller than the width w-OP2c of the second contact hole OP2c in the second direction DR2. The recess portion RP may not include a portion covered by the second group insulating layer IG2.

[0207] The contact portion TP is a portion connected to the pad portion DL-E via the first contact hole OP1c, and may be provided to have a relatively greater width than that of the recess portion RP in order to provide a sufficient area for connection stability.

[0208] The recess portion RP is a portion surrounding the insulating pattern SP, and may be provided to have a relatively smaller width than that of the contact portion TP so that the recess portion RP may be surrounded again by the second conductive pattern CL2 , details of which will be described later.

[0209] refer to Fig. 12A , Fig. 12B and Fig.13, a portion of the first conductive pattern CL1-A (i.e., the recessed portion RP) may be disposed within the second contact hole OP2c. Since the recessed portion RP is not covered by the second group insulating layer IG2 and has a width smaller than that of the second conductive pattern CL2, the outer side surface RP-EG of the first conductive pattern CL1-A in the recessed portion RP may contact the second conductive pattern CL2 and may be covered by the second conductive pattern CL2. Accordingly, the second conductive pattern CL2 may cover the recessed portion RP in a dome shape. That is, a portion of the side surface SP-SS of the insulating pattern SP may be surrounded by the recessed portion RP, and the outer side surface RP-EG of the first conductive pattern CL1-A in the recessed portion RP may be surrounded by the second conductive pattern CL2. Fig.13 As shown in FIG. 1 , in the cross-sectional view, the second conductive pattern CL2 may contact a portion of the outer side surface RP-EG of the first conductive pattern CL1 opposite to the inner side surface defining the hole OP2r.

[0210] In the process of applying the bonding pressure, a portion of the side surface SP-SS of the insulating pattern SP may be supported by both the recessed portion RP and the second conductive pattern CL2. Therefore, in the process of applying the bonding pressure, a portion of the side portion of the insulating pattern SP may be more strongly supported, and the bonding pressure may be more easily transmitted to the protruding portion of the insulating pattern SP.

[0211] According to the present invention, the conductive pattern of the signal pad of the display panel can protrude toward the electronic component through the insulating pattern of the signal pad. The display panel and the electronic component can be combined without an anisotropic conductive film. Even when the signal pad is densely arranged in the pad portion, the short circuit defect caused by the conductive ball can be reduced. In addition, the conductive ball is omitted, and the proximity between the signal pad of the display panel and the bump electrode of the electronic component is improved, and therefore, the bonding pressure can be reduced. The bonding pressure can be reduced, thereby reducing the generation of physical damage to the display panel or the electronic component during the bonding process.

[0212] According to the inventive concept, since the side portion of a part of the insulating pattern is strengthened, the bonding pressure can be centrally transmitted to the remaining part of the insulating pattern. Therefore, since the conductive pattern of the signal pad is further in close contact with the bump electrode of the electronic component, the contact area between the conductive pattern and the bump electrode is increased, and therefore, the bonding defects and contact resistance can be reduced. In addition, the insulating pattern can be manufactured at a height sufficient to prevent problems from occurring during the process. That is, not only can the difficulties in performing the process be solved, but also a display device with improved bonding reliability can be provided.

[0213] Although the embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these embodiments, but a person of ordinary skill in the art can make various changes and modifications within the spirit and scope of the inventive concept as claimed. Therefore, the technical scope of the inventive concept is not limited to the contents described in the detailed description of this specification, but should be determined by the claims.

Claims

1. A display device, comprising a display module, wherein the display module comprises: Pixels; a signal line including a line portion and a pad portion extending from one end of the line portion and electrically connected to the pixel; as well as A signal pad connected to the signal line, the signal pad comprising: A first conductive pattern is disposed on the pad portion; a second conductive pattern, disposed on the first conductive pattern; and an insulating pattern disposed between the pad portion and the second conductive pattern in a cross-sectional view and overlapping the second conductive pattern in a plan view, A hole overlapping the insulating pattern in the plan view is defined in the first conductive pattern, and the insulating pattern passes through the first conductive pattern via the hole.

2. The display device according to claim 1, wherein: A portion of a side surface of the insulating pattern contacts the first conductive pattern.

3. The display device according to claim 1, wherein: The insulating pattern protrudes from the first conductive pattern toward a direction away from the pad portion.

4. The display device according to claim 1, wherein: The first conductive pattern has a multi-layer structure.

5. The display device according to claim 1, wherein: The second conductive pattern contacts at least a portion of an upper surface of the first conductive pattern and a portion of the insulating pattern exposed from the first conductive pattern.

6. The display device according to claim 5, wherein: In the cross-sectional view, the second conductive pattern further contacts a portion of an outer side surface of the first conductive pattern opposite to an inner side surface defining the hole.

7. The display device according to claim 1, wherein: The display module further includes a first group of insulating layers disposed between the pad portion of the signal line and the first conductive pattern, and A lower hole overlapping the hole in the plan view is defined in the first group of insulating layers, and the insulating pattern passes through the first group of insulating layers via the lower hole.

8. The display device according to claim 1, wherein: The display module further includes a first group of insulating layers disposed between the pad portion of the signal line and the first conductive pattern, A first contact hole overlapping the pad portion of the signal line and spaced apart from the insulating pattern in the plan view is defined in the first group of insulating layers, and The first conductive pattern contacts the pad portion of the signal line via the first contact hole.

9. The display device according to claim 8, wherein: The first conductive pattern includes a contact portion and a recessed portion having a width in one direction smaller than a width of the contact portion, In the plan view, the first contact hole overlaps with the contact portion, and The hole is defined in the recessed portion.

10. The display device according to claim 8, wherein: The display module further includes a second group of insulating layers disposed between the first conductive pattern and the second conductive pattern and having a second contact hole, the second contact hole being defined in the second group of insulating layers, and In the plan view, the first contact hole and the insulating pattern are disposed within the second contact hole.

11. The display device according to claim 8, wherein: The pixels include: Light emitting element; a transistor electrically connected to the light emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern; an upper electrode disposed on the gate; and a plurality of connection electrodes electrically connected to the transistor and arranged in different layers, The pad portion of the signal line includes the same material as that of the gate electrode or the upper electrode, and The first conductive pattern includes a same material as that of at least one connection electrode among the plurality of connection electrodes.

12. The display device according to claim 11, wherein: The display module further comprises: A lower insulating layer, disposed between the gate and the upper electrode; an intermediate insulating layer, disposed between the upper electrode and the plurality of connecting electrodes; and an upper insulating layer disposed between the plurality of connecting electrodes, and The first group of insulating layers includes the lower insulating layer, the middle insulating layer and the upper insulating layer.

13. The display device according to claim 11, wherein: The display module further comprises: a thin film encapsulation layer, disposed on the pixel; and A sensing electrode is disposed on the thin film encapsulation layer, The second conductive pattern includes the same material as that of the sensing electrode, The display module further includes a second group of insulating layers disposed between the first conductive pattern and the second conductive pattern, and The second conductive pattern and the sensing electrode contact the second group of insulating layers.

14. The display device according to any one of claims 1 to 13, wherein: The insulating pattern includes a polymer.

15. The display device according to any one of claims 1 to 13, further comprising: an electronic component electrically connected to the display module; as well as an adhesive layer disposed between the display module and the electronic component, The portion of the second conductive pattern overlapping the insulating pattern contacts the electronic component, the electronic component includes a substrate and a bump electrode disposed under the substrate, and the portion of the second conductive pattern overlapping the insulating pattern contacts the bump electrode.

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