Device channel degradation monitoring circuit and chip

Abstract

The invention relates to the technical field of integrated circuits and chips, and provides a device channel degradation monitoring circuit and a chip. The circuit comprises a degeneration ring oscillator, wherein the degeneration ring oscillator comprises an odd number of degeneration phase inverters which are connected in series; a first transistor in the degeneration inverter is a high-voltage power transistor, a drain electrode of the first transistor is connected with a drain electrode of a second transistor through an isolation voltage-withstanding device, a grid electrode of the second transistor is connected with a second input end, and a node between the drain electrode of the second transistor and the isolation voltage-withstanding device is connected with a second output end. The monitoring circuit overcomes the defects that an existing monitoring circuit is only suitable for monitoring a low-voltage SOC chip and cannot monitor a high-voltage circuit and a chip, can support degradation monitoring and early warning of a high-voltage device and the circuit, can be embedded into a power supply and an isolation driving chip, and overcomes the defects that at present, only aging reliability prediction is conducted on the chip when the chip leaves a factory initially, and the reliability of the chip is poor. And early warning cannot be performed on real-time dynamic aging monitoring of the high-voltage power supply and the isolation chip along with working time.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and chips, and in particular to a device channel degradation monitoring circuit and chip. Background Art

[0002] Industrial chips used in the fields of power, rail transit, and automobiles are usually mounted outdoors with terminals, and are very susceptible to strong transient electromagnetic interference generated by the operation of power devices such as IGBTs, as well as environmental factors such as high temperature and high humidity. Industrial chips need to operate stably 24 hours a day, 7 days a week, in high / low temperature, high humidity, and strong electromagnetic environments, with a lifespan of more than 15 years, which poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference.

[0003] With the rapid development of ultra-large-scale integrated circuit manufacturing technology towards deep submicron, while the channel length, junction depth and gate oxide thickness of the device are proportionally reduced and the substrate concentration is increased, the power supply voltage is not proportionally reduced, resulting in a significant increase in the lateral and longitudinal electric fields in the channel region. Hot carriers obtain sufficient energy under high electric fields and cross the interface barrier (3.2eV for electron injection and 4.5eV for hole injection) to be injected into the oxide layer, generating oxide layer trap charges or interface trap charges, which increase or fluctuate the oxide layer charge and make the device degradation more serious. It is generally believed that there are four types of charges on the SiO2 side of the Si-SiO2 interface: 1) fixed oxide layer charge Qf; 2) movable charge Qm; 3) interface trap charge Qit; 4) oxide layer trap charge Qot. When the energy of hot electrons is higher than the Si-SiO2 interface barrier, it is possible to cross the interface barrier and inject into the gate oxide layer. Some carriers eventually reach the gate electrode and form part of the gate current. In the process of hot carriers passing through the gate oxide layer to reach the gate electrode, the hot carriers will use their energy to open the Si-H, Si-OH bonds and other bonds at the interface, generate acceptor-type interface states at the Si-SiO2 interface, or be captured by traps in the gate oxide layer to form trapped charges. These generated interface states and trapped charges will cause changes in the local electric field of the device, thereby leading to the degradation of device characteristics, causing the circuit performance to gradually degrade over time, and ultimately causing the function of the device and the circuit in which it is located to fail, that is, the channel degradation effect.

[0004] Power chips and isolation driver chips usually use high-voltage MOS devices and support power supplies of 40V and above. Traditional channel degradation monitoring circuits only support low-voltage devices of 5V and are only for SOC chips. They cannot support the monitoring of high-voltage devices and circuit systems above 40V, and are not suitable for power chips and isolation driver chips containing high-voltage devices. Summary of the invention

[0005] In order to solve the above technical defects, the present invention provides a device channel degradation monitoring circuit.

[0006] In one aspect, the present invention provides a device channel degradation monitoring circuit, comprising: a degenerate ring oscillator, the degenerate ring oscillator comprising an odd number of degenerate inverters connected in series;

[0007] The degenerate inverter has a first input terminal, a second input terminal, a first output terminal and a second output terminal, the working voltage of the first input terminal and the first output terminal is a low voltage, and the working voltage of the second input terminal and the second output terminal is a high voltage;

[0008] The degenerate inverter includes: a first transistor, a second transistor and an isolation voltage-resistant device, the first transistor is a high-voltage power transistor with a voltage resistance of 12V to 750V, the drain of the first transistor is connected to the drain of the second transistor through the isolation voltage-resistant device, the source of the first transistor is grounded, the source of the second transistor is connected to the high-voltage power supply terminal, the gate of the first transistor is connected to the first input terminal, the node between the drain of the first transistor and the isolation voltage-resistant device is connected to the first output terminal, the gate of the second transistor is connected to the second input terminal, and the node between the drain of the second transistor and the isolation voltage-resistant device is connected to the second output terminal.

[0009] In an embodiment of the present invention, the isolation voltage-withstand device is a resistor device.

[0010] In an embodiment of the present invention, the isolation voltage-withstand device is a diode-connected MOS device.

[0011] In an embodiment of the present invention, the isolation voltage-withstand device is formed by connecting n NMOS transistors in a diode-connected manner.

[0012] In an embodiment of the present invention, the isolation voltage-withstand device is formed by connecting n PMOS transistors in a diode-connected manner.

[0013] In an embodiment of the present invention, the isolation voltage-withstand device is formed by connecting x PMOS transistors and y NMOS transistors in a diode-connected manner.

[0014] In an embodiment of the present invention, the degenerate inverter further includes a diode, an anode of the diode is connected to the gate of the second transistor, and a cathode of the diode is connected to the high voltage power supply terminal.

[0015] In the embodiment of the present invention, it further comprises: a non-degenerate ring oscillator;

[0016] The non-degenerate ring oscillator comprises an odd number of non-degenerate inverters connected in series;

[0017] The non-degenerate inverter has a first input terminal, a second input terminal, a first output terminal and a second output terminal, the operating voltage of the first input terminal and the first output terminal is a low voltage, and the operating voltage of the second input terminal and the second output terminal is a high voltage;

[0018] The non-degenerate inverter includes: a third transistor, a fourth transistor, a fifth transistor and an isolation voltage-resistant device, the third transistor is a high-voltage power transistor, the drain of the third transistor is connected to the source of the fifth transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor through the isolation voltage-resistant device, the source of the third transistor is grounded, the source of the fourth transistor is connected to the high-voltage power supply terminal, the gate of the third transistor is connected to the first input terminal, the node between the drain of the fifth transistor and the isolation voltage-resistant device is connected to the first output terminal, the gate of the fourth transistor is connected to the second input terminal, and the node between the drain of the fourth transistor and the isolation voltage-resistant device is connected to the second output terminal.

[0019] In an embodiment of the present invention, the isolation voltage-withstand device is a resistor device or a diode-connected MOS device.

[0020] In the embodiment of the present invention, it further comprises: a frequency attenuation detection circuit;

[0021] The frequency attenuation detection circuit is used to detect the frequency attenuation of the degenerate ring oscillator over time, and count the number of cycles of the non-degenerate ring oscillator in the corresponding cycle of the degenerate ring oscillator to monitor the channel degradation of the first transistor in the degenerate inverter.

[0022] In an embodiment of the present invention, the frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator and a latch;

[0023] The non-degenerate ring oscillator generates a non-degenerate oscillation signal and outputs it to the counter as a reference clock of the counter;

[0024] The degenerate ring oscillator generates a degenerate oscillation signal and outputs it to the frequency divider for frequency division to obtain a counting signal of the counter and a latch signal of the latch;

[0025] The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator;

[0026] The discriminator determines whether the counting result is greater than a threshold value to obtain a discrimination result;

[0027] The latch latches the discrimination result according to the latch signal and then outputs the monitoring and early warning signal.

[0028] The present invention also provides a power chip, which includes the above-mentioned device channel degradation monitoring circuit.

[0029] The present invention also provides an isolation driving chip, which includes the above-mentioned device channel degradation monitoring circuit.

[0030] The present invention designs a corresponding monitoring circuit for the channel degradation of high-voltage devices, which can support the degradation monitoring and early warning of high-voltage devices and circuits. The channel degradation monitoring circuit of the present invention can be embedded in the power supply and isolation driver chip to form a power supply and isolation driver chip with high-voltage MOS device fault monitoring and early warning functions.

[0031] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 is a schematic structural diagram of a high voltage device channel degradation monitoring circuit provided by an embodiment of the present invention;

[0034] Figure 2 is a circuit diagram of a degenerate inverter provided by a first embodiment of the present invention;

[0035] Figure 3 is a circuit diagram of a degenerate inverter provided by a second embodiment of the present invention;

[0036] Figure 4 is a circuit diagram of a degenerate inverter provided by a third embodiment of the present invention;

[0037] Figure 5 is a circuit diagram of a degenerate inverter provided by a fourth embodiment of the present invention;

[0038] Figure 6 is a circuit diagram of a non-degenerate inverter provided by an embodiment of the present invention;

[0039] Figure 7 is a schematic diagram of the structure of a ring oscillator provided by an embodiment of the present invention;

[0040] Figure 8 is a schematic diagram of a frequency attenuation detection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0042] In the description of the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0043] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be an electrical connection or mutual communication, it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] In the process of implementing the present invention, the inventors found that the traditional channel degradation monitoring circuit is only for SOC chips, and is not suitable for power chips and isolation driver chips. In addition, the traditional channel degradation monitoring solution is only for low-voltage process defect monitoring, and only supports 5V low-voltage devices, and cannot support the monitoring of high-voltage devices and circuit systems.

[0045] The present invention designs a corresponding monitoring circuit for the channel degradation of high-voltage devices to support the degradation monitoring and failure warning of 12V to 750V high-voltage devices and circuits. The channel degradation monitoring circuit of the present invention can be embedded in power supply and isolation driver chips, and is suitable for channel degradation monitoring of power supply chips and isolation driver chips.

[0046] Figure 1 1 is a schematic diagram of the structure of a high voltage device channel degradation monitoring circuit provided by an embodiment of the present invention. Figure 1As shown, the high-voltage device channel degradation monitoring circuit provided in this embodiment includes: a non-degenerate ring oscillator, a degenerate ring oscillator and a frequency attenuation detection circuit. The degenerate ring oscillator includes an odd number of degenerate inverters connected in series, and the non-degenerate ring oscillator includes an odd number of non-degenerate inverters connected in series. There are high-voltage devices in both the degenerate inverter and the non-degenerate inverter. The high-voltage devices in the degenerate inverter are subjected to voltage stress and channel degradation occurs, so that the frequency of the degenerate ring oscillator decays over time. The non-degenerate ring oscillator generates a low-voltage non-degenerate oscillation signal CLK_REF and outputs it to the frequency attenuation detection circuit, and the degenerate ring oscillator generates a low-voltage degenerate oscillation signal CLK_DEG and outputs it to the frequency attenuation detection circuit. The frequency attenuation detection circuit is used to detect the frequency attenuation of the degenerate ring oscillator over time. In the corresponding cycle of the degraded ring oscillator, the number of cycles of the non-degenerate ring oscillator is counted to realize the monitoring and early warning of the channel degradation of the high-voltage device. The frequency of the degenerate ring oscillator degenerates (attenuates) over time, while the frequency of the non-degenerate ring oscillator only degenerates very slightly over time. The frequency degradation of the non-degenerate ring oscillator is negligible relative to that of the degenerate ring oscillator.

[0047] In an embodiment of the present invention, a degenerate ring oscillator includes an odd number of degenerate inverters connected in series. The degenerate inverter has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The working voltage of the first input terminal and the first output terminal is a low voltage, and the working voltage of the second input terminal and the second output terminal is a high voltage. The degenerate inverter includes a first transistor, a second transistor and an isolation voltage-resistant device. The first transistor is a high-voltage power transistor with a voltage resistance of 12V to 750V. The drain of the first transistor is connected to the drain of the second transistor through the isolation voltage-resistant device. The source of the first transistor is grounded, and the source of the second transistor is connected to the high-voltage power supply terminal. The gate of the first transistor is connected to the first input terminal, and the node between the drain of the first transistor and the isolation voltage-resistant device is connected to the first output terminal. The gate of the second transistor is connected to the second input terminal, and the node between the drain of the second transistor and the isolation voltage-resistant device is connected to the second output terminal. Since the operating voltage of the second input terminal (connected to the gate of the second transistor) of the degenerate inverter is high voltage, and the operating voltage of the first input terminal (connected to the gate of the first transistor) is low voltage, and the first transistor is a high voltage power transistor, but the first output terminal (connected to the drain of the first transistor) is required to output low voltage, the high voltage is carried by the isolation voltage-resistant device, and the current passes through the isolation voltage-resistant device to generate a voltage drop, causing the high level to become a low level, so that the first output terminal outputs a low voltage signal.

[0048] In a first specific embodiment, if Figure 2As shown, the degenerate inverter includes: a first transistor M1, a second transistor M2 and a resistor R1, the first transistor M1 is a high-voltage power transistor, the drain of the first transistor M1 is connected to the drain of the second transistor M2 through the resistor R1, the source of the first transistor M1 is grounded GND, the source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH, the gate of the first transistor M1 is connected to the first input terminal IN_L, the node between the drain of the first transistor M1 and the resistor R1 is connected to the first output terminal OUT_L, the gate of the second transistor M2 is connected to the second input terminal IN_H, and the node between the drain of the second transistor M2 and the resistor R1 is connected to the second output terminal OUT_H. The resistor R1 is used as an isolation withstand voltage device, and the current passes through the resistor R1 to generate a voltage drop, so that the first output terminal OUT_L outputs a low-voltage signal. Specifically, the operating voltage of the first input terminal IN_L and the first output terminal OUT_L is a low voltage of 0-5V, and the operating voltage of the second input terminal IN_H and the second output terminal OUT_H is a high voltage of 12V-750V. In a typical example, the operating voltage is 40V.

[0049] In a second specific embodiment, Figure 3 As shown, the degenerate inverter includes: a first transistor M1, a second transistor M2, and a diode-connected MOS device as an isolation withstand voltage device. The diode-connected MOS device is formed by connecting n PMOS transistors (MP1-MPn) in a diode-connected manner. The gate of each of the n PMOS transistors is connected to its source as a MOS body diode. The first transistor M1 is a high-voltage power transistor, the drain of the first transistor M1 is connected to the drain of the second transistor M2 through the PMOS transistor (MP1-MPn), the source of the first transistor M1 is grounded GND, the source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH, the gate of the first transistor M1 is connected to the first input terminal IN_L, the node between the drain of the first transistor M1 and the drain of the PMOS transistor MPn is connected to the first output terminal OUT_L, the gate of the second transistor M2 is connected to the second input terminal IN_H, and the node between the drain of the second transistor M2 and the source of the PMOS transistor MP1 is connected to the second output terminal OUT_H. The current passes through the PMOS transistors (MP1-MPn) to generate a voltage drop, so that the first output terminal OUT_L outputs a low voltage signal.

[0050] In a third specific embodiment, Figure 4As shown, the degenerate inverter includes: a first transistor M1, a second transistor M2, and an isolation voltage-resistant device formed by connecting n NMOS transistors (MN1-MNn) in a diode-connected manner. The gate of each of the n NMOS transistors is connected to its drain as a MOS body diode. The first transistor M1 is a high-voltage power transistor, the drain of the first transistor M1 is connected to the drain of the second transistor M2 through the NMOS transistor (MN1-MNn), the source of the first transistor M1 is grounded GND, the source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH, the gate of the first transistor M1 is connected to the first input terminal IN_L, the node between the drain of the first transistor M1 and the source of the NMOS transistor MNn is connected to the first output terminal OUT_L, the gate of the second transistor M2 is connected to the second input terminal IN_H, and the node between the drain of the second transistor M2 and the drain of the NMOS transistor MN1 is connected to the second output terminal OUT_H. The current passes through the NMOS transistors (MN1-MNn) to generate a voltage drop, so that the first output terminal OUT_L outputs a low-voltage signal.

[0051] In the fourth specific embodiment, Figure 5 As shown, the degenerate inverter includes: a first transistor M1, a second transistor M2, and an isolation withstand voltage device formed by connecting x PMOS transistors and y NMOS transistors in a diode connection. The gate of each PMOS transistor in the x PMOS transistors is connected to its source as a MOS body diode, and the gate of each NMOS transistor in the y NMOS transistors is connected to its drain as a MOS body diode. The first transistor M1 is a high-voltage power transistor, the drain of the first transistor M1 is connected to the drain of the second transistor M2 through x PMOS transistors and y NMOS transistors, the source of the first transistor M1 is grounded GND, the source of the second transistor M2 is connected to the high-voltage power supply terminal VDDH, the gate of the first transistor M1 is connected to the first input terminal IN_L, the node between the drain of the first transistor M1 and the source of the NMOS transistor MN1 is connected to the first output terminal OUT_L, the gate of the second transistor M2 is connected to the second input terminal IN_H, and the node between the drain of the second transistor M2 and the source of the PMOS transistor MP1 is connected to the second output terminal OUT_H. The current passes through the x PMOS transistors and the y NMOS transistors to generate a voltage drop, so that the first output terminal OUT_L outputs a low voltage signal.

[0052] In the above embodiment, the degenerate inverter further includes a diode D1, the anode of the diode D1 is connected to the gate of the second transistor M2, and the cathode of the diode D1 is connected to the high voltage power supply terminal VDDH. The diode D1 has a clamping function, which can protect the gate-source voltage VGS of the second transistor M2 to be stable and prevent the second transistor M2 from burning out.

[0053] In an embodiment of the present invention, a non-degenerate ring oscillator includes an odd number of non-degenerate inverters connected in series. The non-degenerate inverter has a first input terminal, a second input terminal, a first output terminal and a second output terminal, the working voltage of the first input terminal and the first output terminal is a low voltage, and the working voltage of the second input terminal and the second output terminal is a high voltage. The non-degenerate inverter includes: a third transistor, a fourth transistor, a fifth transistor and an isolation voltage-resistant device, the third transistor is a high-voltage power transistor, the drain of the third transistor is connected to the source of the fifth transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor through the isolation voltage-resistant device, the source of the third transistor is grounded, the source of the fourth transistor is connected to the high-voltage power supply terminal, the gate of the third transistor is connected to the first input terminal, the node between the drain of the fifth transistor and the isolation voltage-resistant device is connected to the first output terminal, the gate of the fourth transistor is connected to the second input terminal, and the node between the drain of the fourth transistor and the isolation voltage-resistant device is connected to the second output terminal.

[0054] In a specific embodiment, Figure 6 As shown, the non-degenerate inverter includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a resistor R1, and also includes a diode D1, the anode of the diode D1 is connected to the gate of the fourth transistor M4, and the cathode of the diode D1 is connected to the high-voltage power supply terminal VDDH. The third transistor M3 is a high-voltage power transistor, the drain of the third transistor M3 is connected to the source of the fifth transistor M5, the drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4 through the resistor R1, the source of the third transistor M3 is grounded, the source of the fourth transistor M4 is connected to the high-voltage power supply terminal VDDH, the gate of the third transistor M3 is connected to the first input terminal IN_L, the node between the drain of the fifth transistor M5 and the resistor R1 is connected to the first output terminal OUT_L, the gate of the fourth transistor M4 is connected to the second input terminal IN_H, and the node between the drain of the fourth transistor M4 and the resistor R1 is connected to the second output terminal OUT_H. The operating voltage of the first input terminal IN_L and the first output terminal OUT_L is a low voltage of 0-5V, and the operating voltage of the second input terminal IN_H and the second output terminal OUT_H is a high voltage of 12V-750V (for example, 40V). The degenerate inverter needs to apply an overvoltage to the gate of the high-voltage device (the first transistor M1) to accelerate its channel degradation. The non-degenerate inverter does not need to apply an overvoltage to the high-voltage device (the third transistor M3), and the degradation is very slow. A fifth transistor M5 is added between the third transistor M3 and the fourth transistor M4 of the non-degenerate inverter. The fifth transistor M5 plays an isolation role, making it degenerate more slowly, and its degradation can be ignored. Therefore, the output of the non-degenerate inverter is used as a reference and compared with the degenerate inverter to monitor the degree of degradation of the degenerate inverter.

[0055] In other embodiments, the isolation withstand voltage device in the non-degenerate inverter may also be a diode-connected MOS device. The diode-connected MOS device is formed by connecting n PMOS transistors in a diode-connected manner, or by connecting n NMOS transistors in a diode-connected manner, or by connecting x PMOS transistors and y NMOS transistors in a diode-connected manner.

[0056] In the above embodiment, the first transistor M1 and the third transistor M3 can be selected from one of the high-voltage devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), BJT (Bipolar Junction Transistor), etc., and the source-drain voltage (maximum withstand voltage) thereof ranges from 12V to 750V. When a stress voltage is applied to the first high-voltage transistor M1, the channel is degraded, and the frequency of the degraded ring oscillator composed of the degraded inverter decays over time. The source-drain voltage of high-voltage devices such as LDMOS in a conventional power chip is 40V, supporting a 40V power supply.

[0057] like Figure 7 As shown, the ring oscillator is composed of an odd number of inverters. The inverters are the inverters (degenerate inverters, non-degenerate inverters) provided in the above embodiments, and each inverter includes four pins: input high voltage IN_H, output high voltage OUT_H, input low voltage IN_L, and output low voltage OUT_L.

[0058] In the embodiment of the present invention, the frequency attenuation detection circuit is used to detect the frequency attenuation of the degenerate ring oscillator over time, and count the number of cycles of the non-degenerate ring oscillator in the corresponding cycle of the degenerate ring oscillator, so as to realize the monitoring and early warning of the channel degradation of the high-voltage transistor in the degenerate inverter. Figure 8As shown, the frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator and a latch. The non-degenerate ring oscillator generates a low-voltage non-degenerate oscillation signal CLK_REF and outputs it to the counter as the reference clock of the counter. The degenerate ring oscillator generates a low-voltage degenerate oscillation signal CLK_DEG and outputs it to the frequency divider for frequency division to obtain the counting signal of the counter and the latch signal of the latch. The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator; the discriminator determines whether the counting result is greater than the threshold to obtain the discrimination result; the latch latches the discrimination result according to the latch signal (the rising edge of the CLK_DEG signal) and then outputs it. Among them, the frequency of CLK_DEG degenerates over time, and the frequency of CLK_REF does not degenerate over time. As the degraded ring oscillator degrades, the period of the oscillation signal CLK_DEG becomes longer and the frequency becomes smaller (frequency attenuation). After frequency division, the period is even longer. The divided signal is used as a counting signal to count the number of reference clocks (non-degraded oscillation signals). As the degraded ring oscillator degrades, the number of counts increases. If the counting result is greater than the threshold, it means that the frequency of the CLK_DEG signal is attenuated, the degraded ring oscillator reaches a certain degree of degradation, and the latch outputs a channel degradation warning signal.

[0059] The present invention designs a corresponding monitoring circuit for the channel degradation of high-voltage devices, which can support the degradation monitoring and early warning of high-voltage devices and circuits. The channel degradation monitoring circuit of the present invention can be embedded in the power supply and isolation driver chip to form a power supply and isolation driver chip with high-voltage MOS device fault monitoring and early warning functions. The present invention fills the gap that the current process monitoring module only monitors low-voltage processes and does not monitor high-voltage processes; it overcomes the current problem of only predicting the aging reliability of the chip at the initial factory, and being unable to warn the high-voltage power supply and isolation chip over the working time, and real-time dynamic aging monitoring.

[0060] The embodiment of the present invention also provides a power chip, which has the high-voltage device channel degradation monitoring circuit of the above embodiment embedded therein. The power chip can support degradation monitoring and failure warning of 12V to 750V high-voltage devices and circuits.

[0061] The embodiment of the present invention also provides an isolation driver chip, which has the high-voltage device channel degradation monitoring circuit of the above embodiment embedded therein. The isolation driver chip can support degradation monitoring and failure warning of 12V to 750V high-voltage devices and circuits.

[0062] The manufacturing process of the power chip or the isolation driver chip can adopt the ultra-high voltage bipolar CMOS-DMOS (BCD) process technology. By using the ultra-high voltage BCD process of non-epitaxial technology, a MOS device with a withstand voltage of up to 750V can be realized, and the device has higher reliability. The high-voltage device channel degradation monitoring and early warning circuit of the above embodiment is compatible with the ultra-high voltage BCD process.

[0063] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, the technical solutions of the embodiments of the present invention can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A device channel degradation monitoring circuit, characterized in that: include: a degenerate ring oscillator comprising an odd number of serially connected degenerate inverters; The degenerate inverter has a first input terminal, a second input terminal, a first output terminal and a second output terminal, the working voltage of the first input terminal and the first output terminal is a low voltage, and the working voltage of the second input terminal and the second output terminal is a high voltage; The degenerate inverter comprises: a first transistor, a second transistor and an isolation voltage-resistant device, wherein the first transistor is a high-voltage power transistor with a voltage resistance of 12V to 750V; The drain of the first transistor is connected to the drain of the second transistor through an isolation voltage-withstand device, the source of the first transistor is grounded, the source of the second transistor is connected to the high-voltage power supply terminal, the gate of the first transistor is connected to the first input terminal, the node between the drain of the first transistor and the isolation voltage-withstand device is connected to the first output terminal, the gate of the second transistor is connected to the second input terminal, and the node between the drain of the second transistor and the isolation voltage-withstand device is connected to the second output terminal.

2. The device channel degradation monitoring circuit according to claim 1, characterized in that: The isolation voltage-withstand device is a resistor device.

3. The device channel degradation monitoring circuit according to claim 1, characterized in that: The isolation voltage-withstand device is a diode-connected MOS device.

4. The device channel degradation monitoring circuit according to claim 3, characterized in that: The isolation voltage-withstand device is formed by connecting n NMOS transistors in a diode-connected manner.

5. The device channel degradation monitoring circuit according to claim 3, characterized in that: The isolation voltage-withstand device is formed by connecting n PMOS transistors in a diode-connected manner.

6. The device channel degradation monitoring circuit according to claim 3, characterized in that: The isolation voltage-withstand device is formed by connecting x PMOS transistors and y NMOS transistors in a diode-connected manner.

7. The device channel degradation monitoring circuit according to claim 1, characterized in that: The degenerate inverter further includes a diode, the anode of the diode is connected to the gate of the second transistor, and the cathode of the diode is connected to the high voltage power supply terminal.

8. The device channel degradation monitoring circuit according to claim 1, characterized in that: Also includes: Non-degenerate ring oscillator; The non-degenerate ring oscillator comprises an odd number of non-degenerate inverters connected in series; The non-degenerate inverter has a first input terminal, a second input terminal, a first output terminal and a second output terminal, the operating voltage of the first input terminal and the first output terminal is a low voltage, and the operating voltage of the second input terminal and the second output terminal is a high voltage; The non-degenerate inverter includes: a third transistor, a fourth transistor, a fifth transistor and an isolation voltage-resistant device, the third transistor is a high-voltage power transistor, the drain of the third transistor is connected to the source of the fifth transistor, the drain of the fifth transistor is connected to the drain of the fourth transistor through the isolation voltage-resistant device, the source of the third transistor is grounded, the source of the fourth transistor is connected to the high-voltage power supply terminal, the gate of the third transistor is connected to the first input terminal, the node between the drain of the fifth transistor and the isolation voltage-resistant device is connected to the first output terminal, the gate of the fourth transistor is connected to the second input terminal, and the node between the drain of the fourth transistor and the isolation voltage-resistant device is connected to the second output terminal.

9. The device channel degradation monitoring circuit according to claim 8, characterized in that: The isolation voltage-withstand device is a resistor device or a diode-connected MOS device.

10. The device channel degradation monitoring circuit according to claim 1, characterized in that: Also includes: Frequency attenuation detection circuit; The frequency attenuation detection circuit is used to detect the frequency attenuation of the degenerate ring oscillator over time, and count the number of cycles of the non-degenerate ring oscillator in the corresponding cycle of the degenerate ring oscillator to monitor the channel degradation of the first transistor in the degenerate inverter.

11. The device channel degradation monitoring circuit according to claim 10, characterized in that: The frequency attenuation detection circuit comprises: a frequency divider, a counter, a discriminator and a latch; The non-degenerate ring oscillator generates a non-degenerate oscillation signal and outputs it to the counter as a reference clock of the counter; The degenerate ring oscillator generates a degenerate oscillation signal and outputs it to the frequency divider for frequency division to obtain a counting signal of the counter and a latch signal of the latch; The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator; The discriminator determines whether the counting result is greater than a threshold value to obtain a discrimination result; The latch latches the discrimination result according to the latch signal and then outputs the monitoring and early warning signal.

12. A power chip, characterized in that: The power chip comprises the device channel degradation monitoring circuit according to any one of claims 1 to 11.

13. An isolation driver chip, characterized in that: The isolation driving chip comprises the device channel degradation monitoring circuit according to any one of claims 1 to 11.

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