Device substrate degradation monitoring circuit and chip

Abstract

The invention relates to the technical field of integrated circuits and chips, and provides a device substrate degradation monitoring circuit and a chip. The substrate degradation monitoring circuit comprises a plurality of monitoring branches connected in parallel, each monitoring branch comprises a high-voltage MOS device, a comparator and a selector, and the selectors comprise a first selector, a second selector and a third selector; a drain electrode of the high-voltage MOS device is connected with stress voltage through the first selector and is connected to a first input end of the comparator; the grid electrode of the high-voltage MOS device is connected with a test voltage through a second selector, and the test voltage applies a negative bias voltage to the grid drain end of the high-voltage MOS device; the source electrode of the high-voltage MOS device is connected with a reverse test voltage through a third selector; the second input end of the comparator of each monitoring branch inputs a reference voltage, and the second input ends of the comparators of different monitoring branches input different reference voltages. According to the invention, degradation monitoring and early warning of high-voltage devices and circuits can be supported.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and chips, and in particular to a device substrate degradation monitoring circuit and chip. Background Art

[0002] Industrial chips used in the fields of power, rail transit, and automobiles are usually mounted outdoors with terminals, and are very susceptible to strong transient electromagnetic interference generated by the operation of power devices such as IGBTs, as well as environmental factors such as high temperature and high humidity. Industrial chips need to operate stably 24 hours a day, 7 days a week, in high / low temperature, high humidity, and strong electromagnetic environments, with a lifespan of more than 15 years, which poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference.

[0003] The devices in industrial chips will produce substrate degradation under the influence of environmental factors. The traditional monitoring circuit for device substrate degradation is mainly used in low-voltage 5V SOC chips. For example, the external circuit signal representing the circuit under test on the low-voltage 5V SoC chip is received by the measurement ring oscillator, which is in the same aging environment as the circuit under test on the low-voltage 5V SoC chip. The level number used for substrate degradation detection of the circuit under test is obtained to determine whether the circuit under test has substrate degradation.

[0004] Power chips usually use high-voltage MOS devices and support power supplies of 40V and above. Traditional degradation monitoring solutions only support low-voltage devices of 5V and are only for SOC chips. They cannot support the monitoring of high-voltage devices and circuit systems above 40V, and are not suitable for power chips and isolation driver chips containing high-voltage devices.

[0005] Although existing post-compensation methods such as off-chip and post-wafer current monitoring degradation through current analyzers can detect process initial failures of high-voltage MOS devices, the monitored threshold voltage cannot be adjusted and the monitoring time cannot be controlled, making it difficult to achieve dynamic monitoring of reliability failures of power supplies and isolation drive circuits over time. Summary of the invention

[0006] In order to solve the above technical defects, the present invention provides a device substrate degradation monitoring circuit.

[0007] The device substrate degradation monitoring circuit provided by the present invention comprises: a plurality of monitoring branches connected in parallel, each monitoring branch comprises: a high-voltage MOS device, a comparator and a selector, the selector comprises a first selector, a second selector and a third selector;

[0008] The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and is connected to the first input terminal of the comparator;

[0009] The gate of the high-voltage MOS device is connected to a test voltage through a second selector, and the test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device;

[0010] The source of the high-voltage MOS device is connected to a reverse test voltage through a third selector;

[0011] A reference voltage is input to the second input terminal of the comparator of each monitoring branch, and different reference voltages are input to the second input terminals of the comparators of different monitoring branches.

[0012] In the embodiment of the present invention, the gate of the high-voltage MOS device is connected to the source of the high-voltage MOS device through the second selector and the third selector.

[0013] In the embodiment of the present invention, the device substrate degradation monitoring circuit selects the working state of each monitoring branch as the stress application state or the degradation monitoring state through the first selector, the second selector and the third selector.

[0014] In the embodiment of the present invention, when the first selector selects that the drain of the high-voltage MOS device is connected to the stress voltage, the second selector selects that the gate of the high-voltage MOS device is connected to the test voltage, and the third selector selects that the source of the high-voltage MOS device is connected to the reverse test voltage, the working state of the monitoring branch is the stress application state;

[0015] When the first selector selects the drain of the high-voltage MOS device to be connected to the first input terminal of the comparator, and the second and third selectors select the gate and source of the high-voltage MOS device to be connected, the working state of the monitoring branch is the degradation monitoring state.

[0016] In the embodiment of the present invention, the drain connection stress voltage of the high-voltage MOS device in each monitoring branch is the same; and the reference voltage input to the second input terminal of the comparator of each monitoring branch increases in sequence.

[0017] In the embodiment of the present invention, the absolute maximum voltage (source-drain voltage) between the drain and the source of the high-voltage MOS device in each monitoring branch is the same.

[0018] In the embodiment of the present invention, the stress voltages connected to the drains of the high-voltage MOS devices in the monitoring branches are all different; and the reference voltages input to the second input terminals of the comparators of the monitoring branches are increased in sequence.

[0019] In the embodiment of the present invention, the high-voltage MOS device in each monitoring branch is one of DEMOS, LDMOS, VDMOS, and BJT, and the withstand voltage range of the high-voltage MOS device is 12V to 750V.

[0020] The present invention also provides a power chip, in which the above-mentioned device substrate degradation monitoring circuit is embedded.

[0021] The present invention also provides an isolation driving chip, wherein the isolation driving chip is embedded with the above-mentioned device substrate degradation monitoring circuit.

[0022] The present invention designs a corresponding monitoring circuit for substrate degradation of high-voltage devices, and can support substrate degradation monitoring and early warning of high-voltage devices and circuits; the substrate degradation monitoring circuit of the present invention can perform real-time dynamic internal monitoring of PA-level current, and the monitored degradation threshold voltage is adjustable, the stress voltage is adjustable, and the degradation time is controllable, so that dynamic monitoring of reliability failures of power supply and isolation drive circuits over time can be realized, and the circuit can be embedded in the power supply and isolation drive chip to form a power supply and isolation drive chip with high-voltage MOS device failure monitoring function.

[0023] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0025] Figure 1 is a schematic diagram of a device substrate degradation monitoring circuit provided by an embodiment of the present invention;

[0026] Figure 2 is a block diagram of a power chip provided by an embodiment of the present invention;

[0027] Figure 3 4 is a block diagram of an isolation driver chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0029] In the description of the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0030] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be an electrical connection or mutual communication, it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] In the process of realizing the present invention, the inventors found that the traditional fault monitoring circuit is only for 5V SOC chips, which is a low-voltage process defect monitoring module, while the power chip usually uses high-voltage MOS devices and supports 40V and above power supplies. The traditional fault monitoring circuit is not suitable for power chips and isolation driver chips containing high-voltage MOS devices. Although the existing post-compensation methods such as off-chip and post-chip current monitoring degradation through current analyzers can detect the process initial faults of high-voltage MOS devices, the threshold voltage of the monitoring cannot be adjusted and the monitoring time cannot be controlled, making it difficult to achieve dynamic monitoring of reliability faults of power supply and isolation driver circuits over time.

[0032] The present invention designs a corresponding monitoring circuit for substrate degradation of high-voltage devices to support degradation monitoring of 12V to 750V high-voltage devices and circuits. The substrate degradation monitoring circuit of the present invention can be embedded in power and isolation driver chips, and is suitable for channel degradation monitoring of power chips and isolation driver chips.

[0033] The failure mechanism of substrate degradation is: under the action of high temperature stress and negative gate voltage stress, the interface defects of Si-SiO2 interface contain Si-H bond defects. Under the action of hot holes and reactant X, Si-H bonds break, and the split H ions or substances formed by combining with X substances diffuse into the oxide layer. On the one hand, they form interface states at the interface, and on the other hand, they may be captured in the oxide layer, thus forming positive charges in the oxide layer. All of these affect the drift of the threshold voltage, reduce the leakage current of the device, and change the threshold voltage Vth with time stress. Under the action of negative gate voltage bias, the chip of PMOS PEDMOS devices works under high electric field and high temperature conditions, the saturated drain current Idsat and transconductance Gm continue to decrease, and the absolute value of the threshold voltage continues to increase, thus affecting the performance of the circuit.

[0034] The failure mode of NBTI can be described by the following formula:

[0035]

[0036] Where MTTF is the median failure life, A is a constant, E is the electric field density (cm / MV), k is the Boltzmann constant, and E ais the activation energy (eV), β is the electric field density coefficient (cm / MV), and T is the absolute temperature (K).

[0037] The substrate degradation effect is a temperature-related reliability failure mechanism. The typical conditions for its occurrence are in the range of 100℃ to 250℃ and the gate oxide electric field strength E ox <6MV / cm. The impact on PMOS devices under NBTI stress is directly manifested as threshold voltage drift. The threshold of the PMOS tube will drift greatly under voltage and temperature stress, and the absolute value of the threshold voltage will continue to increase, resulting in transconductance degradation of the PMOS, reduced leakage current, and reduced driving capability. Therefore, directly measuring the drift of the threshold voltage can intuitively reflect the impact of NBTI on PMOS devices. Applying a large voltage stress to the PMOS tube in the monitoring circuit will make it reach the critical failure point earlier than the circuit under test, thereby sending an alarm signal to achieve the effect of early warning.

[0038] In high-voltage power supplies and isolation driver chips, high breakdown voltage requires MOS tubes to have thick lightly doped regions and long drift regions. In order to prevent various types of breakdown, DEMOS (Drain-Extended MOS) can be selected. A lightly doped extension layer is added to the drain end of DEMOS. The extension layer increases the drain end withstand voltage by maintaining charge balance, using appropriate vertical profiles, and increasing the length of the low-doped region. The lightly doped region forms a high resistance that can withstand higher voltages. Most of the high drain end voltage will fall on this lightly doped region, so the lightly doped extension layer can increase the drain end withstand voltage. The extension layer greatly reduces the possibility of punch-through between the drain and the source; at the same time, the lightly doped extension layer makes the gate end unaffected by the drain end voltage and increases the gate end length, so the possibility of gate end breakdown is reduced. DEMOS is often used in power supplies and isolation driver chips, and its substrate degradation effect directly affects the reliability of the overall chip.

[0039] By monitoring the threshold voltage of the pedmos tube in the failed circuit, the threshold voltage of the degraded pedmos tube drifts and is higher than the threshold voltage of the normal non-degraded pedmos tube. The threshold voltage with different drift degrees also reflects the degree of degradation of the pedmos tube. Based on this, the degree of degradation of the pedmos tube can be determined by comparing the threshold voltage with different Vref reference voltages. In the traditional degradation monitoring technology solution, the degradation monitoring system only supports 5V devices and can only monitor SoC low-voltage circuits, and cannot support the monitoring of high-voltage pedmos devices and circuit systems.

[0040] In order to solve the problem that ordinary monitoring circuits can only monitor low-voltage 5V devices, the present invention proposes a device substrate degradation monitoring circuit, which can support the monitoring of 12V to 750V high-voltage resistant devices and circuits; and is combined with a power supply and an isolation driver chip, embedded in the power supply and isolation driver chip, to form a power supply and isolation driver chip with device high-voltage fault monitoring function.

[0041] The embodiment of the present invention provides a device substrate degradation monitoring circuit, including multiple monitoring branches connected in parallel, each monitoring branch includes a high-voltage MOS device, a comparator and a selector, and the selector includes a first selector, a second selector and a third selector; the drain of the high-voltage MOS device is connected to a stress voltage through the first selector, and is connected to the first input of the comparator; the gate of the high-voltage MOS device is connected to a test voltage through the second selector, and the test voltage is used to apply a negative bias to the gate-drain terminal of the high-voltage MOS device; the source of the high-voltage MOS device is connected to a reverse test voltage through the third selector; the second input terminal of the comparator of each monitoring branch inputs a reference voltage, and the second input terminals of the comparators of different monitoring branches input different reference voltages. The present invention proposes a chip-based, real-time dynamic internal monitoring module for pA-level current dynamics, the monitored degradation threshold voltage is adjustable, the stress voltage is adjustable, and the degradation time is controllable, which can realize dynamic monitoring of reliability failures of power supply and isolation drive circuits over time. In a specific embodiment, the high-voltage MOS device in each monitoring branch can be one of the high-voltage MOS devices such as DEMOS (Drain-Extended MOS), LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), BJT (Bipolar Junction Transistor), etc., and its source-drain voltage (maximum withstand voltage) ranges from 12V to 750V.

[0042] Figure 1 is a schematic diagram of a device substrate degradation monitoring circuit provided by an embodiment of the present invention. In this embodiment, the high-voltage MOS tubes in each monitoring branch are DEMOS devices, and the source-drain voltage vds of the DEMOS devices in each monitoring branch are the same. Figure 1As shown, taking a 40V pedmos device as an example, the device substrate degradation monitoring circuit includes a plurality of monitoring branches connected in parallel, each monitoring branch includes: a pedmos 40V device, a comparator AMP and a selector sel; each monitoring branch has three selectors sel, and for the convenience of description, the selectors from top to bottom are defined as the first selector sel, the second selector sel, and the third selector sel. In each monitoring branch, the drain of the pedmos 40V device is connected to the stress voltage Stress through the first selector sel, and is connected to the first input terminal (reverse input terminal) of the comparator AMP; the gate of the pedmos 40V device is connected to the test voltage press through the second selector sel, and the test voltage press is a negative bias applied to the gate-drain terminal of the pedmos 40V device; the source of the pedmos 40V device is connected to the reversed test voltage press through the third selector sel. The gate of the pedmos 40V device is connected to the source of the pedmos 40V device through the second selector sel and the third selector sel. A different reference voltage Vref is input to the second input terminal (non-inverting input terminal) of the comparator AMP of each monitoring branch.

[0043] The power supply voltage range in the monitoring circuit is 0-5V, which is a monitoring circuit composed of ordinary low-voltage devices; in the monitored circuit, the power supply voltage is in the working range of 0-40V, which is a circuit structure composed of high-voltage pedmos 40v devices. In the fault monitoring circuit composed of 5V low-voltage devices, multiple pedmos 40v tubes for monitoring substrate degradation are included. These pedmos 40v tubes are applied with the same or different stress voltages Stress during the degradation stage. At the same time, in the stage of detecting the degree of degradation, each pedmos 40v tube output is connected to a comparator, and the reference voltage Vref of each comparator is different. Figure 1 In the figure, press is the negative bias stress applied to the gate and drain of the tested pedmos 40v device. Generally, a negative bias of 0 to 5V is applied to the gate and drain. The source-drain voltage vds of the pedmos 40v device is 40v, which is a high-voltage MOS tube that can meet the 40V power supply. The negative bias stress (i.e., the test voltage) press applied to the gate and drain of the pedmos 40v device is 0 to 5V, and the threshold voltage vth of the pedmos 40v device is 0.92V. By applying a constant voltage stress to the source of the pedmos, when press = 0V, vgs>vth, the pedmos is in the saturation region, thereby degrading it. When the stress voltage Stress is 5V, 5.5V, and 6V, it can produce a difference with the 5V voltage of the drain, thereby simulating the degradation of the high-voltage device and analyzing the impact of substrate degradation on the life of the pedmos 40v device.

[0044] Figure 1 The substrate degradation monitoring circuit shown is essentially a circuit that monitors the drift of the threshold voltage. The circuit formed by connecting ABCDEF in each monitoring branch is a circuit that applies voltage stress and monitors the degree of degradation, and the output is sent to one input terminal of the comparator AMP, and the reference voltage Vref is input to the other input terminal of the comparator AMP. The power supply terminal provides a stress voltage Stress, and the stress voltage Stress of each monitoring branch can be fixed and the same, or it can be different. When the threshold voltage of the pedmos 40v device drifts under the effect of substrate degradation, the threshold voltage output at the B terminal of the monitoring circuit becomes larger. When the degraded threshold voltage is greater than a certain set value, the comparator AMP outputs a high level to issue a warning to the subsequent circuit.

[0045] In the embodiment of the present invention, the working state of the monitoring branch can be selected / switched to be a stress application state or a degradation monitoring state through three selectors Sel. When the first selector Sel selects the drain of the pedmos device to be connected to the stress voltage Stress, the second selector Sel selects the gate of the pedmos device to be connected to the test voltage Press, and the third selector Sel selects the source of the pedmos device to be connected to the reverse test voltage, the working state of the monitoring branch is the stress application state; when the first selector Sel selects the drain of the pedmos device to be connected to the first input terminal of the comparator, and the second selector Sel and the third selector Sel select the gate and source of the pedmos device to be connected, the working state of the monitoring branch is the degradation monitoring state.

[0046] In a specific embodiment, the stress voltage Stress of the drain connection of the pedmos device in each monitoring branch is the same, and the source-drain voltage vds of the pedmos device in each monitoring branch is the same, which is 40V. The reference voltage Vref input to the comparator AMP of each monitoring branch increases in sequence, for example: 0.95V, 0.96V, 0.97V, etc. The circuit state can be switched by the selector Sel: when the circuit is in the stress state, the selector Sel selects the ACE path to apply overvoltage stress to the pedmos 40v device; when the circuit is in the monitoring circuit state, the Sel selector selects the BDF path. For example: when the substrate of a pedmos 40v device is degraded, its maximum threshold voltage vth increases to above 0.95V and below 0.96V. During the monitoring stage, the threshold voltage vth is compared with the reference voltage Vref 0.95V of the comparator. The degraded threshold voltage is higher than the reference voltage, and the output end of the comparator outputs a low level, issuing a warning for the subsequent circuit. It can be seen that the substrate of the pedmos 40v device in the monitoring branch is degraded, and the reference voltage Vref of the comparator in other monitoring branches is higher than 0.96V. The comparator does not issue a warning and can continue to work. As the circuit working time increases, the substrate of the pedmos 40v devices in other monitoring branches continues to degrade, and the maximum threshold voltage vth of the pedmos 40v devices increases to above 0.96V and below 0.97V. In the monitoring stage, the threshold voltage vth is compared with the reference voltage Vref of the comparator. The degraded threshold voltage is higher than the reference voltage Vref of the comparator by 0.95V and 0.96V. The output ends of the two comparators both output low levels, which issue warnings for subsequent circuits. It can be seen that the substrates of the pedmos 40v devices in the two monitoring branches are degraded. The remaining comparators with Vref higher than 0.97V do not issue warnings and can continue to work, and so on. The warnings issued by comparators with different reference voltages Vref show that the larger the threshold voltage after degradation, the more comparators that issue warnings, indicating a higher degree of degradation, thereby judging the degree of degradation of the threshold voltage of substrate degradation at this time, and realizing visualization of the threshold voltage vth of the monitored circuit. Since the reference voltage Vref of the comparator is an external input, a circuit structure with an adjustable monitoring degradation threshold is formed at the same time, which plays a role in fault monitoring and early warning of the high-voltage pedmos device.

[0047] In another specific embodiment, the stress voltage Stress of the drain connection of the pedmos 40V device in each monitoring branch is different. For example, the stress voltage Stress in the monitoring branch is 5V, 5.5V, 6V, etc. The difference in stress voltage Stress will lead to different degradation times of the pedmos 40V device. Increasing the stress voltage Stress will advance the degradation time, and reducing the stress voltage Stress will delay the degradation time. Assuming that the maximum threshold voltage vth of the pedmos 40v device degrades to above 0.95V, the degradation degree is 20%, and the threshold voltage vth degrades to above 0.96V, the degradation degree is 30%, and so on. Then, by increasing the stress voltage Stress, the pedmos 40V device can be degraded in advance, the degradation time can be controlled, and the waiting time for monitoring the degradation degree can be saved, so that the degree of degradation of the current pedmos 40V device can be known.

[0048] It should be noted that the reference voltage Vref of the comparator in the present invention includes but is not limited to 0.95V, 0.96V, and 0.97V, which can be set according to the requirements. The stress voltage Stress in each monitoring branch includes but is not limited to 5V, 5.5V, and 6V, which can be set according to the requirements.

[0049] The embodiment of the present invention further provides a power chip, which has the device substrate degradation monitoring circuit of the above embodiment embedded therein. Figure 2 As shown, the device substrate degradation monitoring circuit of the above embodiment is embedded in a power chip, and a power chip capable of monitoring substrate degradation faults of 12V-750V high-voltage devices is integrated.

[0050] The embodiment of the present invention further provides an isolation driver chip, in which the device substrate degradation monitoring circuit of the above embodiment is embedded. Figure 3 As shown, the device substrate degradation monitoring circuit of the above embodiment is embedded in the isolation driver chip, integrating the isolation driver chip with the function of monitoring the substrate degradation fault of the 12V-750V high voltage device.

[0051] The substrate degradation monitoring circuit of the present invention can support fault warning of high-voltage circuits, and also support monitoring of high-voltage PEDMOS devices and circuits; and in combination with power supply and isolation driver chips, the substrate degradation monitoring circuit is embedded in the power supply and isolation driver chips to form a power supply and isolation driver chip with high-voltage device substrate degradation monitoring function. The present invention can adjust the monitored degradation threshold voltage, can adjust different voltage stresses, make the degradation time controllable, and thus accurately and quickly know the degradation degree of the device.

[0052] The manufacturing process of the power chip or the isolation driver chip can adopt the ultra-high voltage bipolar CMOS-DMOS (BCD) process technology. By using the ultra-high voltage BCD process of non-epitaxial technology, a MOS device with a withstand voltage of up to 700V can be realized, and the device has higher reliability. The high-voltage device substrate degradation monitoring and early warning circuit of the above embodiment is compatible with the ultra-high voltage BCD process.

[0053] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A device substrate degradation monitoring circuit, characterized in that: It includes a plurality of monitoring branches connected in parallel, each monitoring branch includes: a high-voltage MOS device, a comparator and a selector, and the selector includes a first selector, a second selector and a third selector; The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and is connected to the first input terminal of the comparator; The gate of the high-voltage MOS device is connected to a test voltage through a second selector, and the test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device; The source of the high-voltage MOS device is connected to a reverse test voltage through a third selector; A reference voltage is input to the second input terminal of the comparator of each monitoring branch, and different reference voltages are input to the second input terminals of the comparators of different monitoring branches.

2. The device substrate degradation monitoring circuit according to claim 1, characterized in that: The gate of the high-voltage MOS device is connected to the source of the high-voltage MOS device through the second selector and the third selector.

3. The device substrate degradation monitoring circuit according to claim 2, characterized in that: The device substrate degradation monitoring circuit selects the working state of each monitoring branch as a stress application state or a degradation monitoring state through a first selector, a second selector and a third selector.

4. The device substrate degradation monitoring circuit according to claim 3, characterized in that: When the first selector selects that the drain of the high-voltage MOS device is connected to the stress voltage, the second selector selects that the gate of the high-voltage MOS device is connected to the test voltage, and the third selector selects that the source of the high-voltage MOS device is connected to the reverse test voltage, the working state of the monitoring branch is the stress application state; When the first selector selects the drain of the high-voltage MOS device to be connected to the first input terminal of the comparator, and the second and third selectors select the gate and source of the high-voltage MOS device to be connected, the working state of the monitoring branch is the degradation monitoring state.

5. The device substrate degradation monitoring circuit according to claim 1, characterized in that: The stress voltage of the drain connection of the high-voltage MOS device in each monitoring branch is the same; The reference voltage input to the second input terminal of the comparator of each monitoring branch increases in sequence.

6. The device substrate degradation monitoring circuit according to claim 5, characterized in that: The source-drain voltages of the high-voltage MOS devices in each monitoring branch are the same.

7. The device substrate degradation monitoring circuit according to claim 1, characterized in that: The stress voltage of the drain connection of the high-voltage MOS device in each monitoring branch is different; The reference voltage input to the second input terminal of the comparator of each monitoring branch increases in sequence.

8. The device substrate degradation monitoring circuit according to claim 1, characterized in that: The high-voltage MOS device in each monitoring branch is one of DEMOS, LDMOS, VDMOS and BJT, and the withstand voltage range of the high-voltage MOS device is 12V to 750V.

9. A power chip, characterized in that: The power chip comprises the device substrate degradation monitoring circuit according to any one of claims 1 to 8.

10. An isolation driver chip, characterized in that: The isolation driving chip comprises the device substrate degradation monitoring circuit according to any one of claims 1 to 8.

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