Low power consumption design method and system for CPU card security chip

Abstract

The present application relates to the technical field of CPU card security chips, and discloses a low-power design method and system for a CPU card security chip. The method comprises: sampling current waveforms of a key storage area, an encryption operation unit, and an identity authentication processor of the CPU card security chip, recording current data of the CPU card security chip when executing data encryption, identity authentication, and security calculation, and obtaining a characteristic parameter set of a security function module; establishing an encryption operation power consumption model and an identity authentication power consumption model, and obtaining a power consumption characteristic matrix under different key lengths by piecewise linear fitting; classifying security application tasks to obtain a multi-level security task classification table; executing a differential power consumption attack protection strategy according to the multi-level security task classification table, and calculating the operating voltage and frequency configuration sequence of each security function module. The present application achieves an optimal balance between power consumption and performance under different key lengths, and improves the comprehensive performance of the CPU card security chip.

Description

Technical Field

[0001] The present application relates to the technical field of CPU card security chips, and in particular to a low-power design method and system for a CPU card security chip. Background Art

[0002] With the widespread application of smart cards in financial payment, identity authentication, access control and other fields, the low-power design of CPU card security chips has received increasing attention. When traditional CPU card security chips perform encryption operations, data storage and identity authentication, the power consumption characteristics of each security function module are highly nonlinear, which not only increases the power consumption of the chip, but also provides a possible breakthrough for differential power analysis attacks.

[0003] At present, the power management strategy of CPU card security chips mainly adopts fixed voltage and frequency configuration schemes, which cannot be dynamically adjusted according to the resource demand characteristics of tasks with different security levels. At the same time, traditional power management methods often focus on reducing overall power consumption, ignoring the side channel information leakage problem that may be caused by power consumption fluctuations, which makes the chip face security risks when performing high-security level operations. Summary of the invention

[0004] The present application provides a low-power design method and system for a CPU card security chip. The present application achieves an optimal balance between power consumption and performance under different key lengths, thereby improving the overall performance of the CPU card security chip.

[0005] The first aspect of the present application provides a low power consumption design method for a CPU card security chip, the low power consumption design method for a CPU card security chip comprising:

[0006] The key storage area, encryption operation unit and identity authentication processor of the CPU card security chip are sampled for current waveforms, and the current data of the CPU card security chip when performing data encryption, identity authentication and security calculation are recorded to obtain a characteristic parameter set of the security function module;

[0007] According to the characteristic parameter set of the security function module, an encryption operation power consumption model and an identity authentication power consumption model are established, and a power consumption characteristic matrix under different key lengths is obtained by piecewise linear fitting;

[0008] Classifying the safety application tasks based on the power consumption characteristic matrix to obtain a multi-level safety task classification table;

[0009] A differential power consumption attack protection strategy is executed according to the multi-level security task classification table, and an operating voltage and frequency configuration sequence of each security function module is calculated.

[0010] The second aspect of the present application provides a low power consumption design system for a CPU card security chip, the low power consumption design system for a CPU card security chip comprising:

[0011] The sampling module is used to sample the current waveform of the key storage area, encryption operation unit and identity authentication processor of the CPU card security chip, record the current data of the CPU card security chip when performing data encryption, identity authentication and security calculation, and obtain the characteristic parameter set of the security function module;

[0012] Establishing a module, used to establish an encryption operation power consumption model and an identity authentication power consumption model according to the characteristic parameter set of the security function module, and obtain a power consumption characteristic matrix under different key lengths through piecewise linear fitting;

[0013] A classification module, used to classify the safety application tasks based on the power consumption characteristic matrix to obtain a multi-level safety task classification table;

[0014] A calculation module is used to execute the differential power consumption attack protection strategy according to the multi-level security task classification table, and calculate the operating voltage and frequency configuration sequence of each security function module.

[0015] Compared with the prior art, the present application has the following beneficial effects: by establishing a refined power consumption characteristic model, combined with 16-bit high-precision sampling and multi-dimensional data analysis, the dynamic power consumption characteristics of each security function module of the CPU card security chip are accurately characterized, the security sensitivity analysis method is used to classify the tasks in multiple levels, and the optimal configuration sequence is generated through the dynamic power consumption balancing algorithm, which reduces the overall power consumption while ensuring the performance requirements of tasks of different security levels. The randomized clock modulation and voltage jitter technology are innovatively introduced, and the dynamic obfuscation of the power consumption waveform is realized by constructing a time-space interleaving matrix, which effectively enhances the chip's ability to resist differential power consumption analysis attacks. A systematic performance evaluation method is designed, and a comprehensive evaluation of the chip's security performance, computing efficiency and power consumption characteristics is achieved through a comprehensive analysis of multi-dimensional indicators. The working state switching strategy is optimized based on the Markov chain model and fuzzy control algorithm, which reduces the power consumption overhead during the state transition process and improves the energy utilization efficiency of the system. By combining piecewise linear fitting and dynamic balancing control, the optimal balance between power consumption and performance is achieved under different key lengths, significantly improving the comprehensive performance of the CPU card security chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0018] Figure 1 It is a flow chart of a low power consumption design method for a CPU card security chip provided by an embodiment of the present invention;

[0019] Figure 2 The invention is a schematic block diagram of the structure of a low-power design system for a CPU card security chip provided by an embodiment of the invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0022] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0023] It should be further understood that the term "and / or" used in the specification and appended claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations. Figure 1 , an embodiment of the low power consumption design method of the CPU card security chip in the embodiment of the present application includes:

[0024] Step 100, sampling the current waveform of the key storage area, encryption operation unit and identity authentication processor of the CPU card security chip, recording the current data of the CPU card security chip when performing data encryption, identity authentication and security calculation, and obtaining a characteristic parameter set of the security function module;

[0025] It is understandable that the execution subject of the present application can be a low-power design system of a CPU card security chip, or a terminal or a server, which is not limited here. The present application embodiment is described by taking a server as the execution subject as an example.

[0026] Specifically, a high-precision current sampling circuit is embedded in the key functional module of the CPU card security chip to record the current changes when performing data encryption, identity authentication and security calculations. A high-speed sampling ADC (analog-to-digital converter) is used to obtain the real-time current waveform, and the sampling frequency is ensured to be high enough to capture the instantaneous power consumption changes when the chip performs different security tasks, and obtain the original current sampling data. Repeated sampling tests are performed on the original current sampling data to improve the stability and credibility of the sampling data, and the obtained multiple sets of current waveform data are compared and analyzed to extract the stable power consumption characteristics of the chip under specific security operations. Multiple sets of current waveform data are collected in segments to correspond to different working modes. According to the working timing of the chip, the power consumption data is split into different segments, and the voltage and frequency combination data under different working states are obtained by combining the voltage and frequency settings of the chip. The voltage and frequency combination data are classified and stored. In the classification process, the power consumption data is sorted into three different data sets based on the three main security functions of the chip, namely encryption operation, identity authentication and other security calculations. During the encryption operation, the power consumption of the chip will show obvious periodic peak changes. Therefore, a peak power consumption data set during encryption operation is established to capture the maximum power consumption of the encryption unit when processing keys of different lengths. During the authentication process, since the computing tasks are relatively balanced and the power consumption fluctuations are small, the average power consumption data of the process is extracted to form an average power consumption data set during authentication. For the power consumption characteristics when performing security calculations (such as key management, storage access, etc.), the working time data set during security calculations is established by measuring the time required for the calculations and combining the corresponding power consumption data. The above power consumption data sets are analyzed to establish the static power consumption and dynamic power consumption relationship matrix of each security function module. Different power consumption data are grouped according to the key length, and the relationship between static power consumption and dynamic power consumption is analyzed using mathematical fitting methods (such as polynomial fitting or piecewise linear fitting). Static power consumption mainly refers to the power consumption of the chip when it is idle or low-load computing, while dynamic power consumption represents the power consumption change of the chip when performing encryption operations or authentication. Through fitting analysis, the mathematical relationship matrix of the power consumption of each functional module with the task complexity (such as key length, computing load) is obtained. The principal component analysis of the relationship matrix between static power consumption and dynamic power consumption is performed to reduce the data dimension while retaining the main information of the data, and the main power consumption characteristic parameters of the security function module are extracted, such as the main power consumption change trend under different key lengths, the impact of task load on power consumption, and the power consumption distribution law under different working states. The characteristic parameter set of the security function module is obtained.

[0027] Step 200: Establish an encryption operation power consumption model and an identity authentication power consumption model according to a security function module characteristic parameter set, and obtain a power consumption characteristic matrix under different key lengths by piecewise linear fitting;

[0028] Specifically, the characteristic parameter set of the security function module is segmented to obtain multiple groups of key length power consumption data. The power consumption data is classified according to different key lengths, and similar power consumption modes are clustered using statistical methods to build a more accurate model. In the data segmentation process, the power consumption data is denoised and normalized to eliminate the interference of abnormal data and ensure the comparability of data between different key lengths. The encryption operation power consumption model is constructed based on multiple groups of key length power consumption data. Since the power consumption characteristics of encryption operations are usually not linear, but are affected by multiple factors such as calculation complexity, register state switching, and storage access mode, the encryption operation power consumption model is segmented, the entire key length interval is divided into several sub-intervals, and linear fitting is performed in each sub-interval to ensure that the fitting result is more in line with the actual power consumption change trend. In the process of piecewise linear fitting, the least squares method is used to calculate the linear model coefficient group in each sub-interval, so that the encryption operation power consumption can be reasonably approximated within different key lengths. Through segmentation processing and local fitting, the piecewise linear model coefficient group is obtained. The identity authentication power consumption model is constructed based on the piecewise linear model coefficient group. By combining the power consumption model of encryption operation and the changing law of power consumption in the authentication process, an authentication power consumption model based on piecewise linear fitting is constructed. The parameter transfer method is adopted, that is, using some fitting parameters of the encryption operation power consumption model, combined with the statistical analysis results of power consumption data in the authentication process, the calculation formula of authentication power consumption is derived, and the fitting accuracy of the model is optimized. The encryption operation power consumption model and the authentication power consumption model are transformed into a matrix under different key lengths to obtain a power consumption feature map. A joint matrix consisting of encryption operation power consumption data and authentication power consumption data is constructed, and the matrix is ​​projected into a new feature space using the matrix transformation method to extract the main components of the power consumption data. The power consumption feature map is subjected to eigendecomposition operation and orthogonal transformation to obtain the power consumption feature matrix under different key lengths. Eigendecomposition is to decompose a complex power consumption feature map into a set of independent power consumption modes, thereby simplifying the analysis process and improving the accuracy of power consumption prediction. In the process of eigendecomposition, the power consumption feature map is decomposed into several independent components using a matrix decomposition method, such as eigenvalue decomposition or principal component analysis, and the component with the greatest impact on power consumption change is selected as the main feature. In order to ensure the stability of the power consumption feature matrix under different key length conditions, the decomposed features are orthogonally transformed to eliminate the correlation between different power consumption components and ensure that the final power consumption feature matrix can accurately describe the power consumption behavior of the chip in different security tasks. The power consumption feature matrix is ​​obtained.

[0029] Step 300: classify the security application tasks based on the power consumption characteristic matrix to obtain a multi-level security task classification table;

[0030] It should be noted that the task feature vector is constructed based on the power consumption feature matrix. The feature vector T=[t 1 ,t 2 ,t 3 ,t 4 ,t 5 ] contains five core variables, among which t 1 represents the usage rate of the key storage area, t 2 Represents the complexity of encryption operation, t 3 Represents the frequency of identity authentication, t 4 represents the amount of data transmitted, and t 5 Represents the time constraint. By calculating these characteristic variables and integrating them into the task feature vector set, the key characteristics of different security tasks are described. The security sensitivity of the task feature vector set is calculated to obtain the task security sensitivity score so that the task can be classified according to its importance and security risk. The method of security sensitivity calculation adopts a weighted calculation method, that is, different weights are assigned to each component in the task feature vector, and the security sensitivity score of the task is calculated comprehensively. By calculating the security sensitivity score of all tasks, the quantitative evaluation results of the task under different security requirements are obtained. The security sensitivity score of the task is calculated according to the preset threshold TH 1 and TH 2 Segmentation is performed to complete the preliminary task classification. 1 When the security sensitivity score of the task is between TH 1 and TH 2 When the security sensitivity score of the task is less than TH, the task is classified as medium security level operation, including general data encryption, short key encryption and low-frequency identity authentication tasks; when the security sensitivity score of the task is less than TH 2 , the task is classified as a low-security level operation, including ordinary data transmission, simple identity authentication or non-core security computing tasks. Through classification, tasks of different security levels are guaranteed to receive corresponding resource allocation during execution, thereby optimizing power consumption management while ensuring security. The resource requirements of each type of task are analyzed to ensure that the system can reasonably schedule computing resources. For each type of task in the initial task classification result, the resource utilization vector R=[r 1 ,r 2 ,r 3 ], where r 1 represents the key storage area utilization, r 2 represents the utilization rate of the encryption computing unit, r 3represents the utilization rate of the identity authentication processor. In order to obtain an accurate resource demand matrix, the usage of each functional module is recorded during the task execution process, and the consumption of different resources for each task is calculated by combining factors such as the task execution time and computing intensity. A task resource demand matrix is ​​constructed, which reflects the demand for computing resources for tasks of different security levels. Task scheduling priority analysis is performed based on the task resource demand matrix to ensure that tasks can be scheduled in a reasonable order. The core of task scheduling priority analysis is to comprehensively consider factors such as the security level of the task, the computing resource occupancy, and time constraints, so as to calculate the priority sequence of the task. In the analysis process, a scheduling strategy based on resource load balancing is adopted, that is, when multiple tasks compete for computing resources at the same time, high security level tasks are scheduled first, and medium security level tasks and low security level tasks are inserted when resources allow. At the same time, a dynamic scheduling method is adopted, that is, according to the current resource occupancy of the system, the task execution order is adjusted in real time to avoid long-term idleness or overload of computing resources. The task priority sequence is associated and mapped with the security level classification results to ensure that the scheduling priorities of tasks with different security levels are consistent with their security requirements, so as to give priority to meeting the computing needs of high-security level tasks when resources are limited, while ensuring that medium-security level tasks and low-security level tasks can be executed at the appropriate time, forming a multi-level security task classification table.

[0031] Step 400: Execute the differential power consumption attack protection strategy according to the multi-level security task classification table, and calculate the operating voltage and frequency configuration sequence of each security function module.

[0032] Specifically, a differential power attack protection strategy is implemented on the multi-level security task classification table to quantify the information exposed by different tasks at the power consumption level and calculate the power leakage risk coefficient of each task. The calculation of the power leakage risk coefficient depends on multiple factors, including the volatility of power consumption during task execution, the predictability of power consumption characteristics, and the impact of computing load on the power consumption curve. The task power consumption is analyzed in time series, and the distinguishability of different tasks in the power domain is calculated by statistical methods. Based on these analysis results, a task power leakage risk matrix is ​​constructed, which is used to quantify the power leakage risk of different security tasks. A power obfuscation function is constructed according to the task power leakage risk matrix to reduce the predictability of power consumption characteristics and prevent attackers from obtaining key information through differential power analysis (DPA). The core idea of ​​the power obfuscation function is to introduce additional computing loads or randomized operations when executing security tasks to mask the power consumption mode of key operations. A set of power obfuscation parameter sets is generated based on the task power leakage risk matrix, which includes the random power perturbation amplitude, redundant computing strategy, and dynamic power adjustment factor that can be introduced during the execution of different tasks, and ensures that these obfuscation parameters will not affect the correct execution of the tasks. When calculating the power obfuscation parameters, balance security and energy efficiency, that is, ensure that the power consumption mode is sufficiently randomized to prevent DPA attacks, and avoid excessive energy consumption to maintain the goal of low power design. The power obfuscation parameter set is input into the dynamic power balancer to dynamically balance the power consumption of each security function module and ensure that the overall power consumption is evenly distributed, thereby reducing the predictability of power analysis. The role of the dynamic power balancer is to dynamically adjust the working state of each functional module during task execution, so that the power consumption shows a small difference between different tasks and avoids obvious exposure of power consumption characteristics. To achieve this goal, a set of power balance constraints is constructed, which stipulates the maximum change amplitude, power consumption disturbance frequency and random switching probability distribution that the power consumption of each functional module should meet under different security tasks. By satisfying these constraints, it is effectively prevented from inferring key data by comparing the power consumption characteristics of different tasks, thereby improving the security of the chip. Based on the power balance constraints, a working state transition matrix is ​​constructed, and the Markov chain model is used to calculate the optimal state transition sequence to obtain a dynamic working state configuration table. The working state transition matrix is ​​used to describe the state switching relationship of each safety function module during the execution of different tasks, while the Markov chain model is used to optimize the state transition path to minimize the predictability of power consumption characteristics. By combining the two, it is ensured that the chip switches different working states in the best way when executing different tasks, and reduces power consumption while ensuring safety. When calculating the state transition sequence, the execution time, computing load and resource usage of the task are considered to avoid additional energy consumption caused by frequent state switching.The dynamic working state configuration table provides a set of optimized working state scheduling schemes, so that the chip can work with the minimum power consumption exposure risk during the execution of different tasks. In order to optimize the state switching process, the dynamic working state configuration table is subjected to timing constraint analysis, and a state switching timing diagram that meets the clock offset range and voltage fluctuation range is generated. The purpose of the timing constraint analysis is to ensure that the system will not be unstable or execute errors due to too fast or too slow voltage adjustment during state switching. In the timing analysis process, a timing optimization model is established in combination with the chip's operating frequency, power supply voltage adjustment time, and the execution cycle of the computing task to ensure that the state switching can be completed within a reasonable time window. According to the execution requirements of tasks with different security levels, the timing of state switching is optimized so that high-security tasks can be completed in a shorter time, while low-security tasks can be switched smoothly in a longer time. Based on the timing optimization results, an optimized state switching control sequence is obtained, which specifies the working state switching order of different safety function modules at different time points and ensures that the switching process does not affect the stability of task execution. The state switching control sequence is grouped and mapped to generate the working voltage and frequency configuration sequence of each safety function module containing voltage and frequency configuration parameters, switching timing requirements, and safety constraints. According to the security level, computing requirements and state switching control sequence of the task, the operating voltage and frequency of different security function modules are grouped, and different voltage and frequency adjustment strategies are set for high security level tasks, medium security level tasks and low security level tasks. For high security level tasks, a higher randomized power consumption perturbation is used to cover up the power consumption characteristics in the computing process to the greatest extent, while for medium security level tasks and low security level tasks, a lower power consumption perturbation strategy is used to reduce energy consumption as much as possible while ensuring safety.

[0033] The working voltage and frequency configuration sequence is decomposed into voltage control parameters and frequency control parameters. Among them, the voltage control parameters are used to adjust the supply voltage of the chip to adapt to the power consumption requirements of different security tasks, while the frequency control parameters are used to adjust the working clock frequency of the chip to ensure a dynamic balance between computing efficiency and power consumption. In order to effectively manage frequency regulation, a digital phase-locked loop is used to phase modulate the clock signal and generate a clock modulation parameter set. Through the phase-locked loop technology, accurate clock signal adjustment is achieved, so that the clock frequency can smoothly transition between different task modes, and at the same time enhance the system's resistance to external interference. After obtaining the clock modulation parameter set, the clock signal is extended modulated to increase the randomness of the power consumption characteristics, thereby reducing the risk of side channel attacks such as differential power consumption analysis. A pseudo-random sequence generation algorithm is used, and a linear feedback shift register is used to generate an m-sequence, and spread spectrum modulation is performed on the clock signal to obtain a randomized clock sequence. The m-sequence is a pseudo-random sequence with good statistical properties, which can generate uniformly distributed binary signals over a long period, thereby introducing unpredictable change patterns in the clock modulation process. Through spread spectrum modulation, the instantaneous frequency of the clock signal is constantly changing, thereby breaking the direct correspondence between power consumption characteristics and computing operations, making it difficult for attackers to infer key information from the power consumption trajectory. The randomized clock sequence can also effectively alleviate the electromagnetic leakage problem and improve the anti-interference ability of the system. Based on the randomized clock sequence, voltage noise injection is performed to increase the randomness of the chip's power consumption. The pulse width modulation (PWM) technology is used to dynamically adjust the power supply voltage, and the voltage modulation sequence is generated by a digital voltage regulator. The randomized clock sequence is used as a noise source and input into the voltage regulator to generate a voltage jitter waveform. This voltage jitter can effectively interfere with power consumption analysis and make the power consumption curve of encryption operations more complex and unpredictable. The duty cycle of the power supply voltage is adjusted by PWM to control the voltage change amplitude and rate, and to ensure that the voltage modulation does not affect the normal operation of the system. In this way, dynamic power management is achieved without affecting the accuracy of calculations, and the success rate of differential power consumption attacks is effectively reduced. The voltage modulation sequence and the randomized clock sequence are synchronously controlled to ensure that they can work together in different task execution stages and play their maximum effectiveness. The module modulation control word is constructed, which contains voltage modulation, clock modulation and corresponding synchronization parameters, and is used to coordinate the dynamic power consumption adjustment of different functional modules. The core of synchronous control is to keep the clock frequency change and the voltage modulation process time matching to avoid calculation errors caused by phase differences. In order to achieve precise synchronous control, an adaptive adjustment mechanism is introduced to enable the control word to be dynamically adjusted according to real-time feedback during operation, thereby ensuring the stability of the system and the power consumption optimization effect. The module modulation control word is grouped and encoded, and an instruction packet containing clock frequency, operating voltage, modulation parameters and switching timing is generated for parsing and execution during actual operation.The design of the instruction package follows the instruction set architecture of the CPU card security chip to ensure that the power consumption adjustment of different functional modules can be efficiently controlled. The parsing and execution of the instruction package are completed by a finite state machine. The state machine selects the appropriate modulation scheme according to the task type and security level, and performs state switching at the appropriate time. In this way, dynamic and adjustable power management is achieved, and it is ensured that each security function module can work together in the best way. After completing the above low power consumption and security optimization, the generated anti-side channel attack control instruction flow is tested for security performance to verify the actual effect of the optimization scheme. During the security performance test, key indicators such as encryption operation speed, identity authentication response time, and power consumption balance are focused on. By measuring the execution time of encryption operations, the impact of clock modulation and voltage regulation on computing efficiency is evaluated to ensure that the optimized system can still meet the real-time requirements of security applications. By testing the response time of identity authentication, it is analyzed whether randomized power consumption adjustment causes delays in the identity authentication process, and relevant parameters are optimized to improve the user experience of the system. By counting the power consumption fluctuations during the execution of different tasks, the power consumption balance is calculated, and the effectiveness of the power consumption optimization strategy in reducing the predictability of power consumption characteristics is evaluated. Based on these test results, a comprehensive evaluation report of the security chip is generated.

[0034] Based on the control instruction flow of anti-side channel attack, the current waveform in the encryption operation process is collected to obtain the original data reflecting the power consumption characteristics of the chip. A high-precision oscilloscope or a dedicated power consumption analysis device is used to monitor the current changes of the chip in different working modes in real time, and the environmental noise is removed by signal processing methods to ensure the accuracy of the collected data. Through this step, the power leakage assessment parameters used to assess the risk of power leakage are obtained. Security measurement and multidimensional clustering analysis are performed based on the power leakage assessment parameters to evaluate the chip's ability to resist side channel attacks. The key to security measurement is to analyze the predictability of power consumption data, that is, whether the power consumption characteristics can be used by attackers to infer encryption keys. Differential power consumption analysis or correlation power consumption analysis methods are used to simulate attacks on power consumption data, and the number of samples required to successfully extract the key is calculated. If the difficulty of key recovery is high, it means that the power consumption obfuscation strategy of the chip is more effective and has higher security. Using multidimensional clustering analysis technology, the power consumption data under different working modes are classified to observe the distribution of power consumption characteristics of encryption operations. If the power consumption characteristics can be effectively clustered, it means that the power consumption leakage characteristics of the chip are more obvious and there is a security risk. If the power consumption characteristics show a highly dispersed distribution, it means that the chip has a good ability to resist side channel attacks. Through these analyses, the security strength score of the chip is calculated, and quantitative indicators are provided for security under different working conditions. The encryption operation performance of the CPU card security chip under different key lengths is analyzed to evaluate its computing power under different security levels. The encryption operation speed, data throughput and operation delay of the chip under 128-bit, 256-bit and 512-bit key lengths are recorded respectively to construct an encryption performance data set. The encryption operation speed is calculated by measuring the time it takes the chip to execute the complete encryption process, while the data throughput is measured by the amount of data processed per unit time. The operation delay reflects the processing efficiency of the encryption task under different key lengths and can help identify the impact of power optimization strategies on computing performance. Through these measurements, a complete encryption performance data set is constructed. A comprehensive performance evaluation is performed on the encryption performance data set to calculate the performance evaluation score of the chip. A weighted scoring model is constructed based on task completion time, energy consumption indicators and throughput, and is tuned according to the needs of different application scenarios. The performance evaluation score is weighted and integrated with the security strength score to obtain a more representative chip evaluation result matrix. The chip evaluation result matrix is ​​hierarchically mapped to generate a comprehensive security chip evaluation report. In the hierarchical mapping process, the scoring interval is constructed according to the different dimensions of the evaluation matrix, and the chip's security, performance, and power optimization capabilities are divided into multiple levels. The energy consumption trend of the chip is plotted based on the power consumption characteristic curve, and combined with the security protection capability analysis results, the chip's anti-interference ability under different attack models is demonstrated. At the same time, a detailed encryption operation performance table is constructed using performance test data to compare the computing efficiency under different key lengths and provide optimization suggestions for different application scenarios.Through the above steps, a complete security chip comprehensive evaluation report is formed.

[0035] In the embodiment of the present application, by establishing a refined power consumption characteristic model, combined with 16-bit high-precision sampling and multi-dimensional data analysis, the dynamic power consumption characteristics of each security function module of the CPU card security chip are accurately characterized, the security sensitivity analysis method is used to classify the tasks in multiple levels, and the optimal configuration sequence is generated through the dynamic power consumption balancing algorithm, which reduces the overall power consumption while ensuring the performance requirements of tasks of different security levels. The randomized clock modulation and voltage jitter technology are innovatively introduced, and the dynamic obfuscation of the power consumption waveform is realized by constructing a time-space interleaving matrix, which effectively enhances the chip's ability to resist differential power consumption analysis attacks. A systematic performance evaluation method is designed, and a comprehensive evaluation of the chip's security performance, computing efficiency and power consumption characteristics is achieved through a comprehensive analysis of multi-dimensional indicators. The working state switching strategy is optimized based on the Markov chain model and fuzzy control algorithm, which reduces the power consumption overhead during the state transition process and improves the energy utilization efficiency of the system. By combining piecewise linear fitting and dynamic balancing control, the optimal balance between power consumption and performance is achieved under different key lengths, significantly improving the overall performance of the CPU card security chip.

[0036] In a specific embodiment, the process of executing step 100 may specifically include the following steps:

[0037] The key storage area, encryption operation unit and identity authentication processor of the CPU card security chip are sampled for current waveform to obtain original current sampling data;

[0038] Repeated sampling test is performed on the original current sampling data to obtain multiple groups of current waveform data, and the multiple groups of current waveform data are collected in sections to obtain voltage-frequency combination data;

[0039] The voltage-frequency combination data are classified and stored, and a peak power consumption data set during encryption operation, an average power consumption data set during identity authentication, and a working time data set during security calculation are established to obtain a power consumption characteristic data set;

[0040] The power consumption characteristic data set is grouped and fitted according to different key lengths to obtain the static power consumption and dynamic power consumption relationship matrix of each security function module. The static power consumption and dynamic power consumption relationship matrix is ​​subjected to principal component analysis to obtain the characteristic parameter set of the security function module.

[0041] Specifically, a high-precision oscilloscope or dedicated power consumption measurement equipment is used to collect real-time current while the chip is performing different tasks. The instantaneous current at , a series of discrete data points are obtained through high-frequency sampling ,in Representative The current value obtained by sampling is is the total number of samples. Sampling frequency Satisfies the Nyquist sampling theorem, that is, ,in is the highest power consumption change frequency that the chip may produce, to ensure the integrity and accuracy of the sampled data. Repeated sampling tests are performed on the original current sampling data to ensure the stability of the data and eliminate abnormal values ​​caused by external interference. Assume that Group data, each group of data contains sample points, then calculate the average current waveform at the same time point:

[0042]

[0043] in, Indicates Group sampling data at time This step can provide a smoother power consumption curve and reduce noise interference in a single measurement. At the same time, the standard deviation is calculated. To evaluate the stability of the current waveform:

[0044]

[0045] If the standard deviation is large, it means that the power consumption at that time point fluctuates greatly, and there are nonlinear factors or external interference in the calculation process, which requires further analysis and processing. Collect multiple sets of current waveform data in segments to obtain voltage-frequency combination data. Divide the entire task execution process into different calculation stages, such as key loading stage, encryption calculation stage, identity authentication stage, etc., in order to more finely analyze the power consumption characteristics of each functional module. Assume that the operating voltage of the chip is The operating frequency is , then in each time window The voltage and frequency changes are recorded within a time window, and the average power consumption within the time window is established:

[0046]

[0047] in, Indicates the average power consumption value within the time window. and are voltage and current respectively. By processing each calculation stage, the power consumption characteristic data under different voltages and frequencies are obtained. The voltage-frequency combination data is classified and stored so as to establish the peak power consumption data set during encryption operation, the average power consumption data set during identity authentication, and the working time data set during security calculation, forming a complete power consumption characteristic data set. Assuming the peak power consumption of encryption operation is is the maximum power consumption value within a certain time window during the operation, which is expressed as:

[0048]

[0049] in It is the power consumption data of all time windows. Average power consumption during identity authentication It is expressed as:

[0050]

[0051] in, is the execution time of the identity authentication task. The working time dataset of security computing records the execution time of each task for subsequent scheduling optimization. The power consumption characteristic dataset is grouped and fitted according to different key lengths to establish the static power consumption and dynamic power consumption relationship matrix of each security function module. Assuming the key length is bits, then the static power consumption and dynamic power consumption The following formulas are used to fit:

[0052]

[0053]

[0054] in, is the fitting coefficient, It represents the basic power consumption of the chip under no load condition, and Represents the additional power consumption caused by the computing task. These parameters are fitted by the least squares method to establish the power consumption relationship matrix under different key lengths:

[0055]

[0056] Perform principal component analysis on the static power consumption and dynamic power consumption relationship matrix to extract the main factors affecting power consumption changes and reduce the data dimension. Assume that the power consumption data matrix is:

[0057]

[0058] Each row corresponds to a different key length, and each column corresponds to different task power consumption data. By calculating the covariance matrix:

[0059]

[0060] And solve for the eigenvalues ​​and eigenvectors:

[0061]

[0062] Find the characteristic components that mainly affect the power consumption change, retain the most important principal components, and obtain the characteristic parameter set of the safety function module.

[0063] In a specific embodiment, the process of executing step 200 may specifically include the following steps:

[0064] Performing data segmentation on the characteristic parameter set of the security function module to obtain multiple groups of key length power consumption data;

[0065] An encryption operation power consumption model is constructed based on multiple groups of key length power consumption data, and the encryption operation power consumption model is segmented, and linear fitting is performed in each sub-interval after the segmentation process to obtain a piecewise linear model coefficient group;

[0066] The identity authentication power consumption model is constructed based on the piecewise linear model coefficient group, and the encryption operation power consumption model and the identity authentication power consumption model are matrix transformed under different key length conditions to obtain a power consumption feature mapping table;

[0067] The power consumption feature mapping table is subjected to feature decomposition and orthogonal transformation to obtain the power consumption feature matrix under different key lengths.

[0068] Specifically, the power consumption of the CPU card security chip under different key lengths is accurately measured, and the corresponding data set is constructed. Assume that in a certain experiment, the chip performs encryption operations and identity authentication tasks under 128-bit, 256-bit and 512-bit key lengths, and records its power consumption data, where each data point is represented as ,in represents the key length, Represents time, Represents that the key length is time Instantaneous power consumption value at . In order to ensure the accuracy of the data, sampling is performed under multiple experimental conditions and the average power consumption curve is calculated:

[0069]

[0070] in, represents the total number of experiments, and Representative The sampling data of the experiment is obtained. Through this step, the random fluctuations in a single experiment are eliminated, and more stable power consumption characteristic data is obtained. The encryption operation power consumption model is constructed based on multiple sets of key length power consumption data, and it is segmented to improve the fitting accuracy. The piecewise linear fitting method is used to divide the entire data interval into several sub-intervals, and linear regression is used in each sub-interval to approximate the power consumption change. Assume that the total power consumption of the encryption operation Expressed as a piecewise linear function, a linear fitting model is defined in each subinterval:

[0071]

[0072] in, and is the fitting coefficient, representing the The encrypted power consumption change rate and initial power consumption offset within each sub-interval, is the cutoff point for the key length. To solve these fitting coefficients, the least squares method is used:

[0073]

[0074] in, represents the number of measurement samples in the subinterval, It is The actual measured value of the sample points, is the model prediction value. Through this step, a more accurate encryption operation power consumption model is established within different key length ranges. After completing the piecewise fitting of the encryption operation power consumption model, the identity authentication power consumption model is constructed based on the piecewise linear model coefficient group. Since the identity authentication task involves key access and computing operations, its power consumption characteristics are similar to those of encryption operations, but they show different trends in different computing stages. Assuming that the identity authentication power consumption Power consumption of encryption operation After linear transformation, it is expressed as:

[0075]

[0076] in, Represents the power consumption ratio of authentication and encryption operations, Represents the additional power consumption during the authentication process, such as random number generation or storage access. and The specific value of is used to perform regression analysis using experimental data to ensure that the authentication power consumption model can accurately reflect the power consumption characteristics under different key lengths. After obtaining the encryption operation power consumption model and the authentication power consumption model, matrix transformation is performed under different key length conditions to construct a power consumption feature mapping table. The encryption operation power consumption vector is set to:

[0077]

[0078] The power consumption vector for identity authentication is:

[0079]

[0080] In order to obtain a unified power consumption feature mapping table, a transformation matrix is ​​constructed:

[0081]

[0082] The authentication power consumption data is calculated through matrix transformation:

[0083]

[0084] This mapping table is used to describe the power consumption relationship of different tasks and provide a basis for optimizing the allocation of computing resources. In order to extract the main influencing factors of power consumption characteristic data, the power consumption characteristic mapping table is subjected to characteristic decomposition and orthogonal transformation to obtain the power consumption characteristic matrix under different key lengths. Construct the power consumption covariance matrix:

[0085]

[0086] in, Represents the power consumption data under different key lengths, is the mean power consumption vector. Perform eigenvalue decomposition on the covariance matrix:

[0087]

[0088] in, is the eigenvector matrix, It is a diagonal eigenvalue matrix. By selecting the eigenvector corresponding to the maximum eigenvalue, the main dimension that affects the power consumption change is found, and the data is projected into a new coordinate system using orthogonal transformation to reduce data redundancy and improve computational efficiency.

[0089] Before classifying the security application tasks based on the power consumption feature matrix, the method further includes: executing a long sequence dual prediction algorithm on the power consumption feature matrix, constructing a prediction model P(t)=w1×F(tk)+w2×G(t+k), wherein F(tk) is a predicted value of a historical power consumption sequence, G(t+k) is a predicted value of a future power consumption sequence, w1 and w2 are weight coefficients, and obtaining a power consumption data prediction sequence; inputting the power consumption data prediction sequence into a self-attention encoder, extracting time series features Q=[q1,q2,...,qn] through a multi-head attention mechanism, wherein qi is an attention weight vector of the i-th time step, and obtaining a power consumption feature encoding matrix; calculating an adaptive threshold θ=μ×mean(|Q|)+σ×std(|Q|) for the power consumption feature encoding matrix, wherein mean(|Q|) is a feature amplitude mean, std(|Q|) is a feature amplitude standard deviation, and μ and σ are adjustment coefficients, and obtaining a feature screening threshold; compressing the power consumption data stream based on the feature screening threshold, and minimizing the reconstruction error function E=||Q-Q'|| 2 Select key feature points to obtain a compressed power consumption feature sequence; input the compressed power consumption feature sequence into a recurrent neural network, use long short-term memory units to extract the timing dependency, and build a power consumption prediction model M=LSTM(Q compressed ), and obtain the power consumption predictor; the power consumption predictor is trained online, the model parameters are updated by the sliding window method, and the prediction error is minimized by the Adam optimizer to obtain the adaptive power consumption prediction model; the adaptive power consumption prediction model is applied to the real-time power consumption data stream to realize the compression transmission of high-frequency power consumption data, and the compression ratio η=(1-L compressed / L original )×100% to obtain the data compression efficiency index; the power consumption characteristics are reconstructed based on the data compression efficiency index, and the interpolation algorithm is used to restore the power consumption characteristics under the original sampling rate. The reconstruction quality is evaluated by the signal-to-noise ratio to obtain the power consumption characteristic matrix.

[0090] In a specific embodiment, the process of executing step 300 may specifically include the following steps:

[0091] Construct task feature vector T=[t 1 ,t 2 ,t 3 ,t 4 ,t 5 ], where t 1 is the key storage area usage rate, t 2 is the encryption operation complexity, t 3 is the authentication frequency, t 4 is the data transmission volume, t 5 For time constraints, we obtain a set of task feature vectors;

[0092] Calculate the security sensitivity of the task feature vector set to obtain the task security sensitivity score;

[0093] The task security sensitivity score is calculated according to the threshold TH 1 and TH 2 Divide the segment and divide the score greater than TH 1 The tasks are divided into high security level operations, and the scores between TH 1 and TH 2 The tasks between them are classified as medium security level operations, and the scores less than TH 2 The tasks are divided into low-security level operations, and the initial task classification results are obtained;

[0094] Calculate the resource utilization vector R = [r 1 ,r 2 ,r 3 ], where r 1 is the key storage area utilization, r 2 is the utilization rate of encryption computing unit, r 3 is the authentication processor utilization, and the task resource requirement matrix is ​​obtained;

[0095] Based on the task resource requirement matrix, task scheduling priority analysis is performed to obtain the task priority sequence, which is then associated and mapped with the security level classification results to obtain a multi-level security task classification table.

[0096] Specifically, the task feature vector is constructed based on the power consumption feature matrix ,in is the key storage usage, is the encryption operation complexity, is the authentication frequency, is the data transmission volume, To constrain time, the characteristic information of each task in different computing environments is extracted based on the power consumption characteristic matrix of the chip. The power consumption characteristic matrix is ​​set as:

[0097]

[0098] in, Indicates Tasks in the feature dimension By normalizing the characteristic parameters of different tasks, the task feature vector is constructed. :

[0099]

[0100] in, Calculated as:

[0101]

[0102] in, For the The size of the key storage area occupied by each task, is the maximum key storage capacity of the chip. Similarly, the encryption operation complexity It is expressed as:

[0103]

[0104] in, is the computational complexity of the task, which is determined by the number of operations and computational depth of the encryption algorithm, and The highest computational complexity supported by the chip. Indicates the number of times the task performs identity authentication per unit time. It is calculated as follows:

[0105]

[0106] in, is the number of authentication calls for the task, It is the maximum authentication frequency allowed by the system. Data transmission volume Determined by the amount of data read and written by the task:

[0107]

[0108] in, is the data transfer volume of the task, and is the maximum data throughput. Time constraint Reflects the ratio of the time required to complete the task to the system time constraint:

[0109]

[0110] in, is the task completion time, and is the maximum allowed execution time set by the system. Through these calculations, we get the task feature vector set . Security sensitivity is calculated for the task feature vector set to assess the risks of different tasks in terms of power leakage and security. Security sensitivity score Calculated by the weighted sum of the task feature vectors:

[0111]

[0112] in, is a weight parameter, which indicates the influence of each feature on security sensitivity. For example, the influence of encryption operation complexity on security is greater than the data transmission volume, so Greater than Based on the calculated security sensitivity score, it is set according to the set threshold and If , then the task is classified as a high-security operation. , then the task belongs to medium security level operation, and when When , the task is classified as a low-security operation. This segmentation ensures that different tasks are reasonably scheduled according to security requirements. After completing the initial task classification, the resource utilization of each task is calculated to optimize the allocation of computing resources. Set the task resource utilization vector as follows:

[0113]

[0114] in, Indicates the key storage area utilization, which is calculated as:

[0115]

[0116] in, Is the currently available storage capacity. Encryption computing unit utilization for:

[0117]

[0118] in, is the available computing resources. Identity authentication processor utilization The calculation is as follows:

[0119]

[0120] in, is the current available frequency of the authentication processor. By calculating the resource utilization of all tasks, the task resource requirement matrix is ​​constructed:

[0121] ;

[0122] Based on this matrix, task scheduling priority analysis is performed. Task Priority Calculated by weighting resource utilization and security sensitivity:

[0123]

[0124] in, and is the scheduling weight parameter, which determines the relative importance of security and resource utilization. After calculating the priorities of all tasks, the task priority sequence is obtained , and arranged in descending order. The task priority sequence is associated and mapped with the security level classification results to generate a multi-level security task classification table. This table divides the task execution order according to the security level and priority of the task, and ensures that high-security tasks are executed first when resources allow.

[0125] In a specific embodiment, the process of executing step 400 may specifically include the following steps:

[0126] Implement the differential power consumption attack protection strategy on the multi-level security task classification table, calculate the power consumption leakage risk coefficient of each task, obtain the task power consumption leakage risk matrix, and construct the power consumption obfuscation function according to the task power consumption leakage risk matrix to obtain the power consumption obfuscation parameter set;

[0127] Input the power consumption obfuscation parameter set into the dynamic power consumption balancer, dynamically balance the power consumption of each security function module, and obtain the power consumption balance constraint condition;

[0128] Based on the power consumption balance constraint condition, the working state transition matrix is ​​constructed, and the optimal state transition sequence is calculated using the Markov chain model to obtain the dynamic working state configuration table;

[0129] Perform timing constraint analysis on the dynamic working state configuration table, generate a state switching timing diagram that meets the clock offset range and voltage fluctuation range, and optimize the switching timing to obtain the state switching control sequence;

[0130] The state switching control sequence is grouped and mapped to generate the working voltage and frequency configuration sequence of each safety function module including voltage and frequency configuration parameters, switching timing requirements and safety constraints.

[0131] Specifically, the power leakage risk coefficient of each task is calculated to quantify the possibility of different security tasks being attacked due to power consumption feature leakage during execution. As a task The probability that the attacker can infer the key through power consumption analysis during execution is determined by the power consumption characteristic change rate, execution time, and power consumption pattern similarity of the task. The power consumption curve is , then the power leakage risk is defined as:

[0132]

[0133] in, For the task execution time, and Represents the power consumption change rate. A higher power consumption change rate means a more obvious power consumption feature, which increases the possibility of a successful DPA attack. By calculating the power consumption leakage risk coefficient of all tasks, a task power consumption leakage risk matrix is ​​constructed:

[0134]

[0135] in, Representation Task In the security module Based on this matrix, a power consumption obfuscation function is constructed to artificially introduce randomness in the calculation process and reduce the possibility of attackers extracting key information. for:

[0136]

[0137] in, is the power consumption disturbance term, which is dynamically adjusted through a pseudo-random number generator so that the power consumption curve is different each time the same task is executed. The power consumption disturbance term is defined as:

[0138]

[0139] in, is the disturbance amplitude, is the random frequency, is the phase shift. By setting different and , effectively obfuscating the power consumption characteristics. Based on this power consumption obfuscation strategy, generate the power consumption obfuscation parameter set:

[0140]

[0141] Among them, each pair Corresponding tasks The parameter set is input into the dynamic power balancer to dynamically adjust the power consumption of each safety function module so that it can maintain a stable change when executing tasks. Assume that the target power consumption balance value of a module is , then the equilibrium condition is expressed as:

[0142]

[0143] in, is the allowable power consumption fluctuation range. After satisfying this constraint, the working state transition matrix is ​​constructed based on the power consumption balancing result to optimize the power consumption mode of task execution. The working state transition matrix is ​​defined as:

[0144]

[0145] in, Indicates that the task is from the state Switch to status The Markov chain model is used to calculate the optimal state transition sequence to determine the optimal state scheduling scheme for task execution. Assume that the state probability distribution vector is , then the state transition follows:

[0146]

[0147] By solving the steady-state distribution , get the optimal execution state of the task, and generate a dynamic working state configuration table. Perform timing constraint analysis on the dynamic working state configuration table to ensure that the state switching complies with the clock offset range and voltage fluctuation range of the chip. Set the maximum allowed clock offset to and the maximum voltage fluctuation is , then the state switching sequence should satisfy:

[0148]

[0149] Based on this constraint, the state switching timing is optimized to maintain a smooth transition between different tasks and avoid security vulnerabilities caused by sudden changes in power consumption. The optimized state switching control sequence is grouped and mapped to generate an operating voltage and frequency configuration sequence that includes voltage and frequency configuration parameters, switching timing requirements, and security constraints. The final configuration sequence is defined as:

[0150]

[0151] in, For the The supply voltage for each task, is the operating frequency, This configuration sequence is used for dynamic adjustment during chip operation to ensure that the protection against side channel attacks is improved while meeting low power consumption requirements.

[0152] In this embodiment, before constructing a differential power consumption attack protection strategy according to the multi-level security task classification table, it also includes: performing power consumption feature analysis on the multi-level security task classification table, constructing a power consumption fluctuation sequence, extracting time-frequency features through wavelet transform, and obtaining a power consumption leakage feature set; establishing an attack pattern recognition network based on the power consumption leakage feature set, using a multi-layer convolution structure to extract local features, and learning the temporal dependency through long short-term memory units to obtain an attack feature representation vector; inputting the attack feature representation vector into a deep reinforcement learning environment, designing a protection reward function, and obtaining a protection optimization target; constructing a dual Q learning network for the protection optimization target, mapping the current state and the protection action to a Q value, and performing parameter learning through an experience replay mechanism and a target network update strategy to obtain a protection strategy network; based on The protection strategy network adopts a distributed training method, builds multiple parallel environments and collects protection experience at the same time, optimizes network parameters through the policy gradient method, and obtains a robust protection model; combines the robust protection model with the key length information, generates differentiated power consumption obfuscation schemes for tasks with different security levels, and realizes reasonable allocation of protection resources by dynamically adjusting the obfuscation intensity to obtain an adaptive protection strategy; conducts attack tests and verification on the adaptive protection strategy, evaluates the protection effect by injecting simulated differential power consumption attack signals, records the power consumption leakage rate and system overhead, and obtains the protection performance index; inputs the protection performance index into the optimization controller, performs online tuning based on the real-time attack intensity and system status, generates the optimal protection configuration that meets the security and efficiency requirements, and obtains the differential power consumption attack protection strategy.

[0153] In a specific embodiment, the low power consumption design method for executing the CPU card security chip also includes the following steps:

[0154] Decomposing the operating voltage and frequency configuration sequence into voltage control parameters and frequency control parameters, using a digital phase-locked loop to perform phase modulation on the clock signal, and generating a clock modulation parameter set;

[0155] A pseudo-random sequence generation algorithm is executed on the clock modulation parameter set, an m-sequence is generated through a linear feedback shift register, and a spread spectrum modulation is performed on the clock signal to obtain a randomized clock sequence;

[0156] Perform voltage noise injection based on the randomized clock sequence to obtain a voltage jitter waveform, and input the voltage jitter waveform into a digital voltage regulator to dynamically adjust the supply voltage through pulse width modulation to obtain a voltage modulation sequence;

[0157] Performing synchronous control on the voltage modulation sequence and the randomized clock sequence to obtain a module modulation control word;

[0158] The module modulation control word is grouped and encoded to generate an instruction packet containing clock frequency, working voltage, modulation parameters and switching timing, which is parsed and executed through the state machine to obtain a control instruction flow that is resistant to side channel attacks;

[0159] The control instruction flow to combat side-channel attacks performs security performance tests, records encryption operation speed, authentication response time, and power consumption balance, and generates a comprehensive security chip evaluation report.

[0160] Specifically, the operating voltage and frequency configuration sequence is decomposed into voltage control parameters and frequency control parameters. The dynamic operating environment of the chip is analyzed, and the optimal voltage and frequency settings for different computing tasks are extracted. The working voltage is , the operating frequency is , then it is decomposed into voltage control parameters and frequency control parameters ,in:

[0161]

[0162]

[0163] in, and Represent the system's reference operating voltage and reference operating frequency respectively, and and The voltage and frequency offsets are adjusted based on dynamic power optimization and side channel attack resistance strategies. A digital phase-locked loop is used to phase modulate the clock signal to generate a clock modulation parameter set, thereby achieving dynamic adjustment of the clock signal during operation. The output frequency of the digital phase-locked loop It is expressed as:

[0164]

[0165] in, is the reference clock frequency, and is the adjustable frequency division factor of the phase-locked loop, by adjusting The clock frequency of the chip is dynamically controlled to keep it randomly changing during the execution of different tasks, thereby increasing the protection against side channel attacks. The clock modulation parameter set is defined as:

[0166]

[0167] Among them, each pair Corresponding to the clock modulation parameters under a task state. After obtaining the clock modulation parameter set, execute the pseudo-random sequence generation algorithm to improve the randomness of the clock signal and prevent attackers from analyzing the power consumption characteristics through a fixed clock mode. Use a linear feedback shift register to generate an m-sequence to perform spread spectrum modulation on the clock signal. The generated m-sequence is defined as:

[0168]

[0169] in, is the feedback coefficient, It's time The m-sequence value at . By performing spread spectrum modulation on the clock signal, the randomized clock sequence is obtained:

[0170]

[0171] in, The frequency spectrum is spread to make the change of the clock signal unpredictable, thereby enhancing the ability to resist side channel attacks. Based on the randomized clock sequence, voltage noise injection is performed to increase the randomness of power consumption during chip operation. Assuming that the voltage noise It is composed of the superposition of high-frequency disturbance signals, which can be expressed as:

[0172]

[0173] in, is the voltage jitter amplitude, is the noise injection frequency, The voltage jitter waveform is input into the digital voltage regulator, and the supply voltage is dynamically adjusted through pulse width modulation (PWM), so that the final voltage modulation sequence It consists of a reference voltage, a noise injection term, and a clock modulation term:

[0174]

[0175] This method can effectively reduce the stability of power consumption characteristics, making it difficult for attackers to analyze through fixed power consumption modes. The voltage modulation sequence and the randomized clock sequence are synchronously controlled to ensure that the two change in coordination during system operation to form the final module modulation control word. Set the module modulation control word for:

[0176]

[0177] in, The time interval for updating the modulation parameters is used to ensure that the system switches states at the appropriate time point to avoid affecting the computing stability. The module modulation control words are grouped and encoded, and an instruction packet containing clock frequency, operating voltage, modulation parameters and switching timing is generated so that it can be parsed and executed during the chip operation. Set the instruction packet for:

[0178]

[0179] Among them, each The modulation parameters of the corresponding chip in a certain task state. The state machine is used to parse the instruction packet and perform the corresponding voltage and frequency adjustment operations to form a control instruction flow that resists side channel attacks. :

[0180]

[0181] in, Represents parsing and application during state machine execution The control instruction flow against side channel attacks performs security performance tests to verify its effectiveness in the actual operating environment. Set the encryption operation speed for:

[0182]

[0183] in, To encrypt the data volume, Is the encryption operation time. Authentication response time Defined as:

[0184]

[0185] in, The time when the identity authentication request was initiated. The time it takes to complete the authentication. It can be calculated as:

[0186]

[0187] in, For the moment The power consumption, is the average power consumption, By recording these key performance parameters, a comprehensive security chip evaluation report is generated, including the chip's computing efficiency, power consumption distribution, and anti-attack capabilities in different security modes, thereby optimizing low-power design and improving chip security and energy efficiency.

[0188] In a specific embodiment, the process of executing the control instruction flow of the step of resisting the side channel attack to perform security performance test, record the encryption operation speed, authentication response time and power consumption balance, and generate a comprehensive evaluation report of the security chip can specifically include the following steps:

[0189] Based on the control instruction flow that resists side channel attacks, the current waveform during the encryption operation is collected to obtain the power consumption leakage assessment parameters;

[0190] Security measurement and multi-dimensional cluster analysis are performed based on power consumption leakage assessment parameters to obtain security strength scores;

[0191] Based on the security strength score, the encryption operation speed, data throughput and operation delay of the CPU card security chip under 128-bit, 256-bit and 512-bit key lengths are recorded respectively to obtain the encryption performance data set;

[0192] Perform a comprehensive performance evaluation on the encryption performance data set to obtain a performance evaluation score, and perform a weighted fusion of the performance evaluation score and the security strength score to obtain a chip evaluation result matrix;

[0193] The chip evaluation result matrix is ​​hierarchically mapped to generate a comprehensive security chip evaluation report that includes power consumption characteristic curves, security protection capability analysis, and performance test data.

[0194] Specifically, when the CPU card security chip runs an encryption task, its power consumption is measured with high precision. Set the instantaneous power consumption of the chip By working voltage and instantaneous current Calculated:

[0195]

[0196] in, Controlled by the dynamic voltage regulation module, Determined by the current fluctuation caused by the switching activity of the transistor during the encryption operation. In order to evaluate the power leakage, a high-speed sampling ADC (analog-to-digital converter) is used to record the current waveform and obtain a sequence of discrete sampling points:

[0197]

[0198] in, It is The sampling time, is the total number of samples. By calculating the power consumption change rate during the execution of the encryption task, the leakage risk parameter is obtained. :

[0199]

[0200] in, is the rate of change of current with time, the larger This indicates that the power consumption fluctuates violently and is more likely to be exploited by attackers. After obtaining the power consumption leakage assessment parameters, security measurement and multidimensional cluster analysis are performed to calculate the security strength score. . Set the feature vector of the task to:

[0201]

[0202] in, is the key length for encryption tasks, is the computational complexity, is the authentication frequency, is the data throughput, is the execution time. By reducing the dimension through principal component analysis, the feature vector is projected into two-dimensional space, and the tasks are classified using the K-means clustering algorithm to obtain the safety level classification label of the task. :

[0203]

[0204] in, For the Cluster centers, is the number of clusters. Calculate the security strength score As the classification score after clustering:

[0205]

[0206] in, and The weighted parameters ensure that different features contribute reasonably to the final score. Based on the security strength score, the encryption operation speed, data throughput and operation delay of the CPU card security chip under 128-bit, 256-bit and 512-bit key lengths are recorded to construct an encryption performance data set. Set the encryption operation speed Calculated as:

[0207]

[0208] in, is the amount of data processed by encryption, Is the time required to complete encryption. Data Throughput Calculated as:

[0209]

[0210] in, It is the total time including encryption calculation, data transmission and storage operation. Calculated as:

[0211]

[0212] in, is the initialization time of the encryption task. In order to evaluate the overall performance of the chip, a comprehensive performance evaluation is performed on the encryption performance data set, and the performance evaluation score is calculated. The performance score is calculated by weighting encryption speed, data throughput, and computing latency:

[0213]

[0214] in, is a weight parameter to ensure a balance between computing performance and latency. and security strength score Perform weighted fusion to obtain the chip evaluation result matrix:

[0215]

[0216] in, and Respectively represent the key length Corresponding security scores and performance scores. The chip evaluation result matrix is ​​hierarchically mapped to generate a complete security chip comprehensive evaluation report. By setting the security classification threshold and performance grading thresholds , classifying chips into different levels:

[0217] ;

[0218] The power consumption characteristic curve of the chip is drawn through curve fitting, the security protection capability is analyzed, and a comprehensive evaluation report including power consumption characteristics, security protection analysis and performance test data is generated.

[0219] The low power consumption design method of the CPU card security chip in the embodiment of the present application is described above. The low power consumption design system 10 of the CPU card security chip in the embodiment of the present application is described below. Figure 2 In the embodiment of the present application, a low power consumption design system 10 of a CPU card security chip includes:

[0220] The sampling module 11 is used to sample the current waveform of the key storage area, encryption operation unit and identity authentication processor of the CPU card security chip, record the current data of the CPU card security chip when performing data encryption, identity authentication and security calculation, and obtain the characteristic parameter set of the security function module;

[0221] Establishing module 12, used to establish encryption operation power consumption model and identity authentication power consumption model according to the security function module characteristic parameter set, and obtain the power consumption characteristic matrix under different key lengths through piecewise linear fitting;

[0222] A classification module 13, used to classify the safety application tasks based on the power consumption characteristic matrix to obtain a multi-level safety task classification table;

[0223] The calculation module 14 is used to execute the differential power consumption attack protection strategy according to the multi-level security task classification table, and calculate the operating voltage and frequency configuration sequence of each security function module.

[0224] Through the cooperation of the above components, by establishing a refined power consumption characteristic model, combined with 16-bit high-precision sampling and multi-dimensional data analysis, the dynamic power consumption characteristics of each security function module of the CPU card security chip are accurately characterized, the security sensitivity analysis method is used to classify the tasks in multiple levels, and the optimal configuration sequence is generated through the dynamic power consumption balancing algorithm, which reduces the overall power consumption while ensuring the performance requirements of tasks of different security levels. The randomized clock modulation and voltage jitter technology are innovatively introduced, and the dynamic obfuscation of the power consumption waveform is realized by constructing a time-space interleaving matrix, which effectively enhances the chip's ability to resist differential power consumption analysis attacks. A systematic performance evaluation method is designed, and a comprehensive evaluation of the chip's security performance, computing efficiency and power consumption characteristics is achieved through a comprehensive analysis of multi-dimensional indicators. The working state switching strategy is optimized based on the Markov chain model and fuzzy control algorithm, which reduces the power consumption overhead during the state transition process and improves the energy utilization efficiency of the system. By combining piecewise linear fitting and dynamic balancing control, the optimal balance between power consumption and performance is achieved under different key lengths, significantly improving the overall performance of the CPU card security chip.

[0225] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0226] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable an electronic device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0227] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A low power consumption design method for a CPU card security chip, characterized in that: The method comprises: The key storage area, encryption operation unit and identity authentication processor of the CPU card security chip are sampled for current waveforms, and the current data of the CPU card security chip when performing data encryption, identity authentication and security calculation are recorded to obtain a characteristic parameter set of the security function module; An encryption operation power consumption model and an identity authentication power consumption model are established according to the characteristic parameter set of the security function module, and a power consumption characteristic matrix under different key lengths is obtained by piecewise linear fitting; Based on the power consumption characteristic matrix, the security application tasks are classified to obtain a multi-level security task classification table; specifically, the following steps are performed: based on the power consumption characteristic matrix, a task characteristic vector T=[t1, t2, t3, t4, t5] is constructed, where t1 is the usage rate of the key storage area, t2 is the complexity of the encryption operation, t3 is the identity authentication frequency, t4 is the data transmission volume, and t5 is the time constraint, to obtain a task characteristic vector set; security sensitivity calculation is performed on the task characteristic vector set to obtain a task security sensitivity score; the task security sensitivity score is segmented according to thresholds TH1 and TH2, and tasks with a score greater than TH1 are classified as high security level operations, and tasks with a score greater than TH1 are classified as high security level operations. Tasks between TH1 and TH2 are classified as medium security level operations, and tasks with a score less than TH2 are classified as low security level operations, to obtain an initial task classification result; for each type of task in the initial task classification result, a resource utilization vector R=[r1,r2,r3] is calculated, where r1 is the utilization of the key storage area, r2 is the utilization of the encryption operation unit, and r3 is the utilization of the identity authentication processor, to obtain a task resource demand matrix; based on the task resource demand matrix, a task scheduling priority analysis is performed to obtain a task priority sequence, and the task priority sequence is associated and mapped with the security level classification result to obtain a multi-level security task classification table; A differential power consumption attack protection strategy is executed according to the multi-level security task classification table, and the working voltage and frequency configuration sequence of each security function module is calculated; specifically, the method includes: executing the differential power consumption attack protection strategy on the multi-level security task classification table, calculating the power consumption leakage risk coefficient of each task, obtaining the task power consumption leakage risk matrix, and constructing a power consumption confusion function according to the task power consumption leakage risk matrix to obtain a power consumption confusion parameter set; inputting the power consumption confusion parameter set into a dynamic power consumption balancer, dynamically balancing the power consumption of each security function module, and obtaining a power consumption balance constraint condition; constructing a working state transition matrix based on the power consumption balance constraint condition, and using a Markov chain model to calculate the optimal state transition sequence to obtain a dynamic working state configuration table; performing a timing constraint analysis on the dynamic working state configuration table, generating a state switching timing diagram that meets the clock offset range and the voltage fluctuation range, and performing switching timing optimization to obtain a state switching control sequence; grouping and mapping the state switching control sequence to generate a working voltage and frequency configuration sequence of each security function module including voltage and frequency configuration parameters, switching timing requirements and safety constraints.

2. The low power consumption design method of the CPU card security chip according to claim 1, characterized in that: The key storage area, encryption operation unit and identity authentication processor of the CPU card security chip are sampled for current waveforms, and the current data of the chip when performing data encryption, identity authentication and security calculation is recorded to obtain a characteristic parameter set of the security function module, including: The key storage area, encryption operation unit and identity authentication processor of the CPU card security chip are sampled for current waveform to obtain original current sampling data; Performing repeated sampling tests on the original current sampling data to obtain multiple sets of current waveform data, and performing segmented acquisition on the multiple sets of current waveform data to obtain voltage-frequency combination data; The voltage-frequency combination data are classified and stored, and a peak power consumption data set during encryption operation, an average power consumption data set during identity authentication, and a working time data set during security calculation are respectively established to obtain a power consumption characteristic data set; The power consumption characteristic data set is grouped and fitted according to different key lengths to obtain a static power consumption and dynamic power consumption relationship matrix of each security function module, and a principal component analysis is performed on the static power consumption and dynamic power consumption relationship matrix to obtain a security function module characteristic parameter set.

3. The low power consumption design method of the CPU card security chip according to claim 1, characterized in that: The method of establishing an encryption operation power consumption model and an identity authentication power consumption model according to the characteristic parameter set of the security function module, and obtaining a power consumption characteristic matrix under different key lengths by piecewise linear fitting, includes: Performing data segmentation on the characteristic parameter set of the security function module to obtain multiple groups of key length power consumption data; Constructing an encryption operation power consumption model based on the multiple groups of key length power consumption data, and performing segmentation processing on the encryption operation power consumption model, performing linear fitting in each sub-interval after the segmentation processing, and obtaining a piecewise linear model coefficient group; Constructing an identity authentication power consumption model based on the piecewise linear model coefficient group, and performing matrix transformation on the encryption operation power consumption model and the identity authentication power consumption model under different key length conditions to obtain a power consumption feature mapping table; The power consumption characteristic mapping table is subjected to characteristic decomposition operation and orthogonal transformation to obtain a power consumption characteristic matrix under different key lengths.

4. The low power consumption design method of the CPU card security chip according to claim 1, characterized in that: The low power consumption design method of the CPU card security chip also includes: Decomposing the operating voltage and frequency configuration sequence into voltage control parameters and frequency control parameters, performing phase modulation on the clock signal using a digital phase-locked loop, and generating a clock modulation parameter set; Executing a pseudo-random sequence generation algorithm on the clock modulation parameter set, generating an m-sequence through a linear feedback shift register, performing spread spectrum modulation on the clock signal, and obtaining a randomized clock sequence; Performing voltage noise injection based on the randomized clock sequence to obtain a voltage jitter waveform, and inputting the voltage jitter waveform into a digital voltage regulator, dynamically adjusting the power supply voltage through pulse width modulation to obtain a voltage modulation sequence; Synchronously controlling the voltage modulation sequence and the randomized clock sequence to obtain a module modulation control word; The module modulation control word is grouped and encoded to generate an instruction packet including clock frequency, working voltage, modulation parameters and switching timing, and the instruction packet is parsed and executed through a state machine to obtain a control instruction stream that resists side channel attacks; A security performance test is performed on the control instruction flow that resists side-channel attacks, the encryption operation speed, authentication response time and power consumption balance are recorded, and a comprehensive evaluation report of the security chip is generated.

5. The low power consumption design method of the CPU card security chip according to claim 4, characterized in that: The security performance test is performed on the control instruction flow of the anti-side channel attack, the encryption operation speed, the authentication response time and the power consumption balance are recorded, and a comprehensive evaluation report of the security chip is generated, including: Based on the control instruction flow of the anti-side channel attack, the current waveform in the encryption operation process is collected to obtain the power consumption leakage assessment parameter; Performing security measurement and multi-dimensional cluster analysis based on the power consumption leakage assessment parameters to obtain a security strength score; Based on the security strength score, the encryption operation speed, data throughput and operation delay of the CPU card security chip under 128-bit, 256-bit and 512-bit key lengths are recorded respectively to obtain an encryption performance data set; Performing a comprehensive performance evaluation on the encryption performance data set to obtain a performance evaluation score, and performing a weighted fusion on the performance evaluation score and the security strength score to obtain a chip evaluation result matrix; The chip evaluation result matrix is ​​hierarchically mapped to generate a comprehensive security chip evaluation report including power consumption characteristic curves, security protection capability analysis and performance test data.

6. A low power consumption design system for a CPU card security chip, characterized in that: The low power consumption design method for a CPU card security chip according to any one of claims 1 to 5 is used, wherein the low power consumption design system for the CPU card security chip comprises: The sampling module is used to sample the current waveform of the key storage area, encryption operation unit and identity authentication processor of the CPU card security chip, record the current data of the CPU card security chip when performing data encryption, identity authentication and security calculation, and obtain the characteristic parameter set of the security function module; Establishing a module, used to establish an encryption operation power consumption model and an identity authentication power consumption model according to the characteristic parameter set of the security function module, and obtain a power consumption characteristic matrix under different key lengths through piecewise linear fitting; A classification module, used to classify the safety application tasks based on the power consumption characteristic matrix to obtain a multi-level safety task classification table; A calculation module is used to execute the differential power consumption attack protection strategy according to the multi-level security task classification table, and calculate the operating voltage and frequency configuration sequence of each security function module.

Images