Method for adjusting priority of submission queue, host, electronic equipment and computer equipment

Abstract

The invention provides a submission queue priority adjustment method, a host, electronic equipment and computer equipment, and relates to the technical field of data storage. The method comprises the steps that delay durations of a plurality of submission queues are obtained, the delay durations of the submission queues are determined by an average value of completion durations of a plurality of commands in the submission queues, and the completion durations are difference values between execution completion moments of the commands and moments when the commands are added into the submission queues; determining a delay score of the submission queue based on the delay duration of the submission queue; based on the delay scores of the submission queues, determining a target submission queue in the plurality of submission queues, and adjusting the priority of the target submission queue; and sending an instruction, wherein the instruction is used for notifying the priority adjustment result of the target submission queue. The longer the delay duration of the submission queue is, the longer the time for the command in the submission queue to wait to be executed is. Therefore, the priority of the submission queue is adjusted according to the delay score determined by the delay duration, so that the risk that the command cannot be executed for a long time is reduced.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of data storage, and in particular, relates to a submission queue priority adjustment method, a host, an electronic device, and a computer device. Background Art

[0002] Non-volatile memory express (NVMe) is a communication protocol and interface standard for connecting a host (such as a computer) with a non-volatile storage device (such as a solid-state drive). It aims to optimize the read and write performance of non-volatile storage devices and achieve higher data transfer rates and lower access latency. Summary of the invention

[0003] Embodiments of the present disclosure provide a submission queue priority adjustment method, a host, an electronic device, and a computer device, for reducing the risk that a command cannot be executed for a long time.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, a submission queue priority adjustment method is provided, the method comprising: obtaining delay durations of multiple submission queues, the delay duration of the submission queue being determined by an average of completion durations of multiple commands in the submission queue, the completion duration being the difference between a command execution completion time and a command joining time in the submission queue; determining a delay score of the submission queue based on the delay duration of the submission queue; determining a target submission queue from multiple submission queues based on the delay score of the submission queue, and adjusting the priority of the target submission queue; and sending instructions, the instructions being used to notify the target submission queue of a priority adjustment result.

[0006] The present disclosure provides a submission queue priority adjustment method, which calculates the delay score of the submission queue through the delay duration of multiple submission queues, and then determines the target submission queue whose priority needs to be adjusted among the multiple submission queues according to the delay score of the submission queue. Since the delay duration of the submission queue can reflect the time required for the execution of a single command in the submission queue to a certain extent; wherein, the longer the delay duration of the submission queue, the longer the command in the submission queue waits to be executed. Therefore, the delay score of the submission queue calculated by the delay duration of the submission queue can evaluate the urgency of each submission queue in the multiple submission queues, and then adjust the priority of the submission queue, and issue an instruction to notify the target submission queue of the priority adjustment result, so as to reduce the risk of commands not being executed for a long time due to unreasonable command allocation by the host.

[0007] In some embodiments, the priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; based on the delay score of the submission queue, a target submission queue is determined among multiple submission queues, and the priority of the target submission queue is adjusted, including: among multiple submission queues, the submission queue with the largest delay score is determined as the first target submission queue, and the priority of the first target submission queue is adjusted to the emergency priority; and / or, among multiple submission queues, the submission queue with the smallest delay score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority. The larger the delay score of the submission queue, the longer the commands in the submission queue wait to be executed, that is, the greater the risk that the commands in the submission queue cannot be executed for a long time. Therefore, by adjusting the priority of the first target submission queue with the largest delay score to the emergency priority, the commands in the first target submission queue are processed first; the priority of the second target submission queue with the smallest delay score is adjusted to the weighted priority, so as to avoid polling multiple submission queues with emergency priorities, so that the commands in the first target submission queue cannot be executed in time, thereby reducing the risk that the commands cannot be executed for a long time.

[0008] In some embodiments, based on the delay score of the submission queue, a target submission queue is determined among multiple submission queues, and the priority of the target submission queue is adjusted, including: determining the priority score of the submission queue based on the delay score of the submission queue and the number of commands in the submission queue; determining the target submission queue among multiple submission queues based on the priority score of the submission queue, and adjusting the priority of the target submission queue. For a submission queue with more commands, commands at the back of the submission queue may also have the risk of not being executed for a long time. Therefore, the priority score of the submission queue is determined by the number of commands in the submission queue and the delay score, and the target submission queue is determined by the priority score of the submission queue, which can reduce the risk of commands at the back being unable to be executed for a long time.

[0009] In some embodiments, the priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; based on the priority score of the submission queue, a target submission queue is determined among multiple submission queues, and the priority of the target submission queue is adjusted, including: among multiple submission queues, the submission queue with the largest priority score is determined as the first target submission queue, and the priority of the first target submission queue is adjusted to the emergency priority; and / or, among multiple submission queues, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority. In the present disclosure, the more commands in the submission queue, the higher the delay score of the submission queue, and the greater the priority score of the submission queue. Therefore, the priority of the first target submission queue with the largest priority score is adjusted to the emergency priority to give priority to the commands in the first target submission queue; the priority of the second target submission queue with the smallest priority score is adjusted to the weighted priority to avoid polling multiple submission queues with emergency priorities, so that the commands in the first target submission queue cannot be executed in time, thereby reducing the risk that the commands at the back cannot be executed for a long time.

[0010] In some embodiments, the method further includes: determining a target submission queue from among the plurality of submission queues based on the priority score of the submission queue and the delay score of the submission queue, and adjusting the priority of the target submission queue. The priority of the submission queue is adjusted based on the priority score of the submission queue and the delay score of the submission queue, so that the priority adjustment is more accurate to a certain extent.

[0011] In some embodiments, the priority of a submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; based on the priority score of the submission queue and the delay score of the submission queue, a target submission queue is determined among multiple submission queues, and the priority of the target submission queue is adjusted, including: among the submission queues whose delay scores are greater than a first threshold, the submission queue with the largest priority score is determined as the first target submission queue, and the priority of the first target submission queue is adjusted to the emergency priority; and / or, among the submission queues whose delay scores are less than a second threshold, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority; the second threshold is less than the first threshold. To a certain extent, it avoids the inaccurate priority adjustment caused by the large priority score due to the excessive number of commands in the submission queue.

[0012] In some embodiments, the priority score of a submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

[0013] In some embodiments, based on the delay duration of the submission queue, determining the delay score of the submission queue includes: calculating an average value μ of the delay durations of multiple submission queues; calculating a standard deviation σ of the delay durations of multiple submission queues; and normalizing the delay durations according to the mean value formula: Determines the latency score for the submission queue; where lat i is the delay time of the i-th submission queue, score i is the delay score of the ith submission queue. This normalizes the feature values ​​to the same dimension and eliminates the problem of unbalanced weights.

[0014] In a second aspect, a host is provided, including a host processor and an interface circuit for coupling a memory system, the host processor being configured to: obtain delay durations of multiple submission queues, the delay duration of the submission queue being determined by an average of completion durations of multiple commands in the submission queue, the completion duration being the difference between a command execution completion time and a command joining time in the submission queue; determine a delay score of the submission queue based on the delay duration of the submission queue; determine a target submission queue among multiple submission queues based on the delay score of the submission queue, and adjust a priority of the target submission queue; the interface circuit being configured to: send instructions, the instructions being used to notify the target submission queue of a priority adjustment result.

[0015] In some embodiments, the priority of a submission queue includes an emergency priority and a weighted priority, the emergency priority being higher than the weighted priority; the host processor determines a target submission queue among multiple submission queues based on the delay score of the submission queue, and adjusts the priority of the target submission queue, and is specifically configured as follows: among multiple submission queues, determining a submission queue with a largest delay score as a first target submission queue, and adjusting the priority of the first target submission queue to an emergency priority; and / or, among multiple submission queues, determining a submission queue with a smallest delay score as a second target submission queue, and adjusting the priority of the second target submission queue to a weighted priority.

[0016] In some embodiments, the host processor determines a target submission queue among multiple submission queues based on a latency score of the submission queue and adjusts a priority of the target submission queue, and is specifically configured to: determine a priority score of the submission queue based on the latency score of the submission queue and the number of commands in the submission queue; determine a target submission queue among multiple submission queues based on the priority score of the submission queue, and adjust the priority of the target submission queue.

[0017] In some embodiments, the priority of a submission queue includes an emergency priority and a weighted priority, the emergency priority being higher than the weighted priority; the host processor determines a target submission queue among multiple submission queues based on the priority score of the submission queue, and adjusts the priority of the target submission queue, and is specifically configured as follows: among multiple submission queues, determining a submission queue with the largest priority score as the first target submission queue, and adjusting the priority of the first target submission queue to the emergency priority; and / or, among multiple submission queues, determining a submission queue with the smallest priority score as the second target submission queue, and adjusting the priority of the second target submission queue to the weighted priority.

[0018] In some embodiments, the host processor is further configured to determine a target submission queue among the plurality of submission queues based on the priority scores of the submission queues and the latency scores of the submission queues, and adjust the priority of the target submission queue.

[0019] In some embodiments, the priority of a submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; the host processor determines a target submission queue from multiple submission queues based on the priority score of the submission queue and the delay score of the submission queue, and adjusts the priority of the target submission queue, and is specifically configured as follows: among the submission queues whose delay scores are greater than a first threshold, determining the submission queue with the largest priority score as the first target submission queue, and adjusting the priority of the first target submission queue to the emergency priority; and / or, among the submission queues whose delay scores are less than a second threshold, the second threshold is less than the first threshold, determining the submission queue with the smallest priority score as the second target submission queue, and adjusting the priority of the second target submission queue to the weighted priority.

[0020] In some embodiments, the priority score of a submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

[0021] In some embodiments, the host processor determines a delay score of a submission queue based on the delay duration of the submission queue; specifically configured to: calculate an average value μ of the delay durations of multiple submission queues; calculate a standard deviation σ of the delay durations of multiple submission queues; and according to a mean normalization formula: Determines the latency score for the submission queue; where lat i is the delay time of the i-th submission queue, score i is the delay fraction of the ith submission queue.

[0022] According to a third aspect, an electronic device is provided, comprising a host and a memory system, wherein the host comprises a first interface, the memory system comprises a second interface, and the host and the memory system are coupled via the first interface and the second interface, wherein: the first interface is configured to send a first instruction for notifying an adjustment result of a priority of a target submission queue in a plurality of submission queues; and the second interface is configured to receive the first instruction, and send a second instruction to the host based on the received first instruction.

[0023] In a fourth aspect, a computer device is provided, comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any one of the methods in the first aspect can be implemented.

[0024] In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0026] Figure 1 A schematic diagram of a polling arbitration mechanism provided by an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of a weighted polling arbitration mechanism with emergency priority provided in an embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure;

[0029] Figure 4 A schematic diagram of the structure of a NAND flash memory provided by an embodiment of the present disclosure;

[0030] Figure 5 A flowchart of a submission queue priority adjustment method provided in an embodiment of the present disclosure;

[0031] Figure 6 A schematic diagram of a specific process of S2 provided in an embodiment of the present disclosure;

[0032] Figure 7A schematic diagram of a specific process of S3 provided in an embodiment of the present disclosure;

[0033] Figure 8 Another specific flow chart of S2 provided in the embodiment of the present disclosure.

[0034] Figure numerals: 100, electronic device; 110, host; 111, host processor; 112, host memory; 113, bus; 114, first interface; 120, memory system; 121, storage controller; 122, memory; 123, second interface; 210, bare chip; 220, plane; 230, block; 240, page. DETAILED DESCRIPTION

[0035] The following will be combined Figure 1-Figure 8 , the technical solutions in some embodiments of the present disclosure are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0036] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0037] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0038] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0039] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0040] At present, the data transmission protocol specifications between the memory system and the host mainly include the advanced host controller interface (AHCI) and the non-volatile memory express (NVMe). Among them, AHCI is a single queue mode; that is, the host and the memory system exchange data through one queue. Mechanical hard disk drives (HDD) and early solid state drives (SSD) generally use the AHCI protocol.

[0041] Unlike the sequential read and write characteristics of HDD, SSD can read data from multiple different locations at the same time and has high concurrency. Therefore, the single queue mode of the AHCI protocol becomes a bottleneck that limits the concurrency of SSD. Compared with the AHCI protocol, the NVMe protocol supports multiple (up to 65536) queues, which can give full play to the parallel storage advantages of SSD and greatly improve the read and write performance of SSD. In the NVMe protocol, the host can place the management (admin) commands mainly used to manage the memory system in the management submission queue (ASQ), and place the NVM commands mainly responsible for data transmission in the submission queue (SQ). Exemplarily, the host may place a command into a submission queue, and then use a doorbell register to notify the memory system to take out the command from the submission queue; after the memory system completes execution of the command, it writes the execution result into a completion queue (CQ) corresponding to the submission queue, and triggers an interrupt to notify the host that the execution of the command has been completed; the host reviews the execution result on the completion queue, and then notifies the memory system that the execution result on the completion queue has been reviewed and the command execution is complete.

[0042] The memory system needs to determine the order of obtaining commands from the management submission queue and multiple submission queues according to certain rules. This rule is called a multi-queue arbitration mechanism. At present, the NVMe protocol mainly defines two arbitration mechanisms, one is round robin arbitration (RR) and the other is weighted round robin arbitration (WRR) with emergency priority.

[0043] Polling arbitration mechanism such as Figure 1 As shown, the arbitration mechanism polls the management submission queue and the multiple submission queues, takes out a certain number of commands from each submission queue in sequence and executes them, and the management submission queue and the multiple submission queues have the same priority.

[0044] Weighted round-robin arbitration mechanism with emergency priority Figure 2 As shown, exemplarily, the weighted polling arbitration mechanism with urgent priority defines three strict priorities. Among them, the three absolute priorities are management priority (admin class), urgent priority (urgent class) and weighted priority (WWR class), and the management priority is higher than the urgent priority and higher than the weighted priority. That is to say, the memory system always takes out and executes commands from the management submission queue first, and then takes out and executes commands from the submission queue with urgent priority, and finally takes out and executes commands from the submission queue with weighted priority. In some embodiments, the management submission queue always has the highest management priority, and the host only configures the absolute priority of the submission queue; exemplarily, the host can configure the absolute priority of the submission queue as urgent priority or weighted priority. The polling arbitration mechanism is used between management submission queues and between submission queues with the same absolute priority.

[0045] The weighted priority with the lowest absolute priority can include high priority, medium priority and low priority. The submission queues of these three priorities are arbitrated by weighted polling arbitration mechanism. The host can configure the weights of these three priorities, which represent the number of commands obtained from the submission queue each time.

[0046] In some embodiments, the polling arbitration mechanism reads the commands in each submission queue in turn without distinction of priority, and all submission queues are scheduled with the same probability. As a result, delay-sensitive critical services and non-critical services cannot be treated differently, resulting in critical services not being executed in a timely manner. Although weighted polling arbitration with emergency priority can ensure that commands in high-priority submission queues are fully scheduled, there is no fair agreement between priorities, and commands in low-priority (such as low-priority in weighted priority) submission queues may also wait for a long time to be executed, thereby affecting the execution and response of the commands. When the waiting time reaches a certain extent, the command may no longer have practical significance even if it is executed.

[0047] The embodiment of the present disclosure periodically calculates the delay time of the submission queue by the difference between the execution completion time of multiple commands in the submission queue and the time when the commands are added to the submission queue. The longer the delay time of the submission queue, the higher the risk that the commands in the submission queue cannot be executed for a long time, and the more likely it is to have downtime risks such as command timeout. Therefore, the present disclosure regards the submission queue with a relatively large delay time as a more urgent submission queue, and the host changes the priority of the submission queue and notifies the memory system to reduce the risk that the commands in the submission queue cannot be executed for a long time.

[0048] like Figure 3 As shown, an embodiment of the present disclosure provides an electronic device, and the electronic device 100 includes a host 110 and a memory system 120. The electronic device 100 can be a terminal device such as a mobile phone, a television, a display, a tablet computer, or a smart wearable device such as a smart watch, a smart bracelet, virtual reality (VR) glasses, or a communication device such as a server and a base station, or a control device such as a car computer. The embodiment of the present disclosure does not impose any special restrictions on the specific form of the electronic device 100.

[0049] Specifically, the host 110 may include a host processor 111, a host memory 112, a bus 113 and an interface circuit. The host processor 111, the interface circuit and the host memory 112 are coupled to each other through the bus 113. The interface circuit includes a first interface 114. The memory system 120 may be an NVMe SSD. The memory system 120 may include a storage controller 121, a memory 122 and a second interface 123. The host 110 and the memory system 120 are coupled through the first interface 114 and the second interface 123.

[0050] The host processor 111 or the storage controller 121 may be a chip, for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0051] The host memory 112 can be a volatile storage medium, for example, it can be a random access memory (RAM). RAM can include various forms: for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM), etc., which are not limited in the present disclosure.

[0052] The memory 122 can be a flash memory (such as NAND flash memory, NOR flash memory). The flash memory is free from the mechanical parts such as the magnetic head, disk shaft and motor of the traditional mechanical hard disk. There is no motor rotation process, no mechanical failure, and no fear of collision, impact and vibration. Therefore, compared with mechanical hard disks, flash memory has absolute advantages in performance, reliability, energy consumption, and portability, and is widely used in civil, automotive, industrial control, electricity, medical, aviation, navigation equipment and other fields. The present disclosure takes the memory 122 as NAND flash memory as an example, but it is not intended to be limited to this. At this time, the storage controller 121 can control the memory 122 through an open NAND flash interface (open Nand flash interface, ONFI) or a toggle interface. Figure 4The structure of a NAND flash memory is shown. The NAND flash memory includes a plurality of dies 210 (dies). Each of the dies 210 includes a plurality of planes 220 (planes). Each of the planes 220 includes a plurality of blocks 230 (blocks). Each of the blocks includes a plurality of pages 240 (pages).

[0053] Specifically, the host processor 111 in the host 110 may execute the submission queue priority adjustment method.

[0054] like Figure 5 As shown, the method includes steps S1 to S4, as follows:

[0055] S1. The delay time for the host to obtain multiple submission queues.

[0056] In other words, the host 110 obtains the delay time of each submission queue in the multiple submission queues. The host 110 can obtain the delay time of the multiple submission queues according to a preset time rule; for example, once every ten minutes. Figure 3 As shown, multiple submission queues and corresponding completion queues are created in a shared memory (e.g., host memory 112) between the host 110 and the memory system 120, and the doorbell register is located in the controller at the end of the memory system 120. The delay time of each submission queue is determined by the average completion time of multiple commands in the submission queue. As described above, the host 110 can add one or more prepared commands to the submission queue; then use the doorbell register to inform the memory system 120 to fetch the commands in the submission queue to the controller buffer; the memory system 120 can take out one or more commands to execute, regardless of whether the command execution succeeds or fails, the execution result of the command will always be written to the completion queue, and an interrupt will be triggered to notify the host 110 that the execution of the command has been completed; the host 110 reviews the execution result on the completion queue, and then notifies the memory system that the execution result on the completion queue has been reviewed and the command execution is completed. It can be understood that the completion time of a command is equal to the difference between the execution completion time of the command and the time when the command is added to the submission queue. In the embodiment of the present disclosure, the delay time of each submission queue can be equal to the average completion time of multiple commands in the submission queue.

[0057] S2. Based on the delay duration of the submission queue, the host determines a delay score of the submission queue.

[0058] In other words, the host 110 determines the delay score of each submission queue based on the delay duration of each submission queue. Figure 6 As shown, step S2 may include sub-steps S201 to S203, as follows:

[0059] S201. Calculate the average value μ of the delay durations of multiple submission queues.

[0060] In some embodiments, the average value μ of the delay durations of multiple submission queues can be expressed as: Calculated, where n is the number of submission queues, lat i is the delay duration of the i-th submission queue among the n submission queues; that is, the average completion duration of multiple commands in the submission queue.

[0061] S202: Calculate the standard deviation σ of the delay durations of multiple submission queues.

[0062] Specifically, the standard deviation σ of the delay time of multiple submission queues can be expressed as Calculated.

[0063] S203, according to the mean normalization (also called z-score normalization) formula: Determines the lateness score for a submission queue.

[0064] Among them, scor i e is the delay score of the ith submission queue among the n submission queues. It should be understood that the calculation of the delay score may also adopt other data normalization processing methods, including but not limited to linear normalization (also known as min-max normalization), which will not be described in detail in this disclosure.

[0065] S3. Based on the delay score of the submission queue, the host determines a target submission queue among the multiple submission queues and adjusts the priority of the target submission queue.

[0066] Specifically, the larger the delay score of a submission queue, the longer the commands in the submission queue will wait to be executed, which means that there is a greater risk that the commands in the submission queue cannot be executed for a long time. Therefore, among multiple submission queues, the submission queue with the largest delay score is determined as the first target submission queue, and the priority of the first target submission queue is adjusted to the emergency priority to give priority to the commands in the first target submission queue; and / or, among multiple submission queues, the submission queue with the smallest delay score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority; for example, the priority of the second target submission queue can be adjusted to a high priority among the weighted priorities to avoid polling multiple submission queues with emergency priorities, so that the commands in the first target submission queue cannot be executed in time. This reduces the risk that commands cannot be executed for a long time.

[0067] In some embodiments, for a submission queue with a lower priority and more commands, commands at the back of the submission queue also have the risk of not being executed for a long time. Figure 7 As shown, step S3 may include sub-steps S311 and S312, as follows:

[0068] S311. Based on the latency score of the submission queue and the number of commands in the submission queue, the host determines a priority score of the submission queue.

[0069] Specifically, the priority score of the i-th submission queue among n submission queues is priority i , by the latency score of the submission queue i The number of commands in the submission queue cmd_num i In the embodiment of the present disclosure, the priority score of the i-th submission queue among the n submission queues is determined by the product of i By the formula priority i =score i ×cmd_num i Calculated.

[0070] S312. Based on the priority scores of the submission queues, the host determines a target submission queue among the multiple submission queues, and adjusts the priority of the target submission queue.

[0071] Specifically, among multiple submission queues, the submission queue with the largest priority score is determined as the first target submission queue, and the priority of the first target submission queue is adjusted to the emergency priority; and / or, among multiple submission queues, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority.

[0072] For a submission queue with many commands, commands at the back of the submission queue may also be at risk of not being executed for a long time. Figure 6 The method shown, Figure 7 The provided method determines the priority score of a submission queue by the number of commands in the submission queue and the delay score, and determines and adjusts the priority of a target submission queue by the priority score of the submission queue, thereby reducing the risk that commands at the back of a submission queue with more commands cannot be executed for a long time.

[0073] like Figure 8 As shown, in some embodiments, step S3 may further include sub-steps S321 and 322; wherein, sub-step S321 is the same as sub-step S311, and will not be described in detail in this disclosure.

[0074] S322: Based on the priority score of the submission queue and the delay score of the submission queue, the host determines a target submission queue among the multiple submission queues, and adjusts the priority of the target submission queue.

[0075] Specifically, among the submission queues whose delay scores are greater than a first threshold, the submission queue with the largest priority score is determined as the first target submission queue, and the priority of the first target submission queue is adjusted to an emergency priority; and / or, among the submission queues whose delay scores are less than a second threshold, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to a weighted priority; the second threshold is less than the first threshold.

[0076] The first threshold and the second threshold can be set according to historical experience; for example, the delay score is greater than or equal to 3 (score i ≥3) and the highest priority score is adjusted to the emergency priority. Similarly, the latency score is less than or equal to -3 (score i ≤-3) and the lowest priority score has its priority adjusted to the weighted priority.

[0077] For a submission queue that has too many commands but a low latency score, the execution time required for a single command in the submission queue is shorter. Even if there are too many commands in the submission queue, the commands in the submission queue can be executed faster. However, due to the large number of commands in the submission queue, the priority score of the submission queue is large. If the priority of the submission queue is adjusted only by the priority score of the submission queue, the priority adjustment may be inaccurate. Therefore, compared with Figure 7 The method shown, Figure 8 The provided method adjusts the priority of a submission queue by comprehensively considering the priority score of the submission queue and the delay score of the submission queue. This can, to a certain extent, avoid inaccurate priority adjustment caused by a large priority score due to an excessive number of commands in the submission queue.

[0078] It should be understood that if the priority of the first target submission queue determined by the host 110 is the emergency priority, it can be said that the host 110 maintains the priority of the first target submission queue as the emergency priority. It can also be said that if the priority of the first target submission queue determined by the host 110 is the emergency priority, the host 110 does not adjust the priority of the first target submission queue. Similarly, if the priority of the second target submission queue determined by the host 110 is the weighted priority, it can be said that the host 110 maintains the priority of the second target submission queue as the weighted priority (for example, the priority of the second target submission queue is a high priority among the weighted priorities, and the host 110 maintains the priority of the second target submission queue as a high priority among the weighted priorities). It can also be said that if the priority of the second target submission queue determined by the host 110 is the emergency priority, the host 110 does not adjust the priority of the second target submission queue.

[0079] S4. The host sends a command to the memory system.

[0080] Specifically, the host processor 111 of the host 110 controls the first interface 114 to send a first instruction to the second interface 123 of the memory system 120, where the first instruction is used to notify the memory system 120 of the adjustment result of the priority of the target submission queue in the multiple submission queues. After receiving the first instruction through the second interface 123, the memory system 120 sends a second instruction to the first interface 114 of the host 110 through the second interface 123, where the second instruction is used to feedback to the host 110 that the memory system 120 has received the first instruction.

[0081] After the host 110 completes the adjustment of the priority of the submission queue, the memory system 120 obtains commands from multiple submission queues for execution according to the adjusted priority based on the weighted polling arbitration mechanism with emergency priority through the second interface 123. In addition, after the memory system 120 completes the execution of the command, it can also write the execution result of the command to the completion queue through the second interface 123 and notify the host 110 that the execution of the command has been completed. The memory system 120 also receives a notification through the second interface 123 that the execution result in the completion queue has been reviewed by the host 110.

[0082] The present disclosure also provides a computer-readable storage medium, which stores computer-executable instructions. After the computer-executable instructions are executed, each step in the above method embodiment can be implemented, such as executing Figure 5-Figure 8 The method shown.

[0083] The present disclosure provides a computer device, including a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the various steps in the above method embodiments can be implemented, such as executing Figure 5-Figure 8 The method shown.

[0084] The disclosed embodiments provide a submission queue priority adjustment method, host, electronic device, and computer device, which use the submission queue delay score calculated by the submission queue delay duration to adjust the submission queue priority, and issue an instruction to notify the target submission queue of the priority adjustment result. Since the submission queue delay duration can reflect the time required for the execution of a single command in the submission queue to a certain extent; therefore, adjusting the submission queue priority according to the submission queue delay score calculated by the submission queue delay duration can reduce the risk of commands not being executed for a long time due to unreasonable command allocation by the host.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and for the parts not described in detail in a certain embodiment, reference can be made to the corresponding processes in the aforementioned method embodiments, which will not be repeated here.

[0086] It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0087] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0088] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A submission queue priority adjustment method, characterized in that: include: Obtaining delay durations of multiple submission queues, where the delay duration of the submission queues is determined by an average of completion durations of multiple commands in the submission queues, where the completion duration is a difference between a time when the command is executed and a time when the command is added to the submission queue; Determining a delay score of the submission queue based on the delay duration of the submission queue; Determining a target submission queue among the plurality of submission queues based on the delay scores of the submission queues, and adjusting a priority of the target submission queue; Send an instruction, where the instruction is used to notify the target submission queue of a priority adjustment result.

2. The method according to claim 1, characterized in that The priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; determining a target submission queue from the plurality of submission queues based on the delay score of the submission queue, and adjusting the priority of the target submission queue, comprises: Among the multiple submission queues, determine the submission queue with the largest delay score as the first target submission queue, and adjust the priority of the first target submission queue to an emergency priority; and / or, Among the multiple submission queues, determine the submission queue with the smallest delay score as the second target submission queue, and adjust the priority of the second target submission queue to a weighted priority.

3. The method according to claim 1, characterized in that The step of determining a target submission queue among the plurality of submission queues based on the delay scores of the submission queues, and adjusting the priority of the target submission queue comprises: determining a priority score for the submission queue based on a latency score for the submission queue and a number of commands in the submission queue; Based on the priority scores of the submission queues, the target submission queue is determined among the plurality of submission queues, and the priority of the target submission queue is adjusted.

4. The method according to claim 3, characterized in that The priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; The determining the target submission queue among the plurality of submission queues based on the priority scores of the submission queues, and adjusting the priority of the target submission queue, comprises: Among the multiple submission queues, determine the submission queue with the largest priority score as the first target submission queue, and adjust the priority of the first target submission queue to an emergency priority; and / or, Among the multiple submission queues, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority.

5. The method according to claim 3, characterized in that: The method further comprises: The target submission queue is determined among the plurality of submission queues based on the priority score of the submission queue and the delay score of the submission queue, and the priority of the target submission queue is adjusted.

6. The method according to claim 5, characterized in that The priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; determining the target submission queue from the plurality of submission queues based on the priority score of the submission queue and the delay score of the submission queue, and adjusting the priority of the target submission queue, comprises: Among the submission queues whose delay scores are greater than a first threshold, determining the submission queue with the largest priority score as a first target submission queue, and adjusting the priority of the first target submission queue to an emergency priority; and / or, Among the submission queues whose delay scores are less than a second threshold, determining the submission queue with the smallest priority score as the second target submission queue, and adjusting the priority of the second target submission queue to a weighted priority; The second threshold is smaller than the first threshold.

7. The method according to claim 3, characterized in that The priority score of the submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

8. The method according to any one of claims 1 to 7, characterized in that: The step of determining a delay score of the submission queue based on the delay duration of the submission queue comprises: Calculate the average value μ of the delay durations of the plurality of submission queues; Calculate the standard deviation σ of the delay durations of the plurality of submission queues; According to the mean normalization formula: determining a latency score for the submission queue; Where i is the number of submission queues, lat i is the delay time of the i-th submission queue, score i is the delay score of the i-th submission queue.

9. A host, characterized in that: The invention comprises a host processor and an interface circuit for coupling to a memory system, wherein the host processor is configured to: Obtaining delay durations of multiple submission queues, where the delay duration of the submission queues is determined by an average of completion durations of multiple commands in the submission queues, where the completion duration is a difference between a time when the command is executed and a time when the command is added to the submission queue; Determining a delay score of the submission queue based on the delay duration of the submission queue; Determining a target submission queue among the plurality of submission queues based on the delay scores of the submission queues, and adjusting a priority of the target submission queue; The interface circuit is configured as: Send an instruction, where the instruction is used to notify the target submission queue of a priority adjustment result.

10. The host according to claim 9, characterized in that: The priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; the host processor determines a target submission queue from the plurality of submission queues based on the delay score of the submission queue, and adjusts the priority of the target submission queue, and is specifically configured as follows: Among the multiple submission queues, determine the submission queue with the largest delay score as the first target submission queue, and adjust the priority of the first target submission queue to an emergency priority; and / or, Among the multiple submission queues, determine the submission queue with the smallest delay score as the second target submission queue, and adjust the priority of the second target submission queue to a weighted priority.

11. The host according to claim 9, characterized in that: The host processor determines the target submission queue among the plurality of submission queues based on the delay scores of the submission queues, and adjusts the priority of the target submission queue, and is specifically configured as follows: determining a priority score for the submission queue based on a latency score for the submission queue and a number of commands in the submission queue; Based on the priority scores of the submission queues, the target submission queue is determined among the plurality of submission queues, and the priority of the target submission queue is adjusted.

12. The host according to claim 11, characterized in that: The priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; the host processor determines the target submission queue from the plurality of submission queues based on the priority score of the submission queue, and adjusts the priority of the target submission queue, and is specifically configured as follows: Among the multiple submission queues, determine the submission queue with the largest priority score as the first target submission queue, and adjust the priority of the first target submission queue to an emergency priority; and / or, Among the multiple submission queues, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to the weighted priority.

13. The host according to claim 9, characterized in that: The host processor is further configured to: The target submission queue is determined among the plurality of submission queues based on the priority score of the submission queue and the delay score of the submission queue, and the priority of the target submission queue is adjusted.

14. The host according to claim 13, characterized in that: The priority of the submission queue includes an emergency priority and a weighted priority, and the emergency priority is higher than the weighted priority; the host processor determines the target submission queue from the plurality of submission queues based on the priority score of the submission queue and the delay score of the submission queue, and adjusts the priority of the target submission queue, and is specifically configured as follows: Among the submission queues whose delay scores are greater than a first threshold, determining the submission queue with the largest priority score as a first target submission queue, and adjusting the priority of the first target submission queue to an emergency priority; and / or, Among the submission queues whose delay scores are less than a second threshold, where the second threshold is less than the first threshold, the submission queue with the smallest priority score is determined as the second target submission queue, and the priority of the second target submission queue is adjusted to a weighted priority.

15. The host according to claim 9, characterized in that: The priority score of the submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

16. The host according to any one of claims 9 to 15, characterized in that: The host processor determines a delay score of the submission queue based on the delay duration of the submission queue; and is specifically configured to: Calculate the average value μ of the delay durations of the plurality of submission queues; Calculate the standard deviation σ of the delay durations of the plurality of submission queues; According to the mean normalization formula: determining a latency score for the submission queue; Where i is the number of submission queues, lat i is the delay time of the i-th submission queue, score i is the delay score of the i-th submission queue.

17. An electronic device, characterized in that: The system comprises a host and a memory system, wherein the host comprises a first interface, the memory system comprises a second interface, the host and the memory system are coupled via the first interface and the second interface, wherein: The first interface is configured to send a first instruction for notifying the memory system of an adjustment result of a priority level of a target submission queue among the plurality of submission queues; The second interface is configured to receive the first instruction from the host, and send a second instruction for feeding back receipt of the first instruction to the host.

18. A computer device, characterized in that: The invention comprises a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, the method according to any one of claims 1 to 8 can be implemented.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method described in any one of claims 1 to 8 can be implemented.

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