Virtual interruption method, system and equipment and storage medium

Abstract

The invention relates to the field of virtual machines, and discloses a virtual interruption method, system and device and a storage medium, the method is applied to a virtual central processing unit of a virtual machine, and the method comprises the following steps: responding to an access pause instruction, sinking to a host mode, controlling a virtual machine monitor, and marking the current state of the virtual central processing unit as a sleep state; based on a preset interruption checking mode, judging whether virtual interruption exists or not; and in response to the existence of the virtual interrupt, controlling the virtual machine monitor to change the current state from the sleep state to the running state, switching from the host mode to the guest mode, and responding to the virtual interrupt. By means of the technical scheme, the effect of responding to the virtual interrupt in time is achieved, and the situation of virtual interrupt response errors caused by the hardware processing time sequence problem is avoided.

Description

Technical Field

[0001] The present invention relates to the field of virtual machines, and in particular to a virtual interrupt method, system, device and storage medium. Background Art

[0002] As the super resource manager of the central computing unit, the Hypervisor (virtual machine monitor) has control over all hardware resources, including interrupts. Interrupt virtualization is very important and has a great impact on system performance, power consumption, and stability. From the perspective of the Hypervisor, all interrupts received by the virtual machine are virtual interrupts. The traditional method is to rely on the Hypervisor to forward virtual interrupts, which greatly affects efficiency.

[0003] Currently, hardware-assisted virtualization can be achieved by adding dedicated hardware. However, if the virtual central processing unit executes a pause instruction and enters a low-power state, it may be unable to respond to virtual interrupts, or even cause the software system to freeze.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a virtual interrupt method, system, device and storage medium, which achieve the effect of timely responding to virtual interrupts and avoid virtual interrupt response errors caused by hardware processing timing problems.

[0006] An embodiment of the present invention provides a virtual interrupt method, which is applied to a virtual central processing unit of a virtual machine. The method includes:

[0007] In response to the access pause instruction, trapping out of the host mode, and controlling the virtual machine monitor to mark the current state of the virtual central processor as a sleep state;

[0008] Based on the preset interruption checking method, determine whether there is a virtual interruption;

[0009] In response to the existence of the virtual interrupt, the virtual machine monitor is controlled to change the current state from the sleep state to the running state, and the host mode is switched to the guest mode to respond to the virtual interrupt.

[0010] An embodiment of the present invention provides a virtual interrupt system, the system comprising: at least one virtual machine, a virtual machine monitor and a hardware device; the hardware device comprises at least two physical central processing units; each virtual machine comprises at least two virtual central processing units;

[0011] Wherein, each of the virtual central processing units in each of the virtual machines is connected to the corresponding physical central processing unit via the virtual machine monitor;

[0012] Each virtual central processing unit of the virtual machine is used to execute the steps of the virtual interrupt method described in any embodiment.

[0013] An embodiment of the present invention provides a computer device, the computer device comprising:

[0014] Processor and memory;

[0015] The processor is used to execute the steps of the virtual interrupt method described in any embodiment by calling the program or instruction stored in the memory.

[0016] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program or instruction, wherein the program or instruction enables a computer to execute the steps of the virtual interruption method described in any embodiment.

[0017] The embodiments of the present invention have the following technical effects:

[0018] In response to the access pause instruction, the virtual central processing unit falls out of the host mode, controls the virtual machine monitor, marks the current state of the virtual central processing unit as the sleep state, and judges whether there is a virtual interrupt based on the preset interrupt check method, so as to perform a certain delay processing on the judgment of whether there is a virtual interrupt through the preset interrupt check method, so as to provide time for the data in the cache to be written into the memory, and then, in response to the existence of the virtual interrupt, controls the virtual machine monitor to change the current state from the sleep state to the running state, switches from the host mode to the guest mode, and responds to the virtual interrupt, thereby achieving the effect of timely responding to the virtual interrupt and avoiding the virtual interrupt response error caused by the hardware processing timing problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a flow chart of a virtual interrupt method provided by an embodiment of the present invention;

[0021] Figure 2 is a flow chart of another virtual interrupt method provided by an embodiment of the present invention;

[0022] Figure 3is a structural diagram of a virtual interrupt system provided by an embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram of interaction between two virtual central processors in a virtual interrupt system provided by an embodiment of the present invention;

[0024] Figure 5 It is a structural schematic diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0026] The virtual interrupt method provided by the embodiment of the present invention is mainly applicable to the situation where the virtual interrupt is effectively processed when the virtual central processing unit responds to the pause instruction. The virtual interrupt method provided by the embodiment of the present invention can be executed by a virtual interrupt system or a computer device.

[0027] Figure 1 is a flow chart of a virtual interrupt method provided by an embodiment of the present invention. Figure 1 , the virtual interrupt method specifically includes:

[0028] S110 , in response to the access pause instruction, trapping out of the host mode, and controlling the virtual machine monitor to mark the current state of the virtual central processor as a sleep state.

[0029] Among them, the pause instruction is the HLT (Halt) instruction, which is used to pause the CPU (Central Processing Unit) and put it into a low-power state. The host mode can be understood as the Host mode. The current state is information used to describe whether the virtual machine's central processor is running, and can include the Sleep state and the Running state. The Sleep state is a low-power state and an energy-saving mode that effectively reduces its power consumption when it is not active or does not require high performance.

[0030] Specifically, if the virtual central processing unit receives a pause instruction, it can access the pause instruction, indicating that the current virtual central processing unit can enter a sleep state. Therefore, the virtual central processing unit is controlled to exit the host mode, and the current state of the virtual central processing unit is marked as a sleep state through the virtual machine monitor, so as to ensure the low power consumption mode of the virtual central processing unit.

[0031] S120: Determine whether a virtual interrupt exists based on a preset interrupt checking method.

[0032] Among them, the preset interrupt check method is an interrupt check method set to avoid hardware timing problems that lead to the inability to respond to virtual interrupts. It can effectively provide a time interval to provide time for the data in the cache to be written to the memory to trigger the virtual interrupt. The preset interrupt check method includes waiting interrupt check and polling interrupt check. Virtual interrupt is an interrupt method in a virtualized environment. It is understandable that in a virtualized environment, a physical CPU can be used by different virtual CPUs. Therefore, when the conditions for issuing a virtual interrupt are met (for example: data in the physical CPU changes, etc.), it is necessary to inject a virtual interrupt into each virtual CPU.

[0033] Specifically, a preset interrupt check mode can be set for the virtual CPU. After controlling the virtual machine monitor and marking the current state of the virtual CPU as the sleep state, it is necessary to confirm whether there is a virtual interrupt that affects its entry into the sleep state. Therefore, according to the preset interrupt check mode, it is determined whether there is a virtual interrupt, so as to determine whether to wake up the virtual CPU again or give up the occupied physical CPU to other virtual CPUs.

[0034] Based on the above example, if the preset interrupt check mode is to wait for interrupt check, the following method can be used to determine whether there is a virtual interrupt based on the preset interrupt check mode:

[0035] Obtain the memory flushing time corresponding to the virtual CPU, and determine the waiting time according to the memory flushing time;

[0036] Get the current time, and determine whether the reference time between the current time and the time when the pause instruction is received is greater than or equal to the waiting time;

[0037] If so, determine whether there is a virtual interrupt;

[0038] If not, return to the step of obtaining the current time until the reference duration is greater than or equal to the waiting duration.

[0039] Among them, the waiting interrupt check can be understood as setting a waiting time to provide time for the data in the cache to be written into the memory of the physical CPU to trigger the virtual interrupt after marking the current state of the virtual CPU as the sleep state. The memory write time is the time it takes for the data in the cache to be written to the memory of the corresponding physical CPU, which can be understood as the time it takes to write data per unit length. The waiting time is the time it takes to wait and determine whether there is a virtual interrupt based on the memory write time. It can be understood that the waiting time is greater than or equal to the memory write time. The receiving time is the time when the virtual CPU receives the pause instruction. The reference time is the time between the receiving time and the current time. It can be understood that the reference time can change with the passage of the current time.

[0040] Specifically, since the time for writing unit length data (such as a row of data, etc.) from the cache to the memory of the physical CPU is fixed, the memory flushing duration corresponding to the virtual CPU can be obtained. The memory flushing duration can be determined as the waiting duration, or a preset duration can be added on the basis of the memory flushing duration. The preset duration can be a preset hour length, in order to make the waiting duration slightly greater than the memory flushing duration. Get the current moment, calculate the reference duration between the current moment and the moment of receiving the pause instruction, and then determine whether the reference duration is greater than or equal to the waiting duration. If so, it means that after marking the current state of the virtual CPU as the sleep state, it has waited for a long enough time, so it can continue to determine whether there is a virtual interrupt. If not, it means that it has not waited for a long enough time and needs to continue waiting. Therefore, return to the step of obtaining the current moment, the current moment can be updated, and the reference duration can be recalculated until the reference duration is greater than or equal to the waiting duration.

[0041] Based on the above example, if the preset interrupt check mode is polling interrupt check, the following method can be used to determine whether a virtual interrupt exists based on the preset interrupt check mode:

[0042] Determine whether there is a virtual interrupt;

[0043] In response to the existence of the virtual interrupt, triggering the step of executing and controlling the virtual machine monitor to change the current state from the sleep state to the running state;

[0044] In response to the absence of the virtual interrupt, releasing the occupation from the first physical central processor;

[0045] In response to the disconnection time length of the first physical central processor being disconnected reaching a preset period and / or receiving a wake-up instruction, it is determined whether a virtual interrupt exists.

[0046] Among them, the virtual machine monitor (Hypervisor) can be used to establish and execute the software, firmware or hardware of the virtual machine. The running state is a state in which the virtual central processor can run normally, which is relative to the sleep state. The first physical central processor is the physical central processor currently occupied by the virtual central processor. The disconnection duration is the duration determined by starting the timing from the release of the occupation between the virtual central processor and the first physical central processor. The preset period is a pre-set period for periodically detecting virtual interrupts. The wake-up instruction is an instruction sent to the virtual central processor to wake up the virtual central processor from the sleep state to update it to the running state.

[0047] Specifically, a first judgment is made to determine whether a virtual interrupt exists. In response to the existence of a virtual interrupt, it means that a virtual interrupt already exists and it is necessary to exit the sleep state. Therefore, the step of executing and controlling the virtual machine monitor to change the current state from the sleep state to the running state is triggered. If there is no virtual interrupt, the right to use the first physical central processor can be given up and switched to other threads to run. Therefore, the first physical central processor can be released from occupation. After the first physical central processor is released from occupation, the disconnection time of the first physical central processor is timed, and the virtual central processor can receive a wake-up instruction. When at least one of the disconnection time reaches a preset period and a wake-up instruction is received, it means that a second judgment is required, that is, to determine whether a virtual interrupt exists again, so as to provide a certain time between the second judgment and the first judgment, so as to provide time for the data in the cache to be written into the memory of the physical central processor and trigger the virtual interrupt.

[0048] S130 . In response to the existence of a virtual interrupt, control the virtual machine monitor to change the current state from a sleep state to a running state, switch from a host mode to a guest mode, and respond to the virtual interrupt.

[0049] Among them, the guest mode can be understood as the Guest mode.

[0050] Specifically, in the presence of a virtual interrupt, the sleep state cannot be maintained. Therefore, in the host mode, the virtual machine monitor can be controlled to change the current state from the sleep state to the running state, and then switch from the host mode to the guest mode to respond to the virtual interrupt.

[0051] Based on the above example, after determining whether there is a virtual interrupt based on the preset interrupt check method, there is also a case where the determination result is that there is no virtual interrupt. In this case, the following method can be used to handle the situation:

[0052] In response to the absence of the virtual interrupt, de-engaging the first physical CPU;

[0053] In response to receiving the wake-up instruction, a second physical central processor is determined, and a connection with the second physical central processor is established to occupy the second physical central processor.

[0054] The virtual CPU performs virtual machine operations based on the physical CPU, that is, it performs various operations of the virtual machine by occupying the resources of the physical CPU. The second physical CPU is a physical CPU reallocated to the virtual CPU after the virtual CPU and the first physical CPU are released from occupation. The second physical CPU may be the same as or different from the first physical CPU. The first physical CPU and the second physical CPU are both physical CPUs.

[0055] Specifically, if there is no virtual interrupt, the first physical CPU that is currently occupied needs to be released, thereby releasing the occupation of the first physical CPU. After releasing the occupation of the first physical CPU, the virtual CPU is in a sleep state and can be awakened by a wake-up instruction. Upon receiving the wake-up instruction, the second physical CPU allocated to the virtual CPU is determined, and a connection is established with the second physical CPU to occupy resources in the second physical CPU and execute virtual machine operations.

[0056] The present invention has the following technical effects: the virtual central processing unit responds to the access pause instruction, falls out of the host mode, and controls the virtual machine monitor to mark the current state of the virtual central processing unit as the sleep state, and judges whether there is a virtual interrupt based on the preset interrupt check method, and performs a certain delay processing on the judgment of whether there is a virtual interrupt through the preset interrupt check method to provide time for writing data in the cache into the memory, and then, in response to the existence of the virtual interrupt, controls the virtual machine monitor to change the current state from the sleep state to the running state, switches from the host mode to the guest mode, and responds to the virtual interrupt, thereby achieving the effect of timely responding to the virtual interrupt and avoiding the situation of virtual interrupt response errors caused by hardware processing timing problems.

[0057] The above embodiment describes the way in which the virtual CPU responds to the virtual interrupt. In this embodiment, further description may be given on the way in which the virtual interrupt is injected into the target CPU. Figure 2 FIG. 1 is a flowchart of another virtual interrupt method provided by an embodiment of the present invention. The explanations of terms that are the same as or corresponding to the above-mentioned embodiments are not repeated here. Figure 2 As shown, the method may specifically include the following steps:

[0058] S210 , in response to the access pause instruction, trapping out of the host mode, and controlling the virtual machine monitor to mark the current state of the virtual central processor as a sleep state.

[0059] S220: Determine whether a virtual interrupt exists based on a preset interrupt checking method.

[0060] S230 . In response to the existence of the virtual interrupt, control the virtual machine monitor to change the current state from the sleep state to the running state, switch from the host mode to the guest mode, and respond to the virtual interrupt.

[0061] S240: When the condition for issuing a virtual interrupt is met, determine the target CPU corresponding to the virtual CPU, and issue a first interrupt setting notification to the advanced interrupt controller corresponding to the virtual CPU to set the interrupt flag of each target CPU.

[0062] Among them, the virtual interrupt condition is the condition for issuing a virtual interrupt, such as writing data to the memory through the cache, modifying and deleting data in the physical memory, etc. The target central processor is the central processor in other virtual machines that is different from the virtual central processor. The target central processor and the virtual central processor belong to the same virtual machine or different virtual machines. The Advanced Virtual Interrupt Controller (AVIC) is a controller for managing interrupts. It can efficiently process multiple interrupt requests, prioritize and manage different interrupt sources, so as to quickly respond to and process interrupts generated by various external events and internal operations. The first interrupt setting notification is a notification of the interrupt flag setting through the advanced interrupt controller. The interrupt flag is a binary bit used to indicate the state of the interrupt event.

[0063] Specifically, various active or passive virtual machine operations of the virtual central processor are analyzed to determine whether the conditions for issuing a virtual interrupt are met. If so, the target central processor corresponding to the virtual central processor is determined, that is, it is determined which central processors in which virtual machines need to issue interrupts. Furthermore, a first interrupt setting notification is issued to the advanced interrupt controller corresponding to the virtual central processor, and the advanced interrupt controller can set the interrupt flag bit of each target central processor upon receiving the first interrupt setting notification.

[0064] S250: Determine the current state of each target central processing unit from the advanced interrupt controller.

[0065] Specifically, a data table for recording the current status of each CPU of each virtual machine is stored in the memory. Therefore, the advanced interrupt controller can obtain the current status of each target CPU by querying the data table.

[0066] S260 : For each target CPU, inject a target interrupt into the target CPU according to the current state and the interrupt flag of the target CPU.

[0067] The target interrupt is a virtual interrupt injected by the virtual CPU into the target CPU.

[0068] Specifically, for each target CPU, a corresponding target interrupt can be injected respectively. The interrupt injection mode can be determined according to the current state of the target CPU, and the interrupt injection mode is triggered in combination with the interrupt flag of the target CPU to inject the target interrupt into the target CPU.

[0069] Based on the above example, if the current state is the running state, the target interrupt can be injected into the target CPU according to the current state and the interrupt flag of the target CPU in the following way:

[0070] In response to the current state being the running state, based on the interrupt flag bit of the target central processor, a target interrupt is injected into the target central processor through a hardware method.

[0071] Among them, the hardware method is a method of interrupt injection based on an advanced interrupt controller.

[0072] Specifically, if the current state is the running state, the hardware method can be used. The advanced interrupt controller can use the hardware to automatically complete the injection and notification of the target interrupt based on the interrupt flag of the target CPU, that is, the virtual IPI (Inter-Processor Interrupt) injection is completed. Furthermore, the interrupt flag is updated when the target interrupt processing is completed.

[0073] Based on the above example, if the current state is the sleep state, the target interrupt can be injected into the target CPU by means of redundant interrupt setting. Specifically, the target interrupt can be injected into the target CPU according to the current state and the interrupt flag of the target CPU by the following method:

[0074] In response to the current state being a dormant state, injecting a first target interrupt into the target central processor through hardware based on an interrupt flag bit of the target central processor;

[0075] Trapping out of the host mode, and sending a second interrupt setting notification to the virtual machine monitor to set the interrupt flag bit of each target central processor;

[0076] Based on the interrupt flag of the target central processor, a second target interrupt is injected into the target central processor through software, and a wake-up instruction is sent to the target central processor.

[0077] The first target interrupt is a virtual interrupt injected into the target CPU based on hardware. The second target interrupt is a virtual interrupt injected into the target CPU based on software, i.e., a virtual machine monitor. The second interrupt setting notification is a notification of interrupt flag setting through a virtual machine monitor. The software method is a method of interrupt injection based on a virtual machine monitor.

[0078] Specifically, since the target CPU is in a sleep state, it is first necessary to inject the first target interrupt through hardware, specifically, the advanced interrupt controller uses hardware to automatically complete the injection and notification of the first target interrupt based on the interrupt flag of the target CPU. In addition, in order to ensure the effectiveness of interrupt injection in the sleep state, the virtual CPU needs to fall out of the host mode for processing. Then, a second interrupt setting notification is sent to the virtual machine monitor, and the virtual machine monitor can set the interrupt flag of each target CPU when receiving the second interrupt setting notification. In addition, the redundancy of using software to inject the second target interrupt is determined, specifically, the injection and notification of the second target interrupt in the target CPU are completed by the virtual machine monitor based on the interrupt flag of the target CPU. In addition, a wake-up instruction is sent to the target CPU to wake up the thread of the target CPU in the sleep state.

[0079] It is understandable that there is no chronological order between S210 - S230 and S240 - S260 . The above example is only one possible case. There may also be other orders, which will not be elaborated here.

[0080] The present invention has the following technical effects: when a virtual central processor meets the conditions for issuing a virtual interrupt, the virtual central processor determines the target central processor corresponding to the virtual central processor, issues a first interrupt setting notification to the advanced interrupt controller corresponding to the virtual central processor, so as to set the interrupt flag of each target central processor, and then determines the current state of each target central processor from the advanced interrupt controller, and for each target central processor, injects a target interrupt into the target central processor according to the current state and the interrupt flag of the target central processor, so as to inject the target interrupt using different interrupt injection methods according to different current states, thereby realizing the injection of interrupts into each target central processor, and ensuring the effectiveness of interrupt injection in combination with different current states.

[0081] Figure 3 Schematic diagram of a virtual interrupt system provided by an embodiment of the present invention. Figure 3 As shown, the virtual interrupt system includes: at least one virtual machine 310 , a virtual machine monitor 320 and a hardware device 330 ; the hardware device 330 includes at least two physical central processors 331 ; and each virtual machine 310 includes at least two virtual central processors 311 .

[0082] Each virtual CPU 311 in each virtual machine 310 is connected to the corresponding physical CPU 331 via the virtual machine monitor 320;

[0083] Each virtual central processor 311 of the virtual machine 310 is used to execute the steps of the virtual interrupt method provided by any embodiment of the present invention.

[0084] The number of virtual machines 310 (VMs) includes but is not limited to: Figure 3 As shown in 2, the maximum number of virtual central processors 311 (Virtual CPU, VCPU) that can be configured for each virtual machine 310 is the number of physical central processors 331 (Physical CPU, PCPU). Each virtual central processor 311 corresponds to its own VLAPIC (Virtual Local Advanced Programmable Interrupt Controller), and multiple VLAPICs can share the same AVIC. The hardware device also includes devices such as DDR (Double Data Rate SDRAM, double rate synchronous dynamic random access memory), which will not be repeated here.

[0085] Figure 4 1 is a schematic diagram of the interaction between two virtual central processors in a virtual interrupt system provided by an embodiment of the present invention. In particular, two different virtual central processors VCPU0 and VCPU1 are used as examples for explanation. VCPU0 and VCPU1 run on different PCPUs at the same time, and the order of occurrence of each stage between VCPU0 and VCPU1 is uncertain. Figure 4 As shown, the interaction between the two virtual CPUs is as follows:

[0086] VCPU0 and VCPU1 have the same S0 stage and S1 stage:

[0087] In the S0 phase, the VCPU thread is scheduled to run on the corresponding PCPU.

[0088] In the S1 stage, the system switches to the Guest mode.

[0089] The subsequent stages of VCPU1 are as follows:

[0090] In the S2 phase, VCPU1 needs to send an IPI interrupt to VCPU0 and set the interrupt flag of VCPU0 through the AVIC hardware.

[0091] In the S3 stage, the running flag (current state) of VCPU0 is detected through AVIC hardware, and the next action is performed according to the running flag. If VCPU0 is in the Running state, the S7 and S8 stages of VCPU1 are executed; if VCPU0 is in the Sleep state, the S7, S8, S4, S5 and S6 stages of VCPU1 are executed.

[0092] In the S7 stage, interrupt injection and notification are automatically completed through AVIC using hardware.

[0093] In stage S8, it is determined that the injection of the virtual IPI interrupt (target interrupt or first target interrupt) is completed.

[0094] In the S4 stage, since VCPU0 is in the Sleep state, VCPU1 needs to fall out of the Host mode for processing.

[0095] In the S5 stage, the interrupt flag of VCPU0 is set through the virtual machine monitor, and the injection and notification of the interrupt (second target interrupt) are completed through software.

[0096] In the S6 stage, the VCPU0 thread in the sleeping state is awakened.

[0097] The subsequent stages of VCPU0 are as follows:

[0098] In the S2 stage, VCPU0 needs to enter a low power state (sleep state), and due to accessing the HLT instruction, it falls out of the Host mode for processing.

[0099] In the S3 stage, VCPU0 is marked as being in the Sleep state.

[0100] S4 stage, delayed waiting time.

[0101] In the S5 stage, it is checked whether VCPU0 has a suspended virtual interrupt. If so, the S6 stage of VCPU0 is executed; if not, the S7 stage of VCPU0 is executed.

[0102] In the S6 stage, the state of VCPU0 is marked as Running, and it re-enters the Guest mode to run and respond to virtual interrupts.

[0103] In the S7 stage, VCPU0 actively gives up the corresponding PCPU usage rights and switches to other threads to run, and VCPU0 waits to be awakened.

[0104] Understandably, Figure 4 The dotted line part in is the interaction part between the two virtual CPUs.

[0105] In the above scheme, in the S4 phase of VCPU0, any equivalent operation that can generate a corresponding delay can be considered as an alternative.

[0106] In the above solution, in the S7 stage of VCPU0, the S5 stage can be combined to be modified into a polling operation (polling interrupt check).

[0107] The present invention has the following technical effects: the above method can solve the problem of virtual interrupt freezing caused by hardware timing BUG (error) at the lowest cost, and the BUG cannot recover by itself. The above method only needs to modify the processing flow, and no hardware changes are required. At the same time, the above method complies with the rules of virtualization, is completely imperceptible to the virtual machine, and does not require any modification to the source code of the virtual machine. Moreover, hardware-assisted acceleration is still available, with almost no loss in performance, successfully avoiding the freezing problem caused by hardware timing BUG.

[0108] Figure 5 Schematic diagram of the structure of a computer device provided by an embodiment of the present invention. Figure 5 As shown, computer device 400 includes one or more processors 401 and memory 402 .

[0109] The processor 401 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device 400 to perform desired functions.

[0110] The memory 402 may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 401 may run the program instructions to implement the virtual interrupt method of any embodiment of the present invention described above and / or other desired functions. Various contents such as initial external parameters, thresholds, etc. may also be stored in the computer-readable storage medium.

[0111] In one example, the computer device 400 may further include: an input device 403 and an output device 404, which are interconnected via a bus system and / or other forms of connection mechanisms (not shown). The input device 403 may include, for example, a keyboard, a mouse, etc. The output device 404 may output various information to the outside, including early warning information, braking force, etc. The output device 404 may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.

[0112] Of course, to simplify, Figure 5 Only some of the components related to the present invention in the computer device 400 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application conditions, the computer device 400 may also include any other appropriate components.

[0113] In addition to the above methods and devices, an embodiment of the present invention may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the virtual interrupt method provided by any embodiment of the present invention.

[0114] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present invention, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0115] In addition, an embodiment of the present invention may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the virtual interrupt method provided by any embodiment of the present invention.

[0116] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0117] It should be noted that the terms used in the present invention are only for describing specific embodiments, rather than limiting the scope of the present application. As shown in the present specification, unless the context clearly indicates an exception, the words "one", "a", "a kind of" and / or "the" do not specifically refer to the singular, but may also include the plural. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method or device including the elements.

[0118] It should also be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A virtual interrupt method, characterized in that: Virtual CPUs for virtual machines, including: In response to the access pause instruction, trapping out of the host mode, and controlling the virtual machine monitor to mark the current state of the virtual central processor as a sleep state; Based on the preset interruption checking method, determine whether there is a virtual interruption; In response to the existence of the virtual interrupt, the virtual machine monitor is controlled to change the current state from the sleep state to the running state, and the host mode is switched to the guest mode to respond to the virtual interrupt.

2. The method according to claim 1, characterized in that: The preset interruption check mode is waiting for interruption check, and judging whether there is a virtual interruption based on the preset interruption check mode includes: Obtaining a memory flushing duration corresponding to the virtual central processing unit, and determining a waiting duration according to the memory flushing duration; Obtaining the current time, and determining whether a reference time between the current time and the time when the pause instruction is received is greater than or equal to the waiting time; If so, determine whether there is a virtual interrupt; If not, return to the step of obtaining the current time until the reference duration is greater than or equal to the waiting duration.

3. The method according to claim 1, characterized in that The preset interruption checking method is a polling interruption checking method, and judging whether a virtual interruption exists based on the preset interruption checking method includes: Determine whether there is a virtual interrupt; In response to the existence of a virtual interrupt, triggering the step of controlling the virtual machine monitor to change the current state from a sleep state to a running state; In response to the absence of the virtual interrupt, releasing the occupation from the first physical central processor; In response to the disconnection time length of the first physical central processor being disconnected reaching a preset period and / or receiving a wake-up instruction, it is determined whether a virtual interrupt exists.

4. The method according to claim 1, characterized in that: After determining whether there is a virtual interrupt based on the preset interrupt checking method, the method further includes: In response to the virtual interrupt not existing, releasing the first physical CPU; In response to receiving the wake-up instruction, determining a second physical central processor, and establishing a connection with the second physical central processor to occupy the second physical central processor; The virtual central processor performs virtual machine operations based on the physical central processor; the first physical central processor and the second physical central processor both belong to the physical central processor.

5. The method according to claim 1, characterized in that Also includes: When a condition for issuing a virtual interrupt is met, determining a target central processor corresponding to the virtual central processor, and issuing a first interrupt setting notification to an advanced interrupt controller corresponding to the virtual central processor to set an interrupt flag bit of each target central processor; wherein the target central processor and the virtual central processor belong to the same virtual machine or different virtual machines; Determining the current state of each of the target central processing units from the advanced interrupt controller; For each target CPU, a target interrupt is injected into the target CPU according to the current state and the interrupt flag of the target CPU.

6. The method according to claim 5, characterized in that The injecting a target interrupt into the target central processor according to the current state and the interrupt flag of the target central processor comprises: In response to the current state being the running state, a target interrupt is injected into the target central processor through hardware based on an interrupt flag of the target central processor.

7. The method according to claim 5, characterized in that The injecting a target interrupt into the target central processor according to the current state and the interrupt flag of the target central processor comprises: In response to the current state being a dormant state, injecting a first target interrupt into the target central processor through hardware based on an interrupt flag of the target central processor; Trapping out of the host mode, and sending a second interrupt setting notification to the virtual machine monitor to set an interrupt flag bit of each of the target central processors; Based on the interrupt flag bit of the target central processor, a second target interrupt is injected into the target central processor by software, and a wake-up instruction is sent to the target central processor.

8. A virtual interrupt system, characterized in that: include: At least one virtual machine, a virtual machine monitor and a hardware device; the hardware device includes at least two physical central processing units; each virtual machine includes at least two virtual central processing units; Wherein, each of the virtual central processing units in each of the virtual machines is connected to the corresponding physical central processing unit via the virtual machine monitor; Each virtual central processing unit of the virtual machine is used to execute the steps of the virtual interrupt method according to any one of claims 1 to 7.

9. A computer device, characterized in that: The computer device comprises: Processor and memory; The processor is used to execute the steps of the virtual interrupt method according to any one of claims 1 to 7 by calling the program or instruction stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a program or an instruction, and the program or the instruction enables a computer to execute the steps of the virtual interruption method according to any one of claims 1 to 7.

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