A single event latch-up resistant network based on a spaceborne computer

Abstract

This invention discloses a single-event latch-up protection network based on a spaceborne computer, relating to the field of single-event latch-up protection technology. The invention deploys spaceborne computers in a distributed architecture, with each computer equipped with a latch-up detection circuit, an anti-latch-up circuit, and a temperature sensor. When a spaceborne computer detects a single-event latch-up effect in its own power domain through the latch-up detection circuit, it cuts off the power supply through the anti-latch-up circuit to achieve latch-up isolation. Simultaneously, the anti-latch-up circuit notifies neighboring spaceborne computers, enabling them to determine whether the triggering environment has been eliminated based on the temperature sensor on the faulty computer. Once the triggering environment is eliminated, the neighboring computer promptly re-energizes the faulty computer, improving its recovery efficiency.

Description

Technical Field

[0001] This invention relates to the field of single-event latch-up protection technology, and more particularly to an anti-single-event latch-up network based on a spaceborne computer. Background Technology

[0002] Currently, spaceborne computers are manufactured using CMOS integrated circuit technology. In the space radiation environment, when computer chips are exposed to radiation, the semiconductor devices ionize, generating photocurrents, a phenomenon known as single-event latch-up. The parasitic current generated by single-event latch-up typically manifests as a large current, which can significantly impact the normal operation of the chip. Once single-event latch-up occurs, the latch-up state can usually only be released by a power-off and power-on operation. If single-event latch-up is not detected and addressed promptly, the accumulated heat from the parasitic current can burn out the device.

[0003] In existing technologies, current threshold detection is generally used to determine whether a single-event latch-up effect has occurred. When the current exceeds a preset current threshold, the load power supply is immediately cut off, and after a delay, the power is restored to allow the chip to exit the single-event latch-up state, thereby achieving protection against single-event latch-up.

[0004] However, traditional methods for protecting against single-event latch-up will not function properly for a period of time after the overall chip is powered off. The power-on time is controlled by a fixed delay circuit, making it difficult to determine whether the triggering environment of the single-event latch-up effect has been removed. Therefore, the power-on time cannot be controlled autonomously, resulting in low recovery efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide a single-event latch-up network based on a spaceborne computer to address the aforementioned technical problems.

[0006] The present invention adopts the following technical solution:

[0007] This invention provides a single-event latch-up resistant network based on a spaceborne computer, comprising: multiple spaceborne computers in a distributed architecture;

[0008] Each of the aforementioned onboard computers is equipped with a latch-up detection circuit, an anti-latch-up circuit, and a temperature sensor;

[0009] The temperature sensor is located in the power domain of the corresponding onboard computer, and the temperature sensor is connected to each of the neighboring onboard computers.

[0010] The latch-up detection circuit is used to detect the power domain of the corresponding onboard computer and outputs a latch-up signal when a single-event latch-up occurs in the power domain of the corresponding onboard computer.

[0011] The anti-latch-up circuit includes: a power control latch, a latch latch, a first NOT gate, and a first AND gate;

[0012] The input terminal of the latch is connected to the output terminal of the latch detection circuit of the corresponding onboard computer, and the output terminal of the latch is connected to the neighboring onboard computer. When a latch signal is received, the latch is used to output a latch interrupt signal to the neighboring onboard computer after integration and delay, so that the neighboring onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection. When the temperature detection determines that the triggering environment of the single-event latch-up effect of the corresponding onboard computer has been eliminated, the neighboring onboard computer outputs a reset signal to the power control latch.

[0013] The output of the latch is also connected to the first input of the first AND gate via the first NOT gate, the second input of the first AND gate is connected to the output of the latch detection circuit, and the output of the first AND gate is connected to the input of the power control latch. The set terminal of the power control latch is connected to the neighboring onboard computer, and the output terminal of the power control latch is connected to the power domain of the corresponding onboard computer. The power control latch is used to respond to the latch signal before the latch's integration delay and turn off the power of the corresponding onboard computer. After the latch's integration delay, the input of the power control latch flips, and after the single-event latch-up triggering environment is eliminated, the output flips by receiving a reset signal through the set terminal to turn on the power of the corresponding onboard computer.

[0014] Optionally, the set terminal of the latch latch is connected to the control module of the onboard computer.

[0015] The latch latch does not respond to the output signal of the latch detection circuit until it receives a latch signal and the onboard computer has completed its power-on startup.

[0016] The input of the latch is flipped after the single-event latch-up triggering environment of the onboard computer is eliminated. After the onboard computer is powered on and started, the output is flipped by receiving the start-up completion signal through the set terminal, and the output signal of the latch detection circuit is responded to again.

[0017] Optionally, both the power control latch and the latch latch include: a second OR gate, a delay capacitor, a pull-up resistor, a second AND gate, and a trigger.

[0018] The first input terminal of the second OR gate serves as the input terminal of the power control latch / latch latch. The output terminal of the second OR gate is connected to a delay capacitor and then grounded. The output terminal of the second OR gate is also connected to the input terminal of a flip-flop. The output terminal of the flip-flop serves as the output terminal of the power control latch / latch latch. The output terminal of the flip-flop is connected to the first output terminal of the second AND gate. The second input terminal of the second AND gate is connected to a pull-up resistor and then serves as the set terminal of the power control latch / latch latch.

[0019] The power control latch / latch latch is used to delay and integrate the input positive pulse signal, output a high level and hold it relative to the input signal, and under the set negative pulse signal, the output flips to a low level and holds it relative to the set signal.

[0020] Optionally, the latch-up detection circuit includes: a current sensing resistor, a subtractor, a differentiating circuit, an adder, and a positive Schmitt trigger;

[0021] The current sensing resistor is located in the power domain of the onboard computer;

[0022] The voltage across the current sensing resistor is input to the positive and negative input terminals of the subtractor. The output terminal of the subtractor is connected to the input terminal of the differentiator circuit and the first input terminal of the adder, respectively. The output terminal of the differentiator circuit is connected to the second input terminal of the adder. The output terminal of the adder is connected to the input terminal of the positive Schmitt trigger. The output terminal of the positive Schmitt trigger is connected to the input terminal of the latch-up protection circuit and the second input terminal of the first AND gate, respectively.

[0023] The subtractor is used to obtain the voltage difference across the current sensing resistor, the differentiator is used to obtain the gradient of the voltage difference, the adder is used to add the gradient of the voltage difference to the voltage difference in a weighted manner to obtain the voltage to be detected, and the Schmitt trigger is used to determine whether a single-event latch-up occurs in the power domain of the corresponding onboard computer based on the voltage to be detected.

[0024] Optionally, the power domains of the distributed onboard computers are connected in a mesh network structure.

[0025] The latch is used to output a latch interrupt signal to the neighboring onboard computer after an integral delay upon receiving a latch signal, so that the neighboring onboard computer disconnects the connection between the power domain of the neighboring onboard computer and the power domain of the onboard computer where the latch is located.

[0026] Optionally, the anti-latch-up circuit further includes a first OR gate, a second NOT gate, and a pull-up resistor;

[0027] The input of the second NOT gate is connected to the neighboring onboard computer via a pull-up resistor. The output of the second NOT gate is connected to the first input of the first OR gate. The output of the first AND gate is connected to the second input of the first OR gate. The output of the first OR gate is connected to the input of the power control latch.

[0028] The neighboring onboard computer sends control signals to control the power supply of the onboard computer where the latch-up circuit is located via a first OR gate, a second NOT gate, and a pull-up resistor.

[0029] The above-mentioned at least one technical solution adopted in this invention can achieve the following beneficial effects:

[0030] The present invention deploys each onboard computer in a distributed architecture. Each onboard computer is equipped with a latch detection circuit, an anti-latch-up circuit and a temperature sensor. The anti-latch-up circuit includes a power control latch, a latch latch, a first NOT gate and a first AND gate.

[0031] When one of the onboard computers detects a single-event latch-up (SUE) fault in its power domain through the latch detection circuit, the output of the latch is inverted through the first NOT gate before the latch latch integration delay, and the latch signal is input to the anti-latch-up circuit through the first AND gate. The anti-latch-up circuit then cuts off the power supply to achieve latch-up isolation.

[0032] When a faulty onboard computer loses power, the single-event latch-up effect cannot be maintained and will inevitably disappear. At this time, the latch latch, after integration and delay, outputs a latch interrupt signal to the neighboring onboard computer, causing the neighboring onboard computer to control the temperature sensor in the corresponding onboard computer's power domain to detect the temperature and determine whether the triggering environment has been eliminated. If it has been eliminated, the signals at both input terminals of the first AND gate will flip, thereby causing the input of the power control latch to flip. At the same time, the neighboring onboard computer will output a reset signal to the set terminal of the power control latch, causing the output of the power control latch to flip, thus timely controlling the faulty onboard computer to be powered on again. The automatic processing of the latch signal input and the automatic state transition can be completed through a simple circuit structure, improving the recovery efficiency of the faulty onboard computer. Attached Figure Description

[0033] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0034] Figure 1 A schematic diagram of a spaceborne computer network structure provided by the present invention;

[0035] Figure 2 A schematic diagram of an anti-latch-up state machine circuit provided by the present invention;

[0036] Figure 3 This invention provides a schematic diagram of the state transition process of an anti-latch-up state machine after a single-event latch-up occurs.

[0037] Figure 4 A reset and shutdown signal line and its functional diagram are provided for this invention;

[0038] Figure 5 A schematic diagram of a resettable latch circuit provided by the present invention;

[0039] Figure 6 A specific circuit diagram of a power control latch and a latch latch in an anti-latch-up circuit provided by the present invention;

[0040] Figure 7 This is a schematic diagram of a latch detection circuit provided by the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0042] Currently, single-event latch-up (SET) is typically determined by current threshold detection. One method for SET protection is to immediately cut off the load power supply when the detected current exceeds a preset current threshold, and then re-energize after a delay, allowing the chip to exit the SET state. Another method is to absorb or discharge excessive SET current through a buffer after detecting a SET current pulse, thereby reducing the gain of the parasitic transistor and preventing the SET condition from being met, thus achieving latch-up protection.

[0043] The first type of method results in a period of power loss and inability to function properly after the entire chip is powered off. The power-on time is controlled by a fixed delay circuit, making it difficult to determine whether the latch-up triggering environment has been released and thus unable to autonomously control the power-on time. The second type of method uses an additional thyristor rectifier device to discharge the latch-up current. While this effectively suppresses excessive latch-up current, it also places higher demands on the integrated circuit manufacturing process.

[0044] This invention proposes a distributed computer architecture where the computer is composed of a network of multiple nodes. When a single-event latch-up occurs on a single node, the node quickly shuts down to isolate the latch-up and sends a latch-up interruption message to neighboring nodes. Once the node's power is restored and the latch-up is cleared, the neighboring nodes restart the node, enabling the computer to autonomously control its power-on startup and significantly improving the overall radiation resistance of the computer network. The proposed anti-latch-up network utilizes basic CMOS devices to construct an anti-latch-up state machine, eliminating the need for additional process components. It uses circuit logic to implement the latch-up isolation function, preventing the single-node latch-up effect from affecting upstream circuits. After the latch-up is cleared, it can be reset by neighboring nodes and re-enter the latch-up detection mode.

[0045] The technical solutions provided by the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of a spaceborne computer network structure according to the present invention. In one or more embodiments of the present invention, the spaceborne computer-based anti-single-event latch-up network may include multiple spaceborne computers in a distributed architecture. For example, the anti-single-event latch-up network proposed in this invention may be constructed by building the computers in a mesh network structure, where each node processes information. When a single-event latch-up occurs, the faulty node immediately loses its information processing capability, and the handling of the single-event latch-up event requires the faulty node to cooperate with its neighboring nodes.

[0047] Each onboard computer is equipped with a latch-up detection circuit, an anti-latch-up circuit, and a temperature sensor. The temperature sensor is located in the power domain of the corresponding onboard computer and is connected to each neighboring onboard computer. The latch-up detection circuit detects the power domain of the corresponding onboard computer and outputs a latch-up signal when a single-event latch-up occurs in the power domain. The anti-latch-up circuit immediately sends a latch-up interruption signal to neighboring nodes after detecting a latch-up signal and automatically cuts off the power to the faulty node. In one or more embodiments of the present invention, for a mesh network, a node's latch-up interruption can be sent to four neighboring nodes to ensure reliability.

[0048] The anti-latch-up circuit may include a power control latch, a latch latch, a first NOT gate, and a first AND gate.

[0049] The input of the latch is connected to the output of the latch detection circuit of the corresponding onboard computer, and the output of the latch is connected to the neighboring onboard computer. When a latch signal is received, the latch is used to output a latch interrupt signal to the neighboring onboard computer after integration and delay, so that the neighboring onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection. When the temperature detection determines that the triggering environment of the single-event latch-up effect of the corresponding onboard computer has been eliminated, the neighboring onboard computer outputs a reset signal to the power control latch.

[0050] The output of the latch is also connected to the first input of the first AND gate via the first NOT gate. The second input of the first AND gate is connected to the output of the latch detection circuit, and the output of the first AND gate is connected to the input of the power control latch. The set terminal of the power control latch is connected to the neighboring onboard computer, and the output of the power control latch is connected to the power domain of the corresponding onboard computer. The power control latch is used to respond to the latch signal before the latch's integration delay and turn off the power of the corresponding onboard computer. After the latch's integration delay, the input of the power control latch flips. After the single-event latch-up triggering environment is eliminated, the output flips by receiving a reset signal through the set terminal and turns on the power of the corresponding onboard computer.

[0051] Furthermore, in one or more embodiments of the present invention, the anti-latch-up circuit may further include a first OR gate, a second NOT gate, and a pull-up resistor.

[0052] The input of the second NOT gate is connected to the neighboring onboard computer via a pull-up resistor. The output of the second NOT gate is connected to the first input of the first OR gate. The output of the first AND gate is connected to the second input of the first OR gate. The output of the first OR gate is connected to the input of the power control latch. Based on this, the neighboring onboard computer can send control signals via the first OR gate, the second NOT gate, and the pull-up resistor to control the power supply of the onboard computer where the latch-up protection circuit is located.

[0053] Furthermore, in one or more embodiments of the present invention, the power domains of the onboard computers in a distributed architecture are connected according to a mesh network structure.

[0054] The latch is used to output a latch interrupt signal to the neighboring onboard computer after an integral delay upon receiving a latch signal, so that the neighboring onboard computer disconnects the connection between the power domain of the neighboring onboard computer and the power domain of the onboard computer where the latch is located.

[0055] The core logic component of an anti-latch-up circuit is an anti-latch-up state machine. The anti-latch-up state machine can stably and reliably process input signals and generate the required control signals. The circuit principle of the anti-latch-up state machine is as follows: Figure 2 As shown, it contains 4 input signals and 2 output signals.

[0056] The "Shutdown" and "Reset" signals are control signals used by neighboring nodes to control the power supply of this node. They control whether the power supply of this node is turned off or on. Negative pulses are valid, and pull-up resistors are used inside the state machine.

[0057] During the period between power-off and the completion of initialization and stable operation of this node, the single-event latch detection logic may erroneously flip. Therefore, in one or more embodiments of this invention, the set terminal of the latch latch is connected to the control module of the onboard computer. The latch latch does not respond to the output signal of the latch detection circuit until it receives a latch signal and the onboard computer has completed its power-on startup. After the triggering environment of the single-event latch effect in the onboard computer is eliminated, the input of the latch latch flips. After the onboard computer completes its power-on startup, the output flips again by receiving a startup completion signal through the set terminal, thus responding to the output signal of the latch detection circuit. This allows the anti-latch state machine to maintain power-on, shield the latch detection result, and notify the anti-latch state machine of startup completion via a "startup completion" signal, indicating that it can begin operation.

[0058] When a node detects a single-event latch-up, it can notify the anti-latch-up state machine via a "latch" signal. After the "latch" signal is held high for a certain period, the anti-latch-up state machine switches the "latch interrupt" signal high to notify neighboring nodes and immediately switches the "switch" output signal from 0 to 1, thereby shutting off the power supply to the local node. Table 1 shows a schematic of all input and output signals of the anti-latch-up state machine.

[0059] Table 1. Schematic diagram of all input and output signals of the anti-latch-up state machine.

[0060] Signal name direction valid state normal state Meaning description Turn off enter Negative pulse effective Floating upward External control shutdown module power supply Reset enter Negative pulse effective Floating upward External control to turn on module power latch enter Positive pulse effective low level Input a positive pulse when a latching event is detected Startup complete enter Negative pulse effective Floating upward System startup complete input negative pulse switch Output Level active High / Low Level A high level signal shuts off the system power, while a low level signal turns the system power on. Latch interruption Output Level active low level A latching event was detected, so the output level went high.

[0061] Figure 3 This is a schematic diagram of the state transition process of an anti-latch-up state machine after a single-event latch-up occurs, according to the present invention. Corresponding to... Figure 1 In this system, each node is connected to four neighboring nodes. Latch interrupt, shutdown, and reset signals are independently networked, ensuring that information processing can be completed using the simplest circuitry during latching. The reset and shutdown signals employ an OC (Open Collector Output) output, where the voltage is pulled high via a pull-up resistor and grounded when low, providing a wired-AND function (i.e., all output signals are connected together) to allow direct interconnection of the outputs of all neighboring nodes. Figure 4 As shown, Figure 4 This is a schematic diagram of the reset and shutdown signal lines and their functions in this invention.

[0062] To ensure circuit reliability, the main input signals are pulse-active rather than level-active to eliminate potential signal glitches or jitter. Simultaneously, to support simultaneous control by multiple neighboring nodes and ensure stable and reliable signals during module initialization, the main signals require open-circuit (OC) outputs with pull-up resistors. Therefore, the resettable latch in the circuit is designed to meet these requirements, and its logic function is shown in Table 2 below. Table 2 is a schematic diagram of the logic function of a resettable latch in this invention.

[0063] Table 2. Schematic diagram of resettable latch logic function

[0064]

[0065] The resettable latch initializes to 0 upon power-up. When a positive pulse is received at the In input interface, the latch's internal state switches to 1. Thereafter, it remains in state 1 regardless of the In input's state, until a negative pulse signal is received at the Reset input. At this point, the latch's internal state switches to 0 and remains in that state, ignoring any state at the Reset input. The circuit schematic is shown below. Figure 5 As shown, Figure 5 This is a schematic diagram of a resettable latch circuit according to the present invention.

[0066] Depend on Figure 5 As can be seen, the resettable latches of both the power control latch and the latch latch include: a second OR gate, a delay capacitor, a pull-up resistor, a second AND gate, and a flip-flop.

[0067] The first input of the second OR gate serves as the input of the power control latch / latch latch. The output of the second OR gate is connected to a delay capacitor and then grounded. The output of the second OR gate is also connected to the input of a flip-flop. The output of the flip-flop serves as the output of the power control latch / latch latch. The output of the flip-flop is connected to the first output of the second AND gate. The second input of the second AND gate is connected to a pull-up resistor and then serves as the set terminal of the power control latch / latch latch.

[0068] The power control latch / latch latch is used to delay and integrate the input positive pulse signal, output a high level and hold it relative to the input signal, and under the set negative pulse signal, the output flips to a low level and holds it relative to the set signal.

[0069] Based on this, the resettable latch achieves delayed integration through an internal capacitor and uses a positive Schmitt trigger for threshold decision, realizing logic switching. Feeding the output of the Schmitt trigger back to the input enables the latching function, giving the circuit a self-stabilizing characteristic, maintaining the state after switching. To implement the latch's triggering and resetting, an OR gate is used to cut off the feedback path at the input In, and an AND gate is used to cut off the feedback path at the input Reset.

[0070] Figure 6 This is a schematic diagram of a power control latch and a latch latch in an anti-latch-up circuit according to the present invention. Figure 6 In this context, the power control latch is the resettable latch L1, and the latch latch is the resettable latch L2.

[0071] For latch-up detection circuits, the traditional method uses a threshold decision method, which determines that latch-up has occurred as long as the current exceeds a threshold. However, this method has the drawback that: to avoid false triggers, the threshold is usually set to a relatively high current, which may miss micro-latch-up events and lead to system failure.

[0072] In one or more embodiments of the present invention, to solve this problem, the following circuit is proposed: Due to latch-up detection, the decision threshold references not only the absolute value of the current but also the gradient of current change, and then outputs the result after threshold decision. The circuit schematic is shown below. Figure 7 As shown, Figure 7 This is a schematic diagram of a latch detection circuit according to the present invention.

[0073] The latch-up detection circuit may include: a current-sensing resistor, a subtractor, a differentiating circuit, an adder, and a positive Schmitt trigger. The current-sensing resistor is located in the power domain of the onboard computer.

[0074] The voltage across the current sensing resistor is input to the positive and negative input terminals of the subtractor. The output terminal of the subtractor is connected to the input terminal of the differentiator circuit and the first input terminal of the adder, respectively. The output terminal of the differentiator circuit is connected to the second input terminal of the adder. The output terminal of the adder is connected to the input terminal of the positive Schmitt trigger. The output terminal of the positive Schmitt trigger is connected to the input terminal of the latch-up protection circuit and the second input terminal of the first AND gate, respectively.

[0075] The subtractor is used to obtain the voltage difference across the current sensing resistor, the differentiator is used to obtain the gradient of the voltage difference, the adder is used to add the gradient of the voltage difference to the voltage difference in a weighted manner to obtain the voltage to be detected, and the Schmitt trigger is used to determine whether a single-event latch-up occurs in the power domain of the corresponding onboard computer based on the voltage to be detected.

[0076] The subtractor output formula is:

[0077] make We can obtain:

[0078] The detected current satisfies the formula:

[0079] The output formula of the differentiating circuit is:

[0080] The adder output formula is:

[0081] Sorted as:

[0082] Let the weight coefficients

[0083] Current threshold detection can be summarized by the following formula:

[0084] Where L is the output signal of the latch-up detection circuit, I is the current value from Vin to Vout, dI is the current gradient, a1 and a2 are weighting coefficients, T is the preset current threshold, and the activation function can be implemented by a positive Schmitt trigger.

[0085] This invention employs network topology to achieve circuit latch-up resistance, effectively solving the problem of uncontrollable re-power-on after a single-event latch-up. Distributed nodes enable latch-up hardening and isolation, preventing single-event latch-up from affecting upstream current and enhancing the overall chip's radiation resistance. The latch-up resistance state machine, with its simple circuit structure and basic analog components, automatically processes latch-up signal inputs, automatically transitions states, and simultaneously notifies multiple neighboring nodes. When a reset is required, it is controlled by multiple neighboring nodes, exhibiting high reliability. The micro-latch-up detection function considers both the absolute value of the current and changes in the current gradient when latch-up occurs, resulting in higher detection accuracy.

[0086] It should also be noted that the terms "comprising," "including," or any other variations thereof in this invention are intended to cover non-exclusive inclusion, that is, in addition to the elements listed in this invention, other elements not expressly listed may also be included.

[0087] The various embodiments in this invention are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. Each embodiment focuses on describing the differences from other embodiments.

[0088] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A single-event latch-up resistant network based on a spaceborne computer, characterized in that, include: Multiple spaceborne computers with a distributed architecture; Each of the aforementioned onboard computers is equipped with a latch-up detection circuit, an anti-latch-up circuit, and a temperature sensor; The temperature sensor is located in the power domain of the corresponding onboard computer, and the temperature sensor is connected to each of the neighboring onboard computers. The latch-up detection circuit is used to detect the power domain of the corresponding onboard computer and outputs a latch-up signal when a single-event latch-up occurs in the power domain of the corresponding onboard computer. The anti-latch-up circuit includes: a power control latch, a latch latch, a first NOT gate, and a first AND gate; The input terminal of the latch is connected to the output terminal of the latch detection circuit of the corresponding onboard computer, and the output terminal of the latch is connected to the neighboring onboard computer. When a latch signal is received, the latch is used to output a latch interrupt signal to the neighboring onboard computer after integration and delay, so that the neighboring onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection. When the temperature detection determines that the triggering environment of the single-event latch-up effect of the corresponding onboard computer has been eliminated, the neighboring onboard computer outputs a reset signal to the power control latch. The output of the latch is also connected to the first input of the first AND gate via the first NOT gate, the second input of the first AND gate is connected to the output of the latch detection circuit, and the output of the first AND gate is connected to the input of the power control latch. The set terminal of the power control latch is connected to the neighboring onboard computer, and the output terminal of the power control latch is connected to the power domain of the corresponding onboard computer. The power control latch is used to respond to the latch signal before the latch's integration delay and turn off the power of the corresponding onboard computer. After the latch's integration delay, the input of the power control latch flips, and after the single-event latch-up triggering environment is eliminated, the output flips by receiving a reset signal through the set terminal to turn on the power of the corresponding onboard computer.

2. The anti-single-event latch-up network based on a spaceborne computer as described in claim 1, characterized in that, The set terminal of the latch latch is connected to the control module of the onboard computer. The latch latch does not respond to the output signal of the latch detection circuit until it receives a latch signal and the onboard computer has completed its power-on startup. The input of the latch is flipped after the single-event latch-up triggering environment of the onboard computer is eliminated. After the onboard computer is powered on and started, the output is flipped by receiving the start-up completion signal through the set terminal, and the output signal of the latch detection circuit is responded to again.

3. The anti-single-event latch-up network based on a spaceborne computer as described in claim 1, characterized in that, Both the power control latch and the latch latch include: a second OR gate, a delay capacitor, a pull-up resistor, a second AND gate, and a flip-flop; The first input terminal of the second OR gate serves as the input terminal of the power control latch / latch latch. The output terminal of the second OR gate is connected to a delay capacitor and then grounded. The output terminal of the second OR gate is also connected to the input terminal of a flip-flop. The output terminal of the flip-flop serves as the output terminal of the power control latch / latch latch. The output terminal of the flip-flop is connected to the first output terminal of the second AND gate. The second input terminal of the second AND gate is connected to a pull-up resistor and then serves as the set terminal of the power control latch / latch latch. The power control latch / latch latch is used to delay and integrate the input positive pulse signal, output a high level and hold it relative to the input signal, and under the set negative pulse signal, the output flips to a low level and holds it relative to the set signal.

4. The anti-single-event latch-up network based on a spaceborne computer as described in claim 1, characterized in that, The latch-up detection circuit includes: a current sensing resistor, a subtractor, a differentiating circuit, an adder, and a positive Schmitt trigger; The current sensing resistor is located in the power domain of the onboard computer; The voltage across the current sensing resistor is input to the positive and negative input terminals of the subtractor. The output terminal of the subtractor is connected to the input terminal of the differentiator circuit and the first input terminal of the adder, respectively. The output terminal of the differentiator circuit is connected to the second input terminal of the adder. The output terminal of the adder is connected to the input terminal of the positive Schmitt trigger. The output terminal of the positive Schmitt trigger is connected to the input terminal of the latch-up protection circuit and the second input terminal of the first AND gate, respectively. The subtractor is used to obtain the voltage difference across the current sensing resistor, the differentiator is used to obtain the gradient of the voltage difference, the adder is used to add the gradient of the voltage difference to the voltage difference in a weighted manner to obtain the voltage to be detected, and the Schmitt trigger is used to determine whether a single-event latch-up occurs in the power domain of the corresponding onboard computer based on the voltage to be detected.

5. The anti-single-event latch-up network based on a spaceborne computer as described in claim 1, characterized in that, The power domains of the distributed onboard computers are connected according to a mesh network structure. The latch is used to output a latch interrupt signal to the neighboring onboard computer after an integral delay upon receiving a latch signal, so that the neighboring onboard computer disconnects the connection between the power domain of the neighboring onboard computer and the power domain of the onboard computer where the latch is located.

6. The anti-single-event latch-up network based on a spaceborne computer as described in claim 1, characterized in that, The anti-latch-up circuit also includes a first OR gate, a second NOT gate, and a pull-up resistor; The input of the second NOT gate is connected to the neighboring onboard computer via a pull-up resistor. The output of the second NOT gate is connected to the first input of the first OR gate. The output of the first AND gate is connected to the second input of the first OR gate. The output of the first OR gate is connected to the input of the power control latch. The neighboring onboard computer sends control signals to control the power supply of the onboard computer where the latch-up circuit is located via a first OR gate, a second NOT gate, and a pull-up resistor.

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