Data tracking circuit, data tracking processing method, chip and electronic equipment

Abstract

The embodiment of the invention provides a data tracking circuit, a data tracking processing method, a chip and electronic equipment, the data tracking circuit comprises a selection module and a packaging engine module, tracking source data is received and selected to be output as tracking data through the selection module, the packaging engine module packages the tracking data to generate corresponding data frames, and the corresponding data frames are stored in the storage module. The data frames comprise the identifiers used for identifying the types of the data frames, the larger the number of the data frames of the same type is, the shorter the data bit width of the identifiers of the data frames of the type is, compared with identifiers of fixed lengths, the lengths of most identifiers can be shortened, the data size of the data frames is reduced on the whole, and the data transmission efficiency is improved. And thus, the bandwidth required by the packaged data frame is also reduced.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a data tracking circuit, a data tracking processing method, a chip, and an electronic device. Background Technology

[0002] The data tracing function can support the debugging of complex programs. During the data tracing process, the corresponding data needs to be packaged according to the protocol.

[0003] However, due to some provisions of the protocol, the packaged data frames require greater bandwidth. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a data tracking circuit, a data tracking processing method, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a data tracking circuit, which includes a selection module and a packaging engine module. The selection module is used to receive and select output tracking source data as tracking data. The packaging engine module is used to package the tracking data to generate corresponding data frames. The data frames include an identifier for identifying the type of the data frames. The more data frames of the same type there are, the shorter the data bit width of the identifier of the data frames of that type.

[0006] Secondly, embodiments of this application also provide a data tracking processing method, which includes: receiving and selecting output tracking source data as tracking data; packaging the tracking data to generate corresponding data frames, wherein the data frame includes an identifier for identifying the type of data frame, and the more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame.

[0007] Thirdly, embodiments of this application also provide a chip that includes the data tracking circuit described above.

[0008] Fourthly, embodiments of this application also provide an electronic device, which includes the aforementioned chip or data tracking circuit.

[0009] The data tracking circuit, data tracking processing method, chip, and electronic device provided in this application embodiment receive and select the output tracking source data as tracking data through a selection module. The packaging engine module packages the tracking data to generate corresponding data frames. The data frame includes an identifier for identifying the type of data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame. Compared with a fixed-length identifier, the length of most identifiers can be shortened, thereby reducing the overall data volume of the data frame and thus reducing the bandwidth required for the packaged data frame.

[0010] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A first schematic block diagram of the data tracking circuit provided in an embodiment of this application is shown.

[0013] Figure 2 The schematic diagram of the packaging engine module is shown.

[0014] Figure 3 A block diagram of the second packaging engine unit is shown.

[0015] Figure 4 The schematic diagram of the fourth packaging engine unit is shown.

[0016] Figure 5 A second schematic diagram of the data tracking circuit provided in an embodiment of this application is shown.

[0017] Figure 6 A block diagram of the storage module is shown.

[0018] Figure 7 A third block diagram of the data tracking circuit provided in an embodiment of this application is shown.

[0019] Figure 8 A block diagram of the first packaging engine unit is shown.

[0020] Figure 9 A schematic diagram illustrating the process of generating jump information is shown.

[0021] Figure 10 A schematic diagram illustrating the process of generating synchronization information is shown.

[0022] Figure 11 A schematic diagram of the process for generating port-type frames is shown.

[0023] Figure 12 A schematic diagram of the address allocation principle of the address allocation module is shown.

[0024] Figure 13 A schematic diagram of the storage module updating data is shown.

[0025] Figure 14 A schematic diagram of the chip structure provided in an embodiment of this application is shown.

[0026] Figure 15 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0027] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0030] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0032] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0033] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0034] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0035] The Generic Timer Module (GTM) includes a Multi-Channel Sequencer (MCS) module for executing programs, which needs to support tracing functionality for debugging complex programs. Typically, the data generated by the GTM is packaged according to the NEXUS protocol to generate corresponding frames. A major problem with the NEXUS protocol is that the protocol specifies excessively long frame lengths, especially the frame type identifier, which is long and consists of fixed-width data, leading to excessively high downstream bandwidth requirements. This necessitates a high-speed interface on the chip itself to meet these requirements.

[0036] This application uses dynamically lengthened identifiers to distinguish different types of frames. The bit width of the identifier is inversely proportional to the usage frequency of the frame; that is, the higher the usage frequency of a certain type of frame, the shorter the bit width of the identifier; conversely, the lower the usage frequency of a certain type of frame, the longer the bit width of the identifier. This facilitates extreme compression of the data volume of each frame, greatly reducing the data volume and thus reducing the bandwidth required downstream.

[0037] This application provides a data tracking circuit 100, such as... Figure 1As shown, the data tracking circuit 100 includes a selection module 10 and a packaging engine module 20. The selection module 10 is used to receive and select the output tracking source data as tracking data. The packaging engine module 20 is used to package the tracking data to generate corresponding data frames. The data frame includes an identifier for identifying the type of data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame.

[0038] It is understood that the data tracking circuit 100 provided in this application embodiment receives and selects the output tracking source data as tracking data through the selection module 10, and the packaging engine module 20 packages the tracking data to generate corresponding data frames. The data frame includes an identifier for identifying the type of data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame is. Compared with a fixed-length identifier, the length of most identifiers can be shortened, thereby reducing the overall data volume of the data frame and thus reducing the bandwidth required by the packaged data frame.

[0039] It should be noted that the general-purpose timer module can provide the aforementioned trace source data. This trace source data may include at least one of the following: first source data, second source data, third source data, fourth source data, fifth source data, sixth source data, seventh source data, and eighth source data.

[0040] The general-purpose timer module includes at least one of the following: Time Base Unit (TBU), Sensor Pattern Evaluation (SPE), ARU connected TimerOutput Module (ATOM), Multi Channel Sequencer (MCS), Timer Input Module (TIM), Digital PLL Module (DPLL), Advanced Routing Unit (ARU), and Timer Output Module (TOM).

[0041] The first source data is generated by the time base unit. The second source data is generated by the sensor sequence evaluation module. The third source data is generated by the ARU-connected timer output module. The fourth source data is generated by the multi-channel sequence generation module. The fifth source data is generated by the timer input module. The sixth source data is generated by the digital phase-locked loop module. The seventh source data is generated by the advanced interconnect unit. The eighth source data is generated by the timer output module.

[0042] The tracking data includes the MCS address (S-mcs-addr), MCS data (S-mcs-data), ARU data (S-ARU), DPLL data (S-DPLL), IOS data (S-IOS), and TBU data (S-TBU) output by the selection module 10. S-mcs-addr and S-mcs-data are the fourth source data originating from the multi-channel sequence generation module. S-ARU is the seventh source data originating from the advanced interconnect unit. S-DPLL is the sixth source data originating from the digital phase-locked loop module. S-IOS is a combination of the second source data from the sensor sequence evaluation module, the third source data from the ARU-connected timer output module, the fifth source data from the timer input module, and the eighth source data from the timer output module. S-TBU is the first source data originating from the time base unit. Additionally, the packaging engine module 20 can also optionally package externally input global timestamps.

[0043] In some embodiments, a data frame includes at least one of a program frame, a data frame, a port frame, a timestamp frame, and an information indication frame. For example... Figure 2 As shown, the packaging engine module 20 includes at least one of a first packaging engine unit 21, a second packaging engine unit 22, a third packaging engine unit 23, a fourth packaging engine unit 24, and a fifth packaging engine unit 25. The first packaging engine unit 21 is used to generate program class frames; the second packaging engine unit 22 is used to generate data class frames; the third packaging engine unit 23 is used to generate port class frames; the fourth packaging engine unit 24 is used to generate timestamp class frames; and the fifth packaging engine unit 25 is used to generate information indication class frames. At least one of the following data bit widths—the identifier of the program class frame, the identifier of the data class frame, the identifier of the port class frame, the identifier of the timestamp class frame, and the identifier of the information indication class frame—is less than or equal to a preset fixed bit width.

[0044] It should be noted that the first packaging engine unit 21 is used to package the MCS address to generate a program class frame. The second packaging engine unit 22 is used to package S-mcs-data, S-ARU, and S-DPLL to generate corresponding data class frames. The third packaging engine unit 23 is used to package S-IOS to generate a port class frame. The fourth packaging engine unit 24 is used to package S-TBU and global timestamp to generate a timestamp class frame. In this embodiment, the data bit width of the identifiers of various frames can be configured to be less than or equal to a fixed length (preset fixed bit width) according to the usage frequency of various frames from high to low. This can shorten the length of most identifiers, reduce the overall data volume of the data frame, and thus reduce the bandwidth required for the packaged data frame.

[0045] In some embodiments, the fixed bit width may be, for example, 7 or more integer bits (e.g., 8, 9, or 10 bits, etc.), the data bit width of the identifier of the program frame is two bits; the data bit width of the identifier of the data frame is three, five, or six bits; the data bit width of the identifier of the port frame is four bits; the data bit width of the identifier of the timestamp frame is five or six bits; and the data bit width of the identifier of the information indication frame is seven bits.

[0046] It should be noted that in this embodiment, the data bit width of the identifier can be configured from few to many according to the usage frequency of various frames from high to low. Compared with a fixed-length identifier, the length of most identifiers can be shortened, thereby reducing the overall data volume of the data frame and thus reducing the bandwidth required for the packaged data frame.

[0047] In some embodiments, data frames include data tracking information frames, advanced connectivity information frames, and digital phase-locked loop (PLL) information frames. For example... Figure 3 As shown, the second packaging engine unit 22 includes a first packaging unit 221, a second packaging unit 222, and a third packaging unit 223. The first packaging unit 221 is used to generate data tracking information frames, and the data width of the identifier of the data tracking information frame is three bits. The second packaging unit 222 is used to generate advanced interconnection information frames, and the data width of the identifier of the advanced interconnection information frame is five bits. The third packaging unit 223 is used to generate digital phase-locked loop (PLL) information frames, and the data width of the identifier of the PLL information frame is six bits.

[0048] It should be noted that the first packing unit 221 is used to pack S-mcs-data to generate a data tracking information frame. The second packing unit 222 is used to pack S-ARU to generate an advanced interconnect information frame. The third packing unit 223 is used to pack S-DPLL to generate a digital phase-locked loop information frame.

[0049] In some embodiments, timestamp-type frames include internal timestamp synchronization information frames and global timestamp synchronization information frames. For example... Figure 4 As shown, the fourth packaging engine unit 24 includes a fourth packaging unit 241 and a fifth packaging unit 242. The fourth packaging unit 241 is used to generate internal timestamp synchronization information frames, and the data width of the identifier of the internal timestamp synchronization information frame is five bits. The fifth packaging unit 242 is used to generate global timestamp synchronization information frames, and the data width of the identifier of the global timestamp synchronization information frame is six bits.

[0050] It should be noted that the fourth packing unit 241 is used to pack the S-TBU to generate an internal timestamp synchronization information frame. The fifth packing unit 242 is used to generate a global timestamp synchronization information frame from the global timestamp.

[0051] In summary, different types of frames are distinguished by variable-length identifiers (TCODEs). See the table below for details:

[0052]

[0053] In this context, the PTM of MCSA and the PTM of MCSB represent two different program frame types, each with a data length of 32 bits and an identifier (TCODE) of 2 bits. For example, 2'b00 represents the identifier of the PTM of MCSA, and 2'b01 represents the identifier of the PTM of MCSB.

[0054] The DTM of MCSA and the DTM of MCSB represent two different data frame types, each with a data length of 64 bits and a 3-bit identifier (TCODE). For example, 3'b100 represents the identifier of the DTM of MCSA, and 3'b101 represents the identifier of the DTM of MCSB.

[0055] The IOS0 and IOS1 information represent two different port-type frames, each with a data length of 32 bits and a 4-bit identifier (TCODE). For example, 4'b1100 represents the identifier of the port-type frame corresponding to the IOS0 information, and 4'b1101 represents the identifier of the port-type frame corresponding to the IOS1 information.

[0056] ARU information represents Advanced Connectivity Message frames, all of which have a data length of 64 bits and an identifier (TCODE) of 5 bits. For example, 5'b11100 represents the identifier of an Advanced Connectivity Message frame.

[0057] The T_SYNC internal timestamp synchronization information represents an internal timestamp synchronization information frame, with a data length of 32 bits and an identifier (TCODE) of 5 bits. For example, 5'b11101 represents the identifier of the internal timestamp synchronization information frame.

[0058] DPLL information represents digital phase-locked loop information frames, all of which have a data length of 64 bits and an identifier (TCODE) of 6 bits. For example, 6'b111000 represents the identifier of a digital phase-locked loop information frame.

[0059] The G_SYNC global timestamp information represents a global timestamp synchronization information frame, with a data length of 64 bits and an identifier (TCODE) of 6 bits. For example, 6'b111101 represents the identifier of the global timestamp synchronization information frame.

[0060] The INF_M indicator class represents an information indicator frame, with a data length of 32 bits and an identifier (TCODE) of 7 bits. For example, 7'b1111101 represents the identifier of the information indicator frame.

[0061] The structure of a Program Frame (PTM) is shown in the table below:

[0062]

[0063] The table above shows the format of program-type frames for the GTM trace MCS instruction. Generally, trace messages contain the most program flow. For ARM core sight debugging systems, data lengths that are multiples of 32 bits, such as 32, 64, or 96 bits, are highly efficient for data transport and parsing. Based on these considerations, the PTM frame format is defined. PTM is given a shortest identifier (2 bits) and an 8-bit timestamp.

[0064] The structure of the Data Tracking Message (DTM) frame is shown in the table below:

[0065]

[0066] The structure of the Advanced Connectivity Message (ARU) frame is shown in the table below:

[0067]

[0068] The structure of a digital phase-locked loop (DPLL) information frame is shown in the table below:

[0069]

[0070] For the three types of data frames mentioned above, once the corresponding information is enabled, a corresponding information packet will be sent when the data is valid. It is worth noting that Advanced Connectivity Frames (ARUs) do not carry timestamps. When an Advanced Connectivity Frame is generated, an internal timestamp synchronization frame is also generated to indicate the timestamp of the Advanced Connectivity Frame.

[0071] The structure of a port-type frame (IOS) is shown in the table below:

[0072]

[0073] For port-type frames (IOS), the main processing involves signals of the TIM, TOM, ATOM, SPE, and TBU classes. At the start of a trace, IOS0 and IOS1 messages are emitted to indicate the initial high and low levels of the IOS. Whenever a change occurs in either of the two 16-bit port-observable signals (TS16_IOS0 / 1), the corresponding IOS0 / 1 will emit a message to indicate the change.

[0074] The structure of the internal timestamp synchronization information frame (T_SYNC) is shown in the table below:

[0075]

[0076] T_SYNC is a setting used to synchronize internal timestamps. Due to bandwidth considerations, most timestamps are only 12 bits long. If no new information is generated for more than 4096 timestamp counting cycles, T_SYNC will be triggered when new information is generated next time.

[0077] The following rules are used to ensure the correctness of the internal timestamps:

[0078] 1. When trace starts, it sends a T_SYNC message to indicate the current complete internal timestamp.

[0079] 2. The address allocation module 30 ensures that trace information is written to the storage module 40 in the actual generation order.

[0080] 3. For other information (timestamp is 12 bits), if the timestamps of the previous frame data and the current frame data are the same, then the two frames of data were generated by the same timestamp; if the timestamp of the previous frame data is less than the timestamp of the current frame data, then the high bits of the timestamps of the two frames of data are the same; if the timestamp of the previous frame data is greater than the timestamp of the current frame data, then the high bits of the timestamp of the current frame data are increased by 1 compared to the original high bits of the timestamp.

[0081] 4. When T_SYNC and other information are generated at the same time, T_SYNC is filled into storage module 40 first. In this way, the information before T_SYNC is the accumulated timestamp, while the information after T_SYNC message is the updated internal timestamp.

[0082] 5. If frame loss occurs internally, the internal timestamp is synchronized by sending a T_SYNC frame.

[0083] The structure of the global timestamp synchronization information frame (G_SYNC) is shown in the table below:

[0084]

[0085] G_SYNC is used to synchronize system timestamps and GTM trace information. You can choose whether to add a global timestamp to the trace stream and set the period of the global timestamp. The more frequently the global timestamp appears, the more accurate it is, but the more bandwidth it consumes. Therefore, a suitable synchronization period needs to be set by considering all factors.

[0086] The structure of the information indication frame (INF_M) is shown in the table below:

[0087]

[0088] INF_M is mainly used to indicate overflow status that occurs during the trace process, as well as to indicate the end of the entire GTM trace stream.

[0089] In some embodiments, such as Figure 5 As shown, the data tracking circuit 100 also includes an address allocation module 30 and a storage module 40. The address allocation module 30 is used to determine whether there is a data overflow based on the matching result between the total data volume of the data frame to be updated and the available storage space of the storage module 40, and to allocate a corresponding storage address to the data frame if there is no data overflow. The storage module 40 is used to store the data frame to the available storage space according to the storage address, and to output the stored data according to the read pointer.

[0090] It's important to note that the address allocation module 30 determines whether an overflow will occur by using the current read / write pointers and the sum of the quantities of all types of data being updated. If no overflow occurs, subsequent address allocation proceeds; otherwise, the currently generated data is discarded until the data in the storage module 40 is emptied before further data storage begins. Compared to traditional architectures where high-priority and low-priority messages are generated consecutively in a short period, and low-priority messages are prone to overflow, the current architecture eliminates the previous-level cache, allocates addresses in a single cycle, and writes all data to the storage module 40 within that cycle. This prevents the accumulation of single-type data and reduces the possibility of overflow to some extent.

[0091] In some embodiments, different types of data frames have corresponding different update priorities. The total data volume includes a first data volume and a second data volume. The address allocation module 30 is further configured to determine the starting address of the storage address of the data frame to be written based on the sum of the current write pointer and the second data volume. Here, the first data volume is the data volume of the data frame to be written, and the second data volume is the data volume with an update priority higher than that of the data frame to be written.

[0092] It should be noted that the update priorities of different types of data frames are shown in the table below. The smaller the value in the priority table, the higher the update priority. The update priority refers to the priority of writing to storage module 40; the higher the priority, the more quickly it is written to storage module 40.

[0093] Frame Name Number of Words Priority PTM 2 3 DTM 2 4 iOS 2 5 ARU 2 6 T_SYNC 1 0 DPLL 2 7 G_SYNC 2 1 INF_M 1 2

[0094] The word count refers to the data length of the data frame of a certain type. One word typically represents 32 bits, and two words typically represent 64 bits.

[0095] If the current cycle does not overflow, address allocation module 30 allocates addresses according to the priority order: T_SYNC > G_SYNC > INF_M > PTM > DTM > IOS > ARU > DPLL. Each type of packet information has a specific number of write control interfaces, the number of which can be the maximum number of data updates per cycle. When each type of packet information is updated, the initial write address allocation is (the current write pointer + the number of updates with higher priority than that type of packet information in the current cycle).

[0096] In some embodiments, each data frame includes a storage address, data information, and a data validity signal. For example... Figure 6 As shown, the storage module 40 includes at least one storage unit 41. The storage module 40 is used to update the data information to the storage unit 41 and output the stored data corresponding to the read pointer when the storage address matches the address information of the storage unit 41 and the data valid signal is valid.

[0097] It should be noted that when the write pointer (storage address) with data information matches the address of the storage center, and the corresponding data valid signal is high, the value of the write channel will be updated to the storage unit 41 at the corresponding address, and the data at the address corresponding to the read pointer will be output.

[0098] In some embodiments, such as Figure 7 As shown, the data tracking circuit 100 also includes a register module 50 and a tracking control module 60. The register module 50 stores first configuration data and second configuration data. The first configuration data is used to control the gating of the selection module 10. The tracking control module 60 is used to control the start and / or end of the packaging work of the packaging engine module 20 for various types of data frames according to the second configuration data.

[0099] It should be noted that the tracking control module 60 is also used to control the start and / or end of the packaging engine module 20's packaging work for various types of data frames based on at least a portion of the second configuration data, the tracking source data, and at least one of the external control signals (CTI).

[0100] like Figure 7 As shown, the storage module 40 can also communicate with the ATB interface. ATB (Advanced Trace Bus) is a bus interface in the AMBA (Advanced Microcontroller Bus Architecture) protocol family. It is mainly used for the debugging and tracing system of SoC (System on Chip) and supports the Core Sight architecture for efficient data transmission and debugging functions.

[0101] like Figure 8 As shown, the first packetizing engine unit 21 (MCS_PC_PKG) may include multiple MCS channels, each MCS channel having a packetizing engine (PTM_PKG), for example, eight packetizing engines numbered 0, 1...7. Within one cycle, jump information (jump_message) or synchronization information (sync_message) can be generated on one channel based on the received MCS signal. The jump information or synchronization information is at least a portion of the content of a program frame.

[0102] `jump_message` is primarily used to indicate jump instructions and restore program flow. `sync_message` is mainly used to analyze suspend-type instructions within the MCS. Suspend-type instructions can be understood as monitoring the occurrence of certain data; when the expected value does not appear, program flow will not continue. `sync_message` can reflect the waiting time of suspend-type instructions.

[0103] The process of generating jump_message, such as... Figure 9 As shown:

[0104] Start: to begin.

[0105] (ptm_trace_en == 1)?: Determine if ptm_trace_en is high. ptm_trace_en controls the start or end of the PTM trace. If ptm_trace_en is not high, continue monitoring for a high level.

[0106] (mcs_i_valid&mcs_ch match)?: mcs_i_valid is a signal indicating that the address is valid. mcs_ch match is used to indicate the CH sequence number of the generated information. If ptm_trace_en is high, then it is determined whether mcs_i_valid and mcs_ch match are valid.

[0107] Generate jump_message; mcs_addr_cap = mcs_i_addr; where mcs_i_addr is the address of the MCS instruction, and mcs_addr_cap is the address of the last executed MCS instruction. If mcs_i_valid and mcs_ch match are valid (Y), a jump message is generated, and the current mcs_i_addr is captured into mcs_addr_cap.

[0108] (ptm_trace_en == 0)?: Determine if ptm_trace_en is low. If it is low, then end.

[0109] mcs_i_valid&mcs_ch match: If ptm_trace_en is not low, continue to check if mcs_i_valid and mcs_ch match are valid. If mcs_i_valid and mcs_ch match are invalid (N), proceed to step "(ptm_trace_en == 0)?".

[0110] (mcs_i_addr==mcs_addr_cap+1)?: If mcs_i_valid and mcs_ch match are valid (Y), then determine whether mcs_i_addr is equal to mcs_addr_cap+1.

[0111] Generate jump_message; mcs_addr_cap = mcs_i_addr; order_cnt = 0: If mcs_i_addr equals mcs_addr_cap + 1, then generate jump information, capture the current mcs_i_addr into mcs_addr_cap, and set order_cnt to 0.

[0112] (order_cnt==63)?: If mcs_i_addr is not equal to mcs_addr_cap+1, then check if order_cnt is equal to 63.

[0113] If order_cnt equals 63, proceed to step "Generate jump_message; mcs_addr_cap = mcs_i_addr; order_cnt = 0;".

[0114] If order_cnt is not equal to 63, then increment the value of order_cnt by 1 and proceed to step "(ptm_trace_en==0)?".

[0115] In summary, after Trace starts, PTM will be triggered whenever the first valid address of each enabled MCS channel is reached, where order_cnt indicating sequential data execution is 0 (jump_message); it is determined that the difference between the current valid address of the MCS-enabled channel and the previous valid address of that channel is not 1; when the MCS-enabled channel executes 64 instructions consecutively in sequence, order_cnt indicating sequential data execution is 63.

[0116] The process of generating sync_message is as follows: Figure 10 As shown:

[0117] Start: to begin.

[0118] (ptm_trace_en == 1)?: Determine if ptm_trace_en is high. ptm_trace_en controls the start or end of the PTM trace. If ptm_trace_en is not high, continue monitoring for a high level.

[0119] (ptm_trace_en == 0)?: If ptm_trace_en equals 0, then determine whether ptm_trace_en is low.

[0120] (timestamp[2:0]==current_mcs_ch)?: If ptm_trace_en is low, then determine whether timestamp[2:0] is equal to current_mcs_ch?

[0121] Generate sync_message: If timestamp[2:0] equals current_mcs_ch, then generate the synchronization message and end (end). If timestamp[2:0] does not equal current_mcs_ch, then proceed to step "(timestamp[2:0]==current_mcs_ch)?".

[0122] (Generate jump_message)?: If ptm_trace_en is not equal to 0, then determine whether a jump_message has been generated.

[0123] timestamp_cap = timestamp: If a jump_message is generated, the value of timestamp is captured into timestamp_cap, and then the process proceeds to step "(ptm_trace_en == 0)?".

[0124] If no jump message is generated, then determine whether timestamp[11:4] is not equal to timestamp_cap[11:4], timestamp

[12] is equal to timestamp_cap

[12] , and timestamp[2:0] is equal to current_mcs_ch. If not, proceed to step “(ptm_trace_en==0)?”.

[0125] Generate sync_message; timestamp_cap = timestamp; order_cnt = 0: If timestamp[11:4] is not equal to timestamp_cap[11:4], timestamp

[12] is equal to timestamp_cap

[12] , and timestamp[2:0] is equal to current_mcs_ch, then generate sync_message, capture the current timestamp value into timestamp_cap, and set the order_cnt value to 0.

[0126] Here, current_mcs_ch represents the current channel of the MCS, and is used in sync_message to ensure that the sync_message of each channel is not updated simultaneously.

[0127] In summary, no new data has appeared in the MCS-enabled channels for 4096 consecutive timestamp periods (this trigger condition is configurable, and each channel is individually enabled by internal registers, mainly to deal with the analysis of suspended channel instructions in MCS); when the PTM trace ends, each enabled channel will send a frame to indicate the address where the trace ends.

[0128] The process of generating port-type frames, such as... Figure 11 As shown:

[0129] Start: to begin.

[0130] (IOS_trace_en == 1)?: Checks if IOS_trace_en is high. If IOS_trace_en is not high, it continues to check if IOS_trace_en is high. IOS_trace_en enables IOS-class trace messages.

[0131] Generate IOS message; IOS_cap = IOS_signal: If IOS_trace_en is high, an IOS message (port-type frame) is generated, and the current IOS_signal value is captured in IOS_cap. IOS_signal consists of two 16-bit signals that the port needs to observe.

[0132] (IOS_trace_en == 0)?: Determine if IOS_trace_en is low. If IOS_trace_en is low, then end (end).

[0133] (IOS_cap != IOS_signal)?: If IOS_trace_en is not low, does it determine whether IOS_cap is not equal to IOS_signal?

[0134] If IOS_cap is not equal to IOS_signal, proceed to step "Generate IOS message".

[0135] IOS_cap = IOS_signal.

[0136] If IOS_cap is not equal to IOS_signal, then proceed to step "(IOS_trace_en == 0)?".

[0137] Figure 12 Example of interaction between the packing engine (PTM_PKG) and address allocation module 30 for Program Class Frames (PTM):

[0138] The packing engine (PTM_PKG) generates a maximum of two data items at a time, with each updated data item including a data value and a data validity signal.

[0139] When the data validity signal is high, it indicates that new data, such as PTM data 1 and PTM data 2, has been generated in the current cycle. The allocated address follows the rule of the current write pointer plus the number of updates of higher priority than this type of information in the current cycle. If the packing engine (PTM_PKG) generates two data items in the current cycle, namely update data 1 and update data 2, then:

[0140] PTM address 1 = current write pointer + number of updates for T_SYNC + number of updates for G_SYNC + number of updates for INF_M.

[0141] PTM address 2 = current write pointer + number of updates for T_SYNC + number of updates for G_SYNC + number of updates for INF_M + 1.

[0142] The above are the address allocation rules for address allocation module 30.

[0143] Figure 13 An example is shown of a storage cell 41 with address n in storage module 40. The storage module 40 of the current design specification has 32 storage cells 41, and the addresses of these storage cells 41 are 0-31, where n∈(0-31). When the value of any of the preceding addresses is equal to n and the corresponding data valid signal is high, data will be updated in the storage cell 41 with address n.

[0144] For example, for T_SYNC, when the address value is equal to n and the corresponding (data) valid signal is high, the data is updated to the memory cell 41 at address n.

[0145] For G_SYNC, when the value of address 1 is equal to n and the corresponding (data) valid signal 1 is high, data 1 is updated to memory cell 41 at address n. When the value of address 2 is equal to n and the corresponding (data) valid signal 2 is high, data 2 is updated to memory cell 41 at address n.

[0146] For INF_M, when the address value is equal to n and the corresponding (data) valid signal is high, the data is updated to the memory unit 41 at address n.

[0147] For PTM, when the value of address 1 is equal to n and the corresponding (data) valid signal 1 is high, data 1 is updated to memory cell 41 at address n. When the value of address 2 is equal to n and the corresponding (data) valid signal 2 is high, data 2 is updated to memory cell 41 at address n.

[0148] For DTM, when the value of address 1 is equal to n and the corresponding (data) valid signal 1 is high, data 1 is updated to memory cell 41 at address n. When the value of address 2 is equal to n and the corresponding (data) valid signal 2 is high, data 2 is updated to memory cell 41 at address n.

[0149] For IOS, when the value of address 1 is equal to n and the corresponding (data) valid signal 1 is high, data 1 is updated to memory cell 41 at address n. When the value of address 2 is equal to n and the corresponding (data) valid signal 2 is high, data 2 is updated to memory cell 41 at address n.

[0150] For the ARU, when the value of address 1 is equal to n and the corresponding (data) valid signal 1 is high, data 1 is updated to memory cell 41 at address n. When the value of address 2 is equal to n and the corresponding (data) valid signal 2 is high, data 2 is updated to memory cell 41 at address n.

[0151] For DPLL, when the value of address 1 is equal to n and the corresponding (data) valid signal 1 is high, data 1 is updated to memory cell 41 at address n. When the value of address 2 is equal to n and the corresponding (data) valid signal 2 is high, data 2 is updated to memory cell 41 at address n.

[0152] In summary, this application uses variable-length TCODE (Huffman coding) to define the frame format, which simplifies the frame format and greatly reduces the amount of data (traditionally, the NEXUS frame format is used); and the compression method of MCS reduces the complexity of traditional decoding (NEXUS decodes the program flow, sends frames during jumps, and checks whether the current program address is incremented by 1 to send the frame); the architecture consisting of the address allocation module 30 and the storage module 40 can achieve a more efficient data filling method and reduce the risk of overflow.

[0153] This application embodiment also provides a data tracking processing method, which includes: receiving and selecting output tracking source data as tracking data; packaging the tracking data to generate corresponding data frames, wherein the data frame includes an identifier for identifying the type of data frame, and the more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame.

[0154] It is understood that the data tracking processing method provided in this application receives and selects the output tracking source data as tracking data, packages the tracking data to generate corresponding data frames, and the data frames include identifiers for identifying the type of data frames. The more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame is. Compared with a fixed-length identifier, the length of most identifiers can be shortened, thereby reducing the overall data volume of the data frames and thus reducing the bandwidth required by the packaged data frames.

[0155] In some embodiments, the data tracking processing method further includes: configuring the data frame to include at least one of program frame, data frame, port frame, timestamp frame, and information indication frame.

[0156] In some embodiments, the data tracking processing method further includes: a configuration program frame including timestamp data, data corresponding to the number of instructions, address data, data corresponding to the number of channels, and data corresponding to the identifier, arranged sequentially from low to high bits; a configuration port frame including timestamp data, port information data, and data corresponding to the identifier, arranged sequentially from low to high bits; and a configuration information indication frame including timestamp data, information indication data, and data corresponding to the identifier, arranged sequentially from low to high bits.

[0157] In some embodiments, the data tracking processing method further includes: configuring data class frames including data tracking information frames, advanced connection information frames, and digital phase-locked loop (PLL) information frames; configuring data tracking information frames including operation data, timestamp data, address data, data corresponding to read / write instructions, data corresponding to channel numbers, and data corresponding to identifiers of program class frames arranged sequentially from low to high bits; configuring advanced connection information frames including low-bit data, high-bit data, data indicating data source, and data corresponding to identifiers arranged sequentially from low to high bits; configuring digital phase-locked loop (PLL) information frames including timestamp data, PLL data, address data, data corresponding to read / write instructions, and data corresponding to identifiers arranged sequentially from low to high bits.

[0158] In some embodiments, the data tracking processing method further includes: configuring a timestamp class frame to include an internal timestamp synchronization information frame and a global timestamp synchronization information frame; configuring the internal timestamp synchronization information frame to include timestamp data arranged sequentially from the least significant bit to the most significant bit and data corresponding to the identifier; configuring the global timestamp synchronization information frame to include timestamp data arranged sequentially from the least significant bit to the most significant bit and data corresponding to the identifier.

[0159] In some embodiments, the data tracking processing method further includes: forcing all data frames to be written to the storage module in the actual order of their generation through the address allocation module; and prioritizing the writing of the internal timestamp synchronization information frame to the storage module when the internal timestamp synchronization information frame is generated simultaneously with other data frames.

[0160] It should be noted that data generated by different modules in the hardware system may be subject to write competition. Forced sequential writing ensures that the physical order of timestamps is strictly consistent with the storage order, eliminating the risk of timing misalignment and thus improving the accuracy of internal timestamps.

[0161] In some embodiments, the data tracking processing method further includes: when the tracking data stream is started or a frame is lost, sending an internal timestamp synchronization information frame to indicate the current complete internal timestamp; for data frames with a timestamp of N bits, performing timestamp reconstruction logic, where N is an integer and N is less than the number of bits in the complete timestamp.

[0162] It should be noted that sending internal timestamp synchronization information frames during tracking startup or detecting frame loss can be used for initial calibration during system startup and for self-repair when frame loss causes timestamp sequence breaks, thereby improving the accuracy of internal timestamps.

[0163] In some embodiments, the data tracking processing method further includes: when the timestamp of the previous data frame is equal to the timestamp of the current data frame, determining that the previous data frame and the current data frame were generated at the same timestamp; when the timestamp of the previous data frame is less than the timestamp of the current data frame, determining that the high-order bits of the timestamp of the previous data frame are equal to the high-order bits of the timestamp of the current data frame; when the timestamp of the previous data frame is greater than the timestamp of the current data frame, determining that the high-order bits of the timestamp of the current data frame are increased by 1 based on the high-order bits of the timestamp of the previous data frame.

[0164] It should be noted that this embodiment dynamically derives the high-order bit value of the current data frame's timestamp based on the relationship between the timestamp values ​​of consecutive frames. This can prevent the overflow of short-bit-width timestamps, and when a frame's timestamp is corrupted due to interference (such as excessive jumps), the error will not continue to propagate, thereby improving the accuracy of the internal timestamp.

[0165] This application embodiment also provides a chip 200, such as Figure 14 As shown, the chip 200 includes the aforementioned data tracking circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0166] It is understood that since the chip 200 provided in this application embodiment includes the above-mentioned data tracking circuit 100, it can also receive and select the output tracking source data as tracking data through the selection module 10. The packaging engine module 20 packages the tracking data to generate corresponding data frames. The data frame includes an identifier for identifying the type of data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame is. Compared with a fixed-length identifier, the length of most identifiers can be shortened, thereby reducing the data volume of the data frame as a whole, and thus reducing the bandwidth required by the packaged data frame.

[0167] This application also provides an electronic device 300, such as... Figure 15 As shown, the electronic device 300 includes a device body and the aforementioned data tracking circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0168] It is understood that since the electronic device 300 provided in this application embodiment includes the above-mentioned data tracking circuit 100 or chip 200, it can also receive and select the output tracking source data as tracking data through the selection module 10. The packaging engine module 20 packages the tracking data to generate corresponding data frames. The data frame includes an identifier for identifying the type of data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier of that type of data frame is. Compared with a fixed-length identifier, the length of most identifiers can be shortened, thereby reducing the data volume of the data frame as a whole, and thus reducing the bandwidth required by the packaged data frame.

[0169] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A data tracking circuit, characterized in that, The data tracking circuit includes: The selection module is used to receive and select the output tracking source data as the tracking data. The packaging engine module is used to package the tracking data to generate corresponding data frames. The data frames include an identifier for identifying the type of the data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier of the data frame of that type.

2. The data tracking circuit as described in claim 1, characterized in that, The data frame includes at least one of the following: program frame, data frame, port frame, timestamp frame, and information indication frame; the packaging engine module includes at least one of the following engine units: The first packaging engine unit is used to generate the program class frame; The second packaging engine unit is used to generate the data class frame; The third packaging engine unit is used to generate the port class frame; The fourth packaging engine unit is used to generate the timestamp-type frame; The fifth packaging engine unit is used to generate the information indication class frame; Wherein, at least one of the data bit widths of the identifier of the program class frame, the identifier of the data class frame, the identifier of the port class frame, the identifier of the timestamp class frame, and the identifier of the information indication class frame is less than or equal to a preset fixed bit width.

3. The data tracking circuit as described in claim 2, characterized in that, The fixed bit width is 7 bits; The identifier of the program class frame has a data width of two bits; The data width of the identifier of the data frame is three, five, or six bits; The identifier of the port-type frame has a data width of four bits; The data width of the identifier of the timestamp-type frame is five or six bits; The data width of the identifier of the information indicator frame is seven bits.

4. The data tracking circuit as described in claim 3, characterized in that, The data frames include data tracking information frames, advanced connection information frames, and digital phase-locked loop information frames. The second packaging engine unit includes: The first packaging unit is used to generate the data tracking information frame, wherein the data width of the identifier of the data tracking information frame is three bits; The second packaging unit is used to generate the advanced interconnect information frame, wherein the data width of the identifier of the advanced interconnect information frame is five bits. The third packaging unit is used to generate the digital phase-locked loop information frame, wherein the data width of the identifier of the digital phase-locked loop information frame is six bits.

5. The data tracking circuit as described in claim 3, characterized in that, The timestamp-type frames include internal timestamp synchronization information frames and global timestamp synchronization information frames; The fourth packaging engine unit includes: The fourth packaging unit is used to generate the internal timestamp synchronization information frame, wherein the data width of the identifier of the internal timestamp synchronization information frame is five bits. The fifth packaging unit is used to generate the global timestamp synchronization information frame, wherein the data width of the identifier of the global timestamp synchronization information frame is six bits.

6. The data tracking circuit as described in any one of claims 1-5, characterized in that, The data tracking circuit also includes: The address allocation module is used to determine whether there is a data overflow based on the matching result between the total data volume of the data frame to be updated and the available storage space, and to allocate a corresponding storage address to the data frame if there is no data overflow. The storage module is used to store the data frame to the available storage space according to the storage address, and to output the stored data according to the read pointer.

7. The data tracking circuit as described in claim 6, characterized in that, Different types of data frames correspond to different update priorities. The total data volume includes a first data volume and a second data volume. The first data volume is the data volume of the data frame to be written, and the second data volume is the data volume of the data frame with a higher update priority than the data frame to be written. The address allocation module is also used to determine the starting address of the storage address of the data frame to be written based on the sum of the current write pointer and the second data volume.

8. The data tracking circuit as described in claim 6, characterized in that, Each of the data frames includes a storage address, data information, and a data validity signal; The storage module includes at least one storage unit. The storage module is used to update the data information to the storage unit and output the stored data corresponding to the read pointer when the storage address matches the address information of the storage unit and the data valid signal is valid.

9. The data tracking circuit as described in any one of claims 1-5, characterized in that, The data tracking circuit also includes: The register module stores first configuration data and second configuration data, wherein the first configuration data is used to control the selection of the selection module; The tracking control module is used to control the start and / or end of the packaging work of the packaging engine module for various types of data frames according to the second configuration data.

10. The data tracking circuit as described in claim 9, characterized in that, The tracking control module is further configured to control the start and / or end of the packaging engine module's packaging operation for various types of data frames based on at least one of the second configuration data, at least a portion of the tracking source data, and an external control signal.

11. The data tracking circuit according to any one of claims 1-5, characterized in that, The data length of each data frame is an integer multiple of 32 bits.

12. A data tracking and processing method, characterized in that, The data tracking and processing method includes: Receive and select the output tracking source data as the tracking data; The tracking data is packaged to generate corresponding data frames. Each data frame includes an identifier for identifying the type of data frame. The more data frames of the same type there are, the shorter the data bit width of the identifier for that type of data frame.

13. The data tracking and processing method as described in claim 12, characterized in that, The data tracking and processing method further includes: The data frame configuration includes at least one of the following: program frame, data frame, port frame, timestamp frame, and information indication frame.

14. The data tracking and processing method as described in claim 13, characterized in that, The data tracking and processing method further includes: The configuration program frame includes timestamp data, data corresponding to the number of instructions, address data, data corresponding to the number of channels, and data corresponding to the identifier, arranged in order from least significant bit to most significant bit. The configuration of the port class frame includes timestamp data, port information data, and data corresponding to the identifier, arranged sequentially from the least significant bit to the most significant bit. The configuration of the information indication frame includes timestamp data, information indication data, and data corresponding to the identifier, arranged sequentially from the least significant bit to the most significant bit.

15. The data tracking and processing method as described in claim 13, characterized in that, The data tracking and processing method further includes: The data frames are configured to include data tracking information frames, advanced connection information frames, and digital phase-locked loop information frames; The configuration of the data tracking information frame includes operation data, timestamp data, address data, data corresponding to read / write instructions, data corresponding to the number of channels, and data corresponding to the identifier of the program frame arranged from low to high bits; The configuration of the advanced connection information frame includes low-order data, high-order data, data indicating the data source, and data corresponding to the identifier, arranged sequentially from low-order to high-order. The configuration of the digital phase-locked loop information frame includes timestamp data, phase-locked loop data, address data, data corresponding to read / write instructions, and data corresponding to identifiers, arranged sequentially from least significant bit to most significant bit.

16. The data tracking and processing method as described in claim 13, characterized in that, The data tracking and processing method further includes: The timestamp-type frames are configured to include internal timestamp synchronization information frames and global timestamp synchronization information frames; The configuration of the internal timestamp synchronization information frame includes timestamp data and data corresponding to the identifier arranged sequentially from the least significant bit to the most significant bit; The configuration of the global timestamp synchronization information frame includes timestamp data and data corresponding to the identifier arranged sequentially from the least significant bit to the most significant bit.

17. The data tracking and processing method as described in claim 16, characterized in that, The data tracking and processing method further includes: The address allocation module forces all data frames to be written to the storage module in the actual order in which they were generated. When the internal timestamp synchronization information frame is generated simultaneously with other data frames, the internal timestamp synchronization information frame is written to the storage module first.

18. The data tracking and processing method as described in claim 16 or 17, characterized in that, The data tracking and processing method further includes: When the tracking data stream starts or a frame is lost, the internal timestamp synchronization information frame is sent to indicate the current complete internal timestamp; For a data frame with an N-bit timestamp, execute the timestamp reconstruction logic, where N is an integer and N is less than the number of bits in the complete timestamp.

19. The data tracking and processing method as described in claim 18, characterized in that, The data tracking and processing method further includes: When the timestamp of the previous data frame is equal to the timestamp of the current data frame, it is determined that the previous data frame and the current data frame were generated at the same timestamp. When the timestamp of the previous data frame is less than the timestamp of the current data frame, the high-order data of the timestamp of the previous data frame is determined to be equal to the high-order data of the timestamp of the current data frame. When the timestamp of the previous data frame is greater than the timestamp of the current data frame, the high-order bits of the timestamp of the current data frame are determined by adding 1 to the high-order bits of the timestamp of the previous data frame.

20. A chip, characterized in that, The chip includes a data tracking circuit as described in any one of claims 1 to 11.

21. An electronic device, characterized in that, The electronic device includes a device body and a chip as described in claim 20 disposed on the device body.

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