Method and apparatus for interrupt management of a computer processor

Abstract

The application provides an interrupt management method and device of a computer processor, and the interrupt management method comprises the following steps: setting an interrupt latch management module, setting M groups of interrupt functions in the interrupt latch management module, each group of interrupt functions corresponding to N interrupt sources, each interrupt source corresponding to a register, and the interrupt function storing the interrupt state of the interrupt source in the register corresponding to the interrupt source when receiving the interrupt pulse sent by the interrupt source; allocating an independent weight configuration to each group of interrupt functions, performing weighted round-robin arbitration on all registers of the M groups of interrupt functions according to the corresponding weight, selecting the effective register polled, generating the corresponding interrupt information and outputting the interrupt information to a bus for reporting. Compared with the prior art, the interrupt management structure of the application is simple and flexible, the resource consumption is small, and the interrupt state can be reported in time according to the needs.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit chip design and relates to an interrupt management reporting device and method. Background Technology

[0002] Interrupt technology, as a core component of modern computer architecture, is the foundation of the flexibility, efficiency, and reliability of computer systems, improving the utilization efficiency of hardware resources. With the continuous increase in computer system functionality and the rapid rise in system complexity, the number of interrupts between the computer's processor, subsystems, and peripheral devices is increasing rapidly.

[0003] In traditional interrupt design, computer processors typically report interrupts to subsystems and peripheral devices via interrupt lines. As the number of interrupts increases, the number of interrupt lines also increases, along with the number of traces between the processor and subsystems. This leads to a significant increase in the complexity of the interrupt lines in the entire chip system. Furthermore, the interrupt controller often has a limit on the number of interrupt lines that can be allocated to a specific subsystem, meaning the number of interrupts allocated to that subsystem is often far less than its needs. A common practice is to combine multiple interrupts into a single interrupt line and send it to the interrupt controller, which incurs a significant backtracking cost for the software.

[0004] Therefore, there is an urgent need for an interrupt management method and device for computer processors that can solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a method and apparatus for interrupt management of a computer processor, wherein the interrupt management structure is simple and flexible, consumes few resources, and can report the interrupt status in a timely manner as needed.

[0006] To achieve the above objectives, the present invention provides an interrupt management method for a computer processor, comprising: setting up an interrupt latch management module, wherein M groups of interrupt functions are set up in the interrupt latch management module, each group of interrupt functions corresponds to N independent interrupt sources, where M and N are both integers greater than or equal to 2; each interrupt source corresponds to a register, the M groups of interrupt functions communicate with the M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt sources; when an interrupt source generates an interrupt request, it transmits the corresponding interrupt pulse to the corresponding interrupt function; when the interrupt function receives the interrupt pulse from the interrupt source, it stores the interrupt status of the interrupt source in the register corresponding to the interrupt source, and the register storing the interrupt status is called the valid register; an independent weight configuration is assigned to each group of interrupt functions, and weighted polling arbitration is performed on the M×N registers corresponding to the M groups of interrupt functions according to the corresponding weights; when the register selected by the polling arbitration is a valid register, corresponding interrupt information is generated and the interrupt information is output to the bus for reporting.

[0007] Preferably, the interrupt information includes the index of the interrupt function corresponding to the valid register and the location index of the interrupt source.

[0008] Preferably, reporting the interrupt information to the bus involves assembling the interrupt information into an AXI packet and sending it to the bus. However, this is not limited to the AXI protocol; other bus protocols such as APB and AHB can also be used to report the interrupt information.

[0009] Preferably, the weight of the interrupt function is matched with the priority of the interrupt function, and the higher the priority of the interrupt function, the higher the weight of the interrupt function.

[0010] Preferably, the interrupt management method further includes the step of clearing the interrupt status stored in the corresponding valid register after reporting the interrupt information to the bus.

[0011] This invention also provides an interrupt management device for a computer processor, including an interrupt latch management module, a polling management module, and a bus message triggering module. The interrupt latch management module includes M groups of interrupt functions, each group of interrupt functions corresponding to N independent interrupt sources, where M and N are both integers greater than or equal to 2. Each interrupt source corresponds to a register. The M groups of interrupt functions communicate with the M×N interrupt sources respectively and manage the corresponding registers according to the interrupt status of the interrupt sources. When an interrupt function receives an interrupt pulse from an interrupt source, it stores the interrupt status of the interrupt source in the register corresponding to the interrupt source. The register storing the interrupt status is called the valid register. The polling management module assigns an independent weight configuration to each group of interrupt functions and performs weighted polling arbitration on the M×N registers corresponding to the M groups of interrupt functions according to the corresponding weights. When the register selected by the polling arbitration is a valid register, corresponding interrupt information is generated and the interrupt information is sent to the bus message triggering module. The bus message triggering module reports the interrupt information to the bus.

[0012] Preferably, the interrupt information includes the index of the interrupt function corresponding to the valid register and the location index of the interrupt source. The location index of the interrupt source can be either the specific location of the interrupt source or the register number.

[0013] Preferably, the bus message triggering module sends the interrupt information as an AXI packet to the bus. Of course, it is not limited to the AXI protocol; other bus protocols such as APB and AHB can also be used to report the interrupt information.

[0014] Specifically, the bus message triggering module sends the interrupt information as an AXI packet to the bus. After the AXI protocol returns the corresponding handshake signal, the bus message triggering module returns a preparation signal to the polling management module. The polling management module ends the current arbitration based on the preparation signal to continue the next weighted polling arbitration, and sends the completion signal as a reporting feedback signal to the interrupt latch management module, so that the interrupt latch management module clears the interrupt status stored in the currently reported valid register based on the reporting feedback signal.

[0015] Preferably, the bus message triggering module also returns a reporting feedback signal to the corresponding interrupt function through the polling management module, and the interrupt function clears the interrupt status of the currently reported valid register according to the reporting feedback signal.

[0016] Preferably, the weight of the interrupt function is matched with the priority of the interrupt function, and the higher the priority of the interrupt function, the higher the weight of the interrupt function.

[0017] Compared to existing technologies, this invention uses bus-based interrupt information reporting, effectively reducing the number of interrupt lines between the processor and subsystems or peripheral devices, saving a significant amount of interconnects. Furthermore, this invention uses multiple interrupt functions to independently manage the information in the registers corresponding to the interrupt sources. Interrupt status can be independently stored, cleared, and reported, providing flexible control and ensuring that clearing operations performed by one interrupt function do not affect the normal operation of other interrupt functions. Moreover, this invention independently configures the weights of each interrupt function, differentiating interrupt function levels based on importance or interrupt frequency, thereby enabling different performance configurations for different interrupt functions and distinguishing between VIP and regular users. Finally, this invention uses a single register to store the interrupt from a single interrupt source, rather than FIFO or other methods, reducing hardware resource overhead. Attached Figure Description

[0018] Figure 1 This is a structural diagram of the interrupt management device of the present invention. Detailed Implementation

[0019] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0020] This invention discloses an interrupt management device connected between a central processing unit (CPU) and a sub-device. The interrupt management device converts the interrupt status of an interrupt source in the sub-device into corresponding interrupt information and reports it to the CPU via a bus. The sub-device can be a subsystem or other device.

[0021] refer to Figure 1The interrupt management device includes an interrupt latch management module 10, a polling management module 20, and a bus message triggering module 30. The interrupt latch management module 10 includes M groups of interrupt functions 11, each group of interrupt functions 11 corresponding to N independent interrupt sources, where M and N are both integers greater than or equal to 2. Each interrupt source corresponds to a register 12. The M groups of interrupt functions 11 communicate with M×N interrupt sources respectively, and manage the corresponding register 12 according to the interrupt status of the interrupt source. When the interrupt function 11 receives an interrupt pulse from the interrupt source, it stores the interrupt status of the interrupt source in the register 12 corresponding to the interrupt source. The register 12 storing the interrupt status is called the valid register 12. The polling management module 20 assigns an independent weight configuration to each group of interrupt functions 11. Based on the corresponding weight, it performs weighted polling arbitration on the M×N registers 12 corresponding to the M groups of interrupt functions 11. When the register 12 selected by the polling arbitration is a valid register 12, it generates the corresponding interrupt information and sends the interrupt information to the bus message triggering module 30. The bus message triggering module 30 reports the interrupt information to the bus and clears the interrupt status of the corresponding valid register 12 after a valid report.

[0022] Specifically, after reporting the interrupt information to the bus, a reporting feedback signal is returned to the interrupt latch management module 10, so that the interrupt function 11 clears the interrupt status of the currently reported valid register 12 according to the reporting feedback signal.

[0023] The interrupt management device is used to execute an interrupt management method, which includes: when the interrupt source generates an interrupt request, it transmits the corresponding interrupt pulse to the corresponding interrupt function 11; when the interrupt function 11 receives the interrupt pulse from the interrupt source, it stores the interrupt status of the interrupt source in the register 12 corresponding to the interrupt source, and the register 12 storing the interrupt status is called the valid register 12; an independent weight configuration is assigned to each group of interrupt functions 11, and weighted polling arbitration is performed on the M×N registers 12 corresponding to the M groups of interrupt functions 11 according to the corresponding weight; when the register 12 selected by the polling arbitration is the valid register 12, the corresponding interrupt information is generated and the interrupt information is output to the bus for reporting, and a reporting feedback signal is returned to the corresponding interrupt function 11; the interrupt function 11 clears the interrupt status stored in the currently reported valid register 12 according to the reporting feedback signal.

[0024] The interrupt information includes the index of the interrupt function 11 corresponding to the interrupt in the valid register 12 and the location index of the interrupt source. Reporting the interrupt information to the bus involves assembling the interrupt information into an AXI packet and sending it to the bus. Specifically, the bus message triggering module 30 sends the interrupt information into an AXI packet to the bus. After the AXI protocol returns the corresponding handshake signal, the bus message triggering module 30 returns a preparation signal to the polling management module 20. The polling management module 20 ends the current arbitration based on the preparation signal to continue the next weighted polling arbitration, and sends a completion signal as a reporting feedback signal to the interrupt latch management module 10, so that the interrupt latch management module 10 clears the interrupt status stored in the currently reported valid register 12 based on the reporting feedback signal. The AXI protocol ensures that interrupt reporting is completed after each bus access successfully hands off the destination.

[0025] In this embodiment, the weight of the interrupt function 11 is matched with the priority of the interrupt function 11; the higher the priority of the interrupt function 11, the higher its weight. The interrupt function 11 can manage one or more registers simultaneously.

[0026] In practical applications, taking 101 interrupt functions as an example, each interrupt function corresponds to 16 interrupt sources to support 16 interrupts, for a total of 11 × 16 = 1616 interrupts.

[0027] When an interrupt occurs, the interrupt status is transmitted to interrupt function 11 in the form of a pulse. Interrupt function 11 uses a register to identify the interrupt status for each interrupt source. A register value of 0 indicates that the interrupt source has no interrupt request, while a value of 1 indicates that the interrupt source has an interrupt to be issued. When any number of interrupt pulses from the 1616 interrupt sources arrive, interrupt function 11 sets the corresponding register to 1. After receiving a signal from the polling management module 20, the corresponding register is cleared to 0. Of course, in addition, when one or more interrupt functions 11 issue a clear command, the registers of the corresponding interrupt function 11 are cleared uniformly. When the interrupt latch management module 10 receives a valid software-controlled clear signal, it clears all the registers 12 (1616 registers) corresponding to all interrupt functions 11.

[0028] The polling management module 20 employs a weighted polling arbitration algorithm. In the first step of the loop, it monitors the interrupt status of 1616 registers. When a register 12 is found to be 1, it selects that register and records the interrupt function 11 number and the register 12 or interrupt source number. These numbers are then passed as interrupt information to the downstream module—the bus message triggering module 30. Simultaneously, a valid signal is set to indicate that valid interrupt information needs to be output. After the polling management module 20 sets the valid signal, the bus message triggering module 30 begins its operation, using the interrupt information transmitted by the polling management module 20 as data, forming an AXI packet, and sending it to the bus. Next, the corresponding handshake signal for the AXI packet is sent to the polling management module 20, indicating that the interrupt reporting is complete. A Ready signal is returned to the polling management module 20, ending the current arbitration. The polling management module 20 returns a reporting feedback signal—complete signal—to the interrupt latch management module 10, which clears the corresponding register. Simultaneously, the polling management module 20 continues polling to find the next valid register and initiate the next round of interrupt reporting.

[0029] Among them, AXI: Advanced eXtensible Interface, is a high-performance, low-latency on-chip bus protocol; FIFO: First Input First Output, refers to first-in, first-out; APB: Advanced Peripheral Bus, means peripheral bus; AHB: Advanced High Performance Bus, is an advanced high-performance bus.

[0030] Each interrupt function 11 can be configured with a different weight, and the weight determines the number of times each interrupt function 11 is arbitrated in each arbitration cycle. Alternatively, each interrupt function 11 can be configured with the same weight, in which case all interrupt functions 11 have the same priority.

[0031] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. An interrupt management method for a computer processor, characterized in that: include: An interrupt latch management module is set up, in which M groups of interrupt functions are set up, and each group of interrupt functions corresponds to N independent interrupt sources, where M and N are both integers greater than or equal to 2; Each interrupt source corresponds to a register. The interrupt functions in the M groups communicate with the M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt source. When the interrupt source generates an interrupt request, it transmits the corresponding interrupt pulse to the corresponding interrupt function. When the interrupt function receives the interrupt pulse from the interrupt source, it stores the interrupt status of the interrupt source in the register corresponding to the interrupt source. The register that stores the interrupt status is called the valid register. Each interrupt function is assigned an independent weight configuration. Based on the corresponding weight, the M×N registers corresponding to the M interrupt functions are weighted and polled for arbitration. When the register selected by the polling arbitration is a valid register, the corresponding interrupt information is generated and the interrupt information is output to the bus for reporting.

2. The interrupt management method as described in claim 1, characterized in that: The interrupt information includes the index of the interrupt function corresponding to the valid register and the location index of the interrupt source.

3. The interrupt management method as described in claim 1, characterized in that: Specifically, the interrupt information is reported to the bus by assembling it into an AXI packet and sending it to the bus.

4. The interrupt management method as described in claim 1, characterized in that: The weight of the interrupt function is matched with the priority of the interrupt function; the higher the priority of the interrupt function, the higher the weight of the interrupt function.

5. The interrupt management method as described in claim 1, characterized in that: It also includes the step of clearing the interrupt status stored in the corresponding valid register after reporting the interrupt information to the bus.

6. An interrupt management device for a computer processor, characterized in that: It includes an interrupt latch management module, a polling management module, and a bus message triggering module. The interrupt latch management module includes M groups of interrupt functions, each group of interrupt functions corresponding to N independent interrupt sources, where M and N are both integers greater than or equal to 2. Each interrupt source corresponds to a register. The M groups of interrupt functions communicate with M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt sources. When an interrupt function receives an interrupt pulse from an interrupt source, it stores the interrupt status of the interrupt source in the register corresponding to the interrupt source. The register storing the interrupt status is called the valid register. The polling management module assigns an independent weight configuration to each group of interrupt functions, and performs weighted polling arbitration on the M×N registers corresponding to the M groups of interrupt functions according to the corresponding weight. When the register selected by the polling arbitration is a valid register, the corresponding interrupt information is generated and the interrupt information is sent to the bus message triggering module. The bus message triggering module reports the interrupt information to the bus.

7. The interrupt management device as described in claim 6, characterized in that: The interrupt information includes the index of the interrupt function corresponding to the valid register and the location index of the interrupt source.

8. The interrupt management device as described in claim 6, characterized in that: The bus message triggering module sends the interrupt information as an AXI packet to the bus.

9. The interrupt management device as described in claim 6, characterized in that: The bus message triggering module also returns a reporting feedback signal to the corresponding interrupt function through the polling management module. The interrupt function clears the interrupt status of the currently reported valid register based on the reporting feedback signal.

10. The interrupt management device as described in claim 6, characterized in that: The weight of the interrupt function is matched with the priority of the interrupt function; the higher the priority of the interrupt function, the higher the weight of the interrupt function.

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