FPGA hardware acceleration method and device based on DPU

Through the DPU-based FPGA hardware acceleration method, the problems of long design time of FPGA hardware and limitation of computing operator type in the prior art are solved, and efficient neural network inference acceleration and computing efficiency improvement are achieved.

CN119647524AInactive Publication Date: 2025-03-18CHINA COAL RES INST +1
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Patent Information

Application Number
CN202411546191.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-10-31
Publication Date
2025-03-18
Estimated Expiration
Not applicable · inactive patent

AI Technical Summary

Technical Problem

When deploying neural network models on FPGA chips, the prior art requires long-term hardware design, which cannot adapt to complex and easy-to-change application needs, and the types of supported computing operators have obvious limitations.

Method used

Using the DPU-based FPGA hardware acceleration method, the deep learning processing unit DPU is connected to the FPGA chip, obtaining initial data, extracting equivalent instructions, and controlling the FPGA chip based on these data and instructions to accelerate the inference of the convolutional neural network.

Benefits of technology

It realizes flexible neural network inference acceleration, improves inference speed, improves computing efficiency, and solves the problem of restricting neural network acceleration by existing accelerators.

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Abstract

The invention provides a DPU-based FPGA hardware acceleration method and device, relates to the technical field of data processing, is applied to a deep learning processing unit DPU, the DPU is connected with a field programmable gate array FPGA chip, and the method comprises the steps that initial data are acquired, the initial data at least comprise input data of a target convolutional neural network, and the input data of the target convolutional neural network are acquired; the target convolutional neural network is used for performing data processing on the initial data; extracting an equivalent instruction after format conversion of the target convolutional neural network; and based on the initial data and the equivalent instruction, controlling a field programmable gate array (FPGA) chip to accelerate reasoning of the target convolutional neural network. The problem that an existing accelerator limits neural network acceleration is solved, and based on high-level parallelism and energy efficiency of the DPU, neural network reasoning acceleration can be flexibly achieved, the reasoning speed is increased, and the calculation efficiency is improved.
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