Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel includes a shift register including N cascaded shift register units, each of the shift register units including a driving module and a gating module, one control end of the gating module being connected with an output end of the driving module; the output end of the driving module in the i-th shift register unit being connected with the input end of the driving module in the (i+1)-th shift register unit, i and N being integers, 1≤i<N; the gating module being configured to receive at least the signal output by the driving module and a sweep control signal, and output a sweep signal; the sweep control signal and the sweep signal each including a ramp signal, the period of the sweep control signal being n*H, H being the scanning time of one row of pixels, n being an integer, n≥2; in the period of the sweep control signal, the width of the ramp signal in the sweep control signal being (n-1)*H+A, 0<A<H. The present application can make the gray scale control more accurate and improve the display effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Currently, light-emitting diodes (LEDs) are widely used in the field of display, such as Micro-LED and Mini-LED, which are often used as display pixels. Micro-LED and Mini-LED are usually driven by Pulse Amplitude Modulation (PAM) circuit and Pulse Width Modulation (PWM) circuit. Among them, the PWM circuit controls the light-emitting pulse width, and the PAM controls the light-emitting pulse amplitude. A sweep signal is needed in the PWM+PAM circuit. Currently, one way to set the sweep signal is to use a shift register circuit and a gating circuit to generate it. The sweep signal generated by the current method has a short working time, which may not be able to completely turn off the light-emitting path within the working time, and the short working time cannot achieve accurate gray scale control, which affects the display effect. SUMMARY

[0003] In order to solve the problems existing in the prior art, the present application provides a display panel and a display device to solve the technical problem of increasing the working time of the sweep signal and improving the display effect.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising a shift register, the shift register comprising N shift register units connected in cascade, each shift register unit comprising a driving module and a gating module, one control end of the gating module being connected with an output end of the driving module; the output end of the driving module in the i-th shift register unit being connected with the input end of the driving module in the (i+1)-th shift register unit, i and N being integers, 1≤i<N;

[0005] The gating module is configured to receive at least the signal output by the driving module and a sweep control signal, and output a sweep signal; the sweep control signal and the sweep signal each comprising a ramp signal, the period of the sweep control signal being n H, H being the scanning time of one row of pixels, and n being an integer, n≥2; wherein, in the period of the sweep control signal, the width of the ramp signal in the sweep control signal is (n-1) H+A, 0<A<H.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present application further provides a display device comprising the display panel provided by any embodiment of the present application.

[0007] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: In this embodiment of the invention, the width of the ramp signal in the frequency sweep control signal is set to (n-1). With H+A, the width of the GND holding period in the sweep frequency control signal is less than H, which can maximize the proportion of the ramp signal in the sweep frequency control signal cycle. This can increase the width of the ramp signal of the sweep frequency signal generated by the shift register unit, thereby increasing the working time of the sweep frequency signal. This ensures that the light-emitting path is completely turned off while the slope of the sweep frequency signal remains unchanged, and makes grayscale control more precise, thus improving the display effect. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the period of a frequency sweep control signal in a related technology;

[0010] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0011] Figure 3A This is a schematic diagram of a shift register unit provided in an embodiment of the present invention;

[0012] Figure 3B A signal timing diagram provided in an embodiment of the present invention;

[0013] Figure 4 Another signal timing diagram provided in an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0015] Figure 6 A timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0016] Figure 7 Another signal timing diagram provided in an embodiment of the present invention;

[0017] Figure 8 Another signal timing diagram provided in an embodiment of the present invention;

[0018] Figure 9 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0021] In the related art, the sweep signal sweep is generated by a shift register circuit and a gating circuit, and the sweep control signal sweep-in is output as the corresponding sweep signal sweep at the gating moment through the gating circuit. Figure 1 It is a schematic diagram of the period of the sweep control signal in a related art. In Figure 1 the embodiment, the period of the sweep control signal sweep-in is 6 H, where H represents the line time, that is, the scanning time corresponding to one line of pixels during display. There are 6 sweep control signals arranged in the display panel, namely the sweep control signal sweep-in1 to the sweep control signal sweep-in6. It can be seen from the signal waveform that in order to prevent signal interference between the sweep signals sweep corresponding to each pixel circuit row, it is necessary to set the sweep control signal sweep-in to have a GND holding period, and the duration of the ramp signal in the sweep control signal sweep-in is​​​​​​​​​​​​​Figure 2 As shown, the display panel includes a shift register 1, which comprises N cascaded shift register units 10. Figure 2 The diagram illustrates a two-stage shift register unit 10. The shift register unit 10 includes a driver module 11 and a gating module 12. One control terminal of the gating module 12 is connected to the output terminal of the driver module 11. The output terminal of the driver module 11 in the i-th stage shift register unit 10(i) is connected to the input terminal of the driver module 11 in the (i+1)-th stage shift register unit 10(i+1), where i and N are integers, and 1 ≤ i. <N。

[0024] The display panel also includes multiple pixel circuits 20, which drive sub-pixels. These sub-pixels can be, for example, Micro-LEDs, Mini-LEDs, or organic light-emitting devices. The multiple pixel circuits 20 are arranged horizontally in a pixel circuit row 20h. For LED devices, which are current-driven devices, constant current driving ensures stable operation under different working conditions and significantly improves the device's lifespan. The brightness of an LED is related to the current flowing through it; the longer the current flows, the greater the brightness. Therefore, the brightness of the LED can be adjusted by regulating the duration of current flow, enabling grayscale adjustment when using LEDs as pixels. In this embodiment, the pixel circuit includes a first driving circuit PAM and a second driving circuit PWM. The first driving circuit PAM is a pulse amplitude modulation circuit, and the second driving circuit PWM is a pulse width modulation circuit. The first driving circuit PAM is configured to control the amplitude of the driving current supplied to the sub-pixel based on a first data voltage, and the second driving circuit PWM is configured to control the duration of the driving current supplied to the sub-pixel based on a second data voltage. The output of the gating module 12 is connected to the second driving circuit PWM. The display panel contains multiple sweep signal lines (marked with the same symbols as the scan signal sweep), each sweep signal line providing a sweep signal sweep to multiple second drive circuits (PWM) within a pixel circuit row 20h. Figure 2 As can be seen, the gating module 12 in the shift register unit 10 is connected to the second driving circuit PWM via the sweep signal line. The sweep signal sweep includes a ramp signal. By coordinating the sweep signal sweep and the second data voltage, the timing at which the second driving circuit PWM provides control signals to the first driving circuit PAM can be controlled, thereby controlling the turn-off time of the driving transistor in the first driving circuit PAM, and thus adjusting the duration of the driving current supplied to the sub-pixel. The specific circuit operation will be described in the following embodiment involving the pixel circuit.

[0025] in addition, Figure 2The diagram shows the shift register unit 10 located on one side of the pixel circuit row 20h. In some embodiments, the shift register unit 10 is disposed between two adjacent pixel circuit rows 20h, which can help to narrow the bezel of the display panel; this is not illustrated in the diagram here.

[0026] In this embodiment of the invention, the gating module 12 is configured to receive at least the signal output by the driving module 11 and the sweep frequency control signal sweep-in, and output the sweep frequency signal sweep. Figure 3A This is a schematic diagram of a shift register unit provided in an embodiment of the present invention, as shown below. Figure 3A As shown, the shift register unit 10 includes a driving module 11 and a gating module 12. The driving module 11 includes an input terminal IN and an output terminal OUT. When the shift register units 10 are cascaded, the input terminal IN of the driving module 11 is connected to the output terminal OUT of the driving module 11 in the previous shift register unit 10. The driving module 11 can be any circuit structure capable of signal shifting. The driving module includes a first transistor M1 and a second transistor M2. The control terminal of the first transistor M1 is connected to the first node Q1, and the control terminal of the second transistor M2 is connected to the second node Q2. Under the control of the potential of the first node, the first transistor M1 provides a first voltage signal VGH to the output terminal OUT of the driving module 11, and under the control of the potential of the second node Q2, the second transistor M2 provides a second voltage signal VGL to the output terminal OUT of the driving module 11. The gating module 12 includes a third transistor M3 and a fourth transistor M4. The control terminal of the third transistor M3 is connected to the output terminal OUT of the drive module 11, and the control terminal of the fourth transistor M4 is connected to the first node Q1. The first terminal of the third transistor M3 receives the sweep frequency control signal sweep-in, and the first terminal of the fourth transistor M4 receives the third voltage signal sweep-V0. The second terminals of the third transistor M3 and the second terminals of the fourth transistor M4 are connected to the output terminal of the gating module 12.

[0027] Optional, such as Figure 3AAs shown, the driving module 11 also includes transistors M5 through M18 (M6 is the sixth transistor, M7 is the seventh transistor, and so on). The driving module 11 also includes four capacitors: C1 (first capacitor), C2 (second capacitor), C3 (third capacitor), and C4 (fourth capacitor). The first node Q1, second node Q2, node Q3, and node Q4, as well as nodes Q5, Q6, QB1, and QB2, are labeled in the driving module 11. The operation of the driving module 11 requires a reset signal RST, a first clock signal CK, a second clock signal XCK, a first voltage signal VGH, and a second voltage signal VGL. The gating module 12 also includes transistor M19 and capacitor C5. The control terminal of the gating module 12 is connected to the driving module 11. Specifically, the control terminal of transistor M3 is connected to the output terminal OUT of the driving module 11 via transistor M19, and the control terminal of transistor M4 is connected to the first node Q1. For the drive module 11, when the second node Q2 is at a low potential and the first node Q1 is at a high potential, the output terminal OUT of the drive module 11 outputs a low-level signal of the second voltage signal VGL; when the first node Q1 is at a low potential, the output terminal OUT of the drive module 11 outputs a high-level signal of the first voltage signal VGH.

[0028] Figure 3B A signal timing diagram provided in this embodiment of the invention can be applied to... Figure 3A The driver module 11 is driven. (Refer to Figure 3 and...) Figure 4Let's look at the timeframes. During time period t10, the first clock signal CK is low, the second clock signal XCK is high, and the input terminal IN is high. Node Q3 is written with a high level, and node Q4 is written with a low level. During this time, the first node Q1 is written with a low level, and the second node Q2 is written with a high level. The output terminal OUT of the driver module 11 outputs a high-level signal. During time period t11, the first clock signal CK is high, the second clock signal XCK is low, and the input terminal IN is low. Node Q3 remains high, node Q4 remains low, the second node Q2 remains high, and the first node Q1 remains low. The output terminal OUT of the driver module 11 outputs a high-level signal. During time period t12, the first clock signal CK is low, the second clock signal XCK is high, and the input terminal IN is low. Node Q3 is written with a low level, and node Q4 is written with a low level. Node Q3 controls the eighteenth transistor M18 to turn on. The first node Q1 is written with a high level, while the second node Q2 is written with a low level. The output terminal OUT of the driver module 11 outputs a low-level signal. During time period t13, the first clock signal CK is low, the second clock signal XCK is high, and the input IN is high. Node Q3 is written with a high level, node Q4 is written with a low level, the first node Q1 is written with a high level, and the second node Q2 is written with a high level. The output OUT of the driver module 11 maintains a low-level signal. During time period t14, the first clock signal CK is high, the second clock signal XCK is low, and the input IN is high. Node Q3 remains high, node Q4 remains low, the first node Q1 is written with a low level, and the second node Q2 is written with a high level. The output OUT of the driver module 11 outputs a high-level signal. Furthermore, between time periods t12 and t13, the first node Q1 remains high, the second node Q2 remains low, and the output OUT of the driver module 11 outputs a low-level signal.

[0029] Figure 4 A signal timing diagram provided in this embodiment of the invention can be applied to... Figure 3A The provided shift register unit 10. Combined with... Figure 3A , Figure 3B and Figure 4During the period when the second node Q2 is at a low potential and the first node Q1 is at a high potential, the output terminal OUT of the drive module 11 outputs a low-level signal, controlling the third transistor M3 to turn on. The gating module 12 outputs the waveform of the sweep frequency control signal sweep-in as the sweep frequency signal sweep. During the period when the first node Q1 is at a low potential, the output terminal OUT of the drive module 11 outputs a high-level signal. The low potential of the first node Q1 controls the fourth transistor M4 to turn on, and the gating module 12 outputs the voltage signal provided by the third voltage signal sweep-V0. According to the working process of the shift register unit 10, the waveform of the sweep frequency control signal sweep-in affects the working time of the sweep frequency signal sweep.

[0030] In this embodiment of the invention, the sweep frequency control signal sweep-in is a periodic signal. Both the sweep frequency control signal sweep-in and the sweep frequency signal sweep include ramp signals, which are signals where the voltage changes over time. The period of the sweep frequency control signal sweep-in is n. H, where H is the scan time of one row of pixels, and n is an integer, n≥2; where, in the period of the sweep frequency control signal sweep-in, the width of the ramp signal in the sweep frequency control signal sweep-in is (n-1). H+A, 0 <A<H。 Figure 4 Taking n=6 as an example, from Figure 4 As can be seen, the sweep frequency control signal sweep-in includes a ramp signal and a GND hold period. During the GND hold period, the sweep frequency control signal sweep-in is a constant voltage signal, and the sum of the width of the ramp signal and the width of the GND hold period is one cycle. It can be understood that in this embodiment of the invention, the signal width refers to the duration of the signal.

[0031] In this embodiment of the invention, the width of the ramp signal in the sweep-in frequency control signal is set to (n-1). If H+A, the width of the GND holding period in the sweep frequency control signal sweep-in is less than H, which can maximize the proportion of the ramp signal in the sweep frequency control signal sweep-in period, thereby increasing the width of the ramp signal of the sweep frequency signal sweep generated by the shift register unit 10, thus increasing the working time of the sweep frequency signal sweep. This ensures that the light emission path is completely turned off while the slope of the sweep frequency signal sweep remains unchanged, and makes grayscale control more precise, improving the display effect.

[0032] In this embodiment of the invention, the driving module 11 has a signal shifting function, and the effective level width of the output signal at the output terminal OUT of the driving module 11 is not less than the effective level width of the received signal at its input terminal IN. The effective level refers to the level at which the transistor connected to it can be turned on. Figure 4The diagram illustrates the effective level as low. In the first-stage shift register unit 10, the input of the drive module 11 receives the start signal STV, where the width of the effective level in the start signal STV is t0, and t0 ≥ (n-1). H+A. Taking n=6 as an example, the width of the ramp signal in the sweep-in frequency control signal is 5. H+A, the width of the effective level in the start signal STV is ≥5. H+A. In this embodiment of the invention, the width of the effective level in the start signal STV is set to be no less than the width of the ramp signal in the sweep frequency control signal sweep-in. Therefore, the effective level width of the signal output by the output terminal OUT of the drive module 11 is no less than the width of the ramp signal in the sweep frequency control signal sweep-in. This allows the complete output of the ramp signal in the sweep frequency control signal sweep-in as the sweep frequency signal sweep to be used when the control gating module 12 is working, thereby increasing the working time of the sweep frequency signal sweep.

[0033] In some embodiments, n is an even number, and the width of the effective level in the start signal STV is t0 = (n+1). H. Combination Figure 3B As shown in the schematic timing diagram, the signal shifting operation of the driver module 11 requires the coordination of the first clock signal CK and the second clock signal XCK. Specifically, during time period t12, the first clock signal CK is low, and the output terminal OUT of the driver module 11 begins to output a low-level signal. During time period t14, the first clock signal CK is high, and the output terminal OUT of the driver module 11 begins to output a high-level signal, thus ending the low-level signal output. From the start of time period t12 to the start of time period t14, the first clock signal CK has four low-level pulses and three high-level pulses, with one pulse representing one line duration. This means that the duration of the low-level signal output by the output terminal OUT is an odd number of line durations. Therefore, due to the structure and operating principle of the driver module 11, the effective level signal output by its output terminal OUT can only exist for an odd number of line durations. Let t0 = (n+1). H enables the effective level width of the output signal at the output terminal OUT of the drive module 11 to be (n+1). H. The effective level width of the output signal at the output terminal OUT of the drive module 11 is greater than the period of the sweep frequency control signal sweep-in. When the control gating module 12 is working, the signal at the output terminal OUT of the drive module 11 can control the complete output of the ramp signal in the sweep frequency control signal sweep-in as the sweep frequency signal sweep, thereby increasing the working time of the sweep frequency signal sweep.

[0034] In some implementations, such asFigure 4 As shown, the ramp signals in the sweep frequency signal include a first ramp signal B1 and a second ramp signal B2, where the width of the second ramp signal B2 is smaller than the width of the first ramp signal B1. The width of the first ramp signal B1 is (n-1). H+A. Combination Figure 3A and Figure 4 During the period when the output terminal OUT of the drive module 11 outputs a low level (i.e., an effective level), the nineteenth transistor M19 is turned on, and the ramp signal in the sweep frequency control signal sweep-in is output as the sweep frequency signal sweep. The width of the first ramp signal B1 in the sweep frequency signal sweep is the working time of the sweep frequency signal sweep. Since the effective level width of the output signal at the output terminal OUT of the drive module 11 is greater than the period of the sweep frequency control signal sweep-in, during the period when the output terminal OUT of the drive module 11 outputs a low level, the gating module 12 outputs not only the waveform of the sweep frequency control signal sweep-in within one cycle, but also a portion of the waveform of the sweep frequency control signal sweep-in within the next cycle. Therefore, the ramp signal in the sweep frequency signal sweep includes the first ramp signal B1 and the second ramp signal B2. The second ramp signal B2 is essentially a small tail phenomenon of the sweep frequency signal sweep.

[0035] In this embodiment of the invention, the width of the second ramp signal B2 is less than H. Combined with... Figure 4 As can be seen, influenced by the sweep-in waveform of the frequency sweep control signal, during the period when the output terminal OUT of the drive module 11 outputs a low level, the sweep signal sweep includes not only the first ramp signal B1 and the second ramp signal B2, but also a constant voltage signal. For example, there is a constant voltage signal V between the first ramp signal B1 and the second ramp signal B2, and the width of the constant voltage signal V is approximately equal to the width of the GND holding period. By setting the width of the second ramp signal B2 to be less than H, and the sum of the widths of the constant voltage signal V and the second ramp signal B2 equal to H, it is ensured that the width of the first ramp signal B1 is sufficiently large, allowing the sweep signal sweep to have a longer operating time.

[0036] In some implementations... Figure 5 A schematic diagram of a pixel circuit provided in an embodiment of the present invention is shown in the figure. Figure 5 As shown, the pixel circuit includes a first driving circuit PAM and a second driving circuit PWM. The first driving circuit PAM is configured to control the amplitude of the driving current supplied to the sub-pixel based on the first data voltage PAM-Data, and the second driving circuit PWM is configured to control the duration of the driving current supplied to the sub-pixel based on the second data voltage PWM-Data. Figure 5 The sub-pixels include light-emitting devices (LEDs).

[0037] The first driving circuit PAM includes a first driving transistor T7, a first gate reset transistor T8, a first data write transistor T9, a first compensation transistor T10, a first control transistor T11, a second control transistor T12, an electrode reset transistor T13, and a first storage capacitor C20. The first storage capacitor C20 is the storage capacitor in the first driving circuit PAM. The first driving transistor T7 is connected in series between the first control transistor T11 and the second control transistor T12. The first control transistor T11 is connected between the first power supply voltage PAM-Vdd and the first terminal of the second driving transistor T7. The second control transistor T12 is connected between the second terminal of the first driving transistor T7 and the light-emitting device LED. The first driving transistor T7 is configured to generate a driving current under the control of its gate voltage. The first data write transistor T9 is connected to the first terminal of the first driving transistor T7. The first compensation transistor T10 is connected to the second terminal of the first driving transistor T7 and the control terminal. The first gate reset transistor T8 is connected to the control terminal (i.e., the gate) of the first driving transistor T7. The first plate of the first storage capacitor C20 is connected to the gate of the first driving transistor T7, and the second plate of the first storage capacitor C20 is connected to the first power supply voltage PAM-vdd. The electrode reset transistor T13 is connected to the first electrode of the light-emitting device LED, and the second control transistor T12 is also connected to the first electrode of the light-emitting device LED. The second electrode of the light-emitting device LED is connected to the third power supply voltage VEE. The gate of the first gate reset transistor T8 is connected to the first scan signal PAM-S1; the gates of the first data write transistor T9, the first compensation transistor T10, and the electrode reset transistor T13 are connected to the second scan signal PAM-S2. The control terminal of the first control transistor T11 and / or the control terminal of the second control transistor T12 receives the first control signal PAM-EM. Additionally... Figure 5 The diagram illustrates that the first terminal of the electrode reset transistor T13 receives the third power supply voltage VEE, and the second terminal is connected to the first electrode of the light-emitting device LED. In other embodiments, the first terminal of the electrode reset transistor T13 may receive a reset signal PAM-REF or a constant voltage signal PAM-INIT.

[0038] The second driving circuit PWM includes a second driving transistor T1, a second gate reset transistor T2, a second data write transistor T3, a second compensation transistor T4, a third control transistor T5, a fourth control transistor T6, and a second storage capacitor C10. The third control transistor T5 is connected between the second power supply voltage PWM-Vdd and the first terminal of the second driving transistor T1. The fourth control transistor T6 is connected between the second terminal of the second driving transistor T1 and the gate of the first driving transistor T7. The second data write transistor T3 is connected to the first terminal of the second driving transistor T1. The second compensation transistor T4 is connected to the second terminal and the gate of the second driving transistor T1. The second gate reset transistor T2 is connected to the gate of the second driving transistor T1, and its gate is connected to the third scan signal PWM-S1. The gates of the second data write transistor T3 and the second compensation transistor T4 are connected to the fourth scan signal PWM-S2. The gates of the third control transistor T5 and the fourth control transistor T6 are connected to the second control signal PWM-EM.

[0039] Figure 5 illustrates that the output terminal of the second driving circuit PWM (i.e., the output terminal of the fourth control transistor T6) is connected to the gate of the first driving transistor T7. In another embodiment, the output terminal of the second driving circuit PWM is connected to the gate of the second control transistor T12, which is not illustrated in the figure here. In another embodiment, an additional light emission duration control transistor is provided on the light emission path of the first driving circuit PAM, such as in... Figure 5 A light-emitting duration control transistor is connected in series between the second control transistor T12 and the light-emitting device LED, and the output terminal of the second driving circuit PWM is connected to the gate of the light-emitting duration control transistor.

[0040] Figure 6 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. (In conjunction with...) Figure 6 Looking at the first driving circuit PAM, during the reset phase t21, the first scan signal PAM-S1 provides a low level to control the first gate reset transistor T8 to turn on, and the gate of the first driving transistor T7 is reset using the reset signal PAM-REF. During the write phase t22, the second scan signal PAM-S2 provides a low level to control the first data write transistor T9 and the first compensation transistor T10 to turn on, writing the first data voltage PAM-Data to the gate of the first driving transistor T7. During the light emission phase t23, the first control signal PAM-EM provides a low level to control the first control transistor T11 and the second control transistor T12 to turn on, and the first driving transistor T7 generates a driving current to supply the light-emitting device LED.

[0041] For the second driving circuit PWM, in the reset phase t21, the third scan signal PWM-S1 provides a low level to control the second gate reset transistor T2 to turn on, and the gate of the second driving transistor T1 is reset using the reset signal PWM-REF. In the writing phase t22, the fourth scan signal PWM-S2 provides a low level to control the second data writing transistor T3 and the second compensation transistor T4 to turn on, writing the second data voltage PWM-Data to the gate of the second driving transistor T1. In the light-emitting phase t23, the second control signal PWM-EM provides a low level to control the third control transistor T5 and the fourth control transistor T6 to turn on. As the voltage on the sweep signal gradually changes, the gate voltage of the second driving transistor T1 gradually changes due to the coupling effect of the second storage capacitor C10. When the gate voltage of the second driving transistor T1 changes to the point that the second driving transistor T1 reaches the turn-on state, the current generated by the second driving transistor T1 will cause a change in the gate voltage of the first driving transistor T7 until the first driving transistor T7 is turned off. Thus, the first driving circuit PAM stops providing driving current to the light-emitting device LED, that is, the duration of providing driving current is controlled by the second driving circuit PWM.

[0042] like Figure 6 As shown, during the operation of the pixel circuit, the effective level period of the first control signal PAM-EM does not coincide with the second ramp signal B2 in the sweep signal. That is, during the second ramp signal B2 period of the sweep signal, the first control signal PAM-EM is ineffective. During this period, the first control transistor T11 and the second control transistor T12 are in the off state. Therefore, the second ramp signal B2 in the sweep signal does not cause the first driving circuit PAW to provide driving current, and thus does not affect the duration of driving current provided by the pixel circuit.

[0043] In some implementations, such as Figure 6 As shown, the first ramp signal B1 in the sweep signal appears earlier than the second ramp signal B2. During the operation of the pixel circuit, the end time of the effective level in the first control signal PAM-EM is no later than the start time of the second ramp signal B2. This ensures that the effective level period of the first control signal PAM-EM does not overlap with the second ramp signal B2 in the sweep signal, and that the effective level period of the first control signal PAM-EM overlaps with the first ramp signal B1, guaranteeing a reasonable and full utilization of the operating time of the first ramp signal B1 in the sweep signal.

[0044] like Figure 6As shown, in the operation of the pixel circuit, the starting time of the first ramp signal B1 is earlier than the starting time of the effective level in the first control signal PAM-EM, that is, earlier than the falling edge of the first control signal PAM-EM. Such a setting can ensure that the sub-pixel can have a dark state of non-emission, meeting the requirements for the gray-scale setting of the sub-pixel. Based on the working principle of the pixel circuit, it can be known that the duration of the light-emitting current is controlled by the second data voltage PWM-Data, that is, the actual light-emitting duration is controlled. The maximum value in the preset value range of the second data voltage PWM-Data controls the maximum light-emitting time of the light-emitting device LED, and the minimum value controls the minimum light-emitting time of the light-emitting device LED, that is, makes the light-emitting device LED not emit light. To ensure that the light-emitting device LED can have a non-emitting state, it is required that when the minimum value of the second data voltage PWM-Data is written into the second driving circuit PWM, the sweep signal sweep changes to a state that can make the second driving transistor T1 in the second driving circuit PWM reach the on state within a certain time period range. When the second driving transistor T1 is already in the on state, the gate voltage of the first driving transistor T7 in the first driving circuit PAM has been pulled up to make the driving transistor in the off state. Even if the first control signal PAM-EM is at the effective level, no driving current will be generated, thereby making the light-emitting device LED in the dark state.

[0045] As Figure 6 shown, in the operation of the pixel circuit, the duration between the starting time of the first ramp signal B1 and the starting time of the effective level in the first control signal PAM-EM is t1, and the duration between the starting time of the effective level in the first control signal PAM-EM and the ending time of the first ramp signal B1 is t2, where t1 < t2. Such a setting not only ensures that the sub-pixel has a dark state of non-emission, but also makes the duration available for regulating the gray-scale display of the sub-pixel long enough to achieve more precise gray-scale regulation.

[0046] In some embodiments, t1 ≥ H. That is, the minimum value of t1 is one line time H. The setting of t1 needs to consider the adjustable values of the slope of the sweep signal sweep and the minimum value of the second data voltage PWM-Data. By coordinating the slope of the sweep signal sweep with t1, the second driving transistor T1 in the second driving circuit PWM can reach the on state within the t1 time period.

[0047] In some embodiments, H < t2 ≤ (n - 2) H + A. Such a setting makes the overlapping time between the effective level in the first control signal PAM-EM and the first ramp signal B1 long enough, enabling full utilization of the working time of the first ramp signal B1, ensuring complete cut-off of the light-emitting path, and making the gray-scale regulation more precise, improving the display effect.

[0048] In some implementations, the effective level period in the first control signal PAM-EM may partially overlap with the constant voltage signal period between the first ramp signal B1 and the second ramp signal B2. The width of the effective level in the first control signal PAM-EM is (n-1). H. For example, when n=6, the width of the first ramp signal B1 is 5. H+A, the width of the effective level in the first control signal PAM-EM is 5. H. The width of the effective level in the first control signal PAM-EM can be matched with the width of the first ramp signal B1 to ensure that the working time of the first ramp signal B1 is fully utilized, making grayscale control more precise.

[0049] In some implementations... Figure 7 This is another signal timing diagram provided in an embodiment of the present invention. Figure 7 The diagram illustrates the timing of several control signals required for the display panel. Specifically, in the first-stage shift register unit 10, the input terminal IN of the drive module 11 receives the start signal STV, and the effective level width of the output signal OUT of the drive module 11 is affected by the input signal IN. As can be seen from the above description of the embodiment, the effective level of the output signal OUT of the drive module 11 controls the sweep frequency control signal sweep-in output by the gating module 12 as the sweep frequency signal sweep. Figure 7 As can be seen, in this embodiment of the invention, the width of the effective level in the start signal STV is set to be greater than the width of the effective level in the first control signal PAM-EM. This enables the width of the first ramp signal B1 in the sweep signal to match the width of the effective level in the first control signal PAM-EM, thereby increasing the working time of the sweep signal.

[0050] In some implementations, such as Figure 5 As shown, in the second drive circuit PWM, the control terminal of the third control transistor T5 and / or the control terminal of the fourth control transistor T6 receive the second control signal PWM-EM. Combined with... Figure 6 As can be seen from the timing diagram, during the operation of the pixel circuit, the width of the effective level in the second control signal PWM-EM is greater than the width of the effective level in the first control signal PAM-EM. This setting allows the second driving transistor T1 to be turned on at any point in time when the first control signal PAM-EM provides an effective level, thereby controlling the gate voltage change of the first driving transistor T7 in the first driving circuit PAM and achieving control over the duration of the driving current provided.

[0051] like Figure 6As shown, in the operation of the pixel circuit, the start time of the effective level in the second control signal PWM-EM is earlier than the start time of the effective level in the first control signal PAM-EM. This setting enables the second control signal PWM-EM to cooperate with the first ramp signal B1. When the minimum value of the second data voltage PWM-Data is written into the second driving circuit PWM, the sweep signal sweep changes within a certain time range to enable the second driving transistor T1 to turn on, thereby pulling up the gate voltage of the first driving transistor T7 in the first driving circuit PAM, making the driving transistor turn off. Even if the first control signal PAM-EM is effective later, no driving current will be generated, making the light-emitting device LED dark.

[0052] like Figure 6 As shown, in the operation of the pixel circuit, the end time of the effective level in the second control signal PWM-EM is later than the end time of the effective level in the first control signal PAM-EM. This setting allows the second driving transistor T1 to be turned on at any point in time when the first control signal PAM-EM provides an effective level, thereby controlling the gate voltage change of the first driving transistor T7 in the first driving circuit PAM and realizing the control of the duration of the driving current provided.

[0053] In some implementations, such as Figure 6 As shown, during the operation of the pixel circuit, the width of the effective level in the second control signal PWM-EM is greater than the sum of the widths of the first ramp signal B1 and the second ramp signal B2 in the sweep signal. The width of the effective level in the second control signal PWM-EM is set to be sufficiently large to ensure that it can match the operating duration of the sweep signal, thus making full and reasonable use of the sweep signal's operating time.

[0054] In some implementations... Figure 8 This is another signal timing diagram provided in an embodiment of the present invention. In this embodiment, the period of the sweep frequency control signal sweep-in is n. H. The display panel includes n sweep frequency control signal lines, meaning the number of sweep frequency control signal lines is the same as the number of cycles of the sweep frequency control signal sweep-in. Each sweep frequency control signal line (sweep-in) provides a sweep frequency control signal (sweep-in), and the sweep frequency control signal line (sweep-in) uses the same marking as the sweep frequency control signal it provides. The n sweep frequency control signal lines (sweep-in) are sequentially arranged as sweep-in1, sweep-in2, up to sweep-inn, with the start time of the cycle of the sweep frequency control signal provided by two adjacent sweep frequency control signal lines (sweep-in) differing by H. Figure 8 The diagram uses n=6 as an example.

[0055] In this embodiment of the invention, the gating module 12 in the j-th level shift register unit 10 and the n-th level shift register unit 10 are... In the m+j level shift register unit 10, the gating module 12 is connected to the j-th sweep frequency control signal line sweep-in, where j and m are integers, 1≤j≤n, 1≤m≤(N / n)-1. For example, when n=6, the gating module 12 in the first level shift register unit 10 and the gating module 12 in the seventh level shift register unit 10 are connected to the first sweep frequency control signal line sweep-in1. In this embodiment of the invention, n sweep frequency control signal lines sweep-in are set in the display panel, and the number of levels of the shift register units 10 connected to the sweep frequency control signal lines sweep-in are set. Multiple sweep frequency control signals sweep-in can be output sequentially through the multi-level shift register units 10 to achieve row-by-row driving of multiple pixel circuit rows.

[0056] Based on the same inventive concept, embodiments of the present invention provide a display device. Figure 9 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 9 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, a mobile phone, tablet, television, smart billboard, or a splicing display device, etc.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The system includes a shift register comprising N cascaded shift register units. Each shift register unit includes a driver module and a gating module. One control terminal of the gating module is connected to the output terminal of the driver module. The output terminal of the driver module in the i-th stage shift register unit is connected to the input terminal of the driver module in the (i+1)-th stage shift register unit. i and N are integers, where 1 ≤ i <N; The gating module is configured to receive at least the signal output by the driving module and the frequency sweep control signal, and output a frequency sweep signal; the frequency sweep control signal and the frequency sweep signal each include a ramp signal, and the period of the frequency sweep control signal is n. H is the scan time of one row of pixels, and n is an integer, n≥2; wherein, in the period of the sweep frequency control signal, the width of the ramp signal in the sweep frequency control signal is (n-1). H+A, 0 <A<H。 2. The display panel according to claim 1, characterized in that, The input terminal of the driving module in the shift register unit of the first stage receives a start signal, wherein the width of the effective level in the start signal is t0, and t0≥(n-1). H+A.

3. The display panel according to claim 2, characterized in that, If n is even, then t0 = (n+1) H.

4. The display panel according to claim 1, characterized in that, The ramp signal in the frequency sweep signal includes a first ramp signal and a second ramp signal, and the width of the first ramp signal is (n-1). H+A, the width of the second ramp signal is smaller than the width of the first ramp signal.

5. The display panel according to claim 4, characterized in that, The width of the second ramp signal is less than H.

6. The display panel according to claim 4, characterized in that, The display panel includes a pixel circuit, which includes a first driving circuit and a second driving circuit. The first driving circuit is configured to control the amplitude of the driving current supplied to the sub-pixel based on a first data voltage, and the second driving circuit is configured to control the duration of the driving current supplied to the sub-pixel based on a second data voltage. The output of the gating module is connected to the second driving circuit; The first driving circuit includes a first driving transistor, a first control transistor, and a second control transistor, wherein the first driving transistor is connected in series between the first control transistor and the second control transistor; the control terminal of the first control transistor and / or the control terminal of the second control transistor receives a first control signal. During the operation of the pixel circuit, the effective level period of the first control signal does not coincide with the second ramp signal.

7. The display panel according to claim 6, characterized in that, During the operation of the pixel circuit, the end time of the effective level in the first control signal is no later than the start time of the second ramp signal.

8. The display panel according to claim 6, characterized in that, During the operation of the pixel circuit, the start time of the first ramp signal is earlier than the start time of the effective level in the first control signal.

9. The display panel according to claim 8, characterized in that, In the operation of the pixel circuit, the duration between the start time of the first ramp signal and the start time of the effective level in the first control signal is t1, and the duration between the start time of the effective level in the first control signal and the end time of the first ramp signal is t2, where t1 < t2.

10. The display panel according to claim 9, characterized in that, t1≥H.

11. The display panel according to claim 9, characterized in that, H<t2≤(n-2) H+A。 12. The display panel according to claim 6, characterized in that, The width of the effective level in the first control signal is (n-1). H.

13. The display panel according to claim 6, characterized in that, The input terminal of the drive module in the first-level shift register unit receives the start signal; The width of the active level in the start signal is greater than the width of the active level in the first control signal.

14. The display panel according to claim 6, characterized in that, The second driving circuit includes a second driving transistor, a third control transistor, and a fourth control transistor, with the second driving transistor connected in series between the third control transistor and the fourth control transistor; the control terminal of the third control transistor and / or the control terminal of the fourth control transistor receive a second control signal; During the operation of the pixel circuit, the width of the effective level in the second control signal is greater than the width of the effective level in the first control signal.

15. The display panel according to claim 14, characterized in that, During the operation of the pixel circuit, the start time of the effective level in the second control signal is earlier than the start time of the effective level in the first control signal.

16. The display panel according to claim 14, characterized in that, During the operation of the pixel circuit, the end time of the effective level in the second control signal is later than the end time of the effective level in the first control signal.

17. The display panel according to claim 6, characterized in that, The second driving circuit includes a second driving transistor, a third control transistor, and a fourth control transistor, with the second driving transistor connected in series between the third control transistor and the fourth control transistor; the control terminal of the third control transistor and / or the control terminal of the fourth control transistor receive a second control signal; During the operation of the pixel circuit, the width of the effective level in the second control signal is greater than the sum of the widths of the first ramp signal and the second ramp signal in the frequency sweep signal.

18. The display panel according to claim 1, characterized in that, The display panel includes n sweep frequency control signal lines, which provide the sweep frequency control signal; the n sweep frequency control signal lines include the first sweep frequency control signal line, the second sweep frequency control signal line, and so on, arranged in sequence, and the start time of the period of the sweep frequency control signal provided by two adjacent sweep frequency control signal lines differs by H. Among them, the gating module in the j-th level shift register unit and the n-th level The gating module in the shift register unit of level m+j is connected to the j-th sweep frequency control signal line, where j and m are integers, 1≤j≤n, and 1≤m≤(N / n)-1.

19. The display panel according to claim 1, characterized in that, The driving module includes a first transistor and a second transistor. The control terminal of the first transistor is connected to a first node, and the control terminal of the second transistor is connected to a second node. Under the control of the potential of the first node, the first transistor provides a first voltage signal to the output terminal of the driving module, and under the control of the potential of the second node, the second transistor provides a second voltage signal to the output terminal of the driving module. The gating module includes a third transistor and a fourth transistor. The control terminal of the third transistor is connected to the output terminal of the driving module, and the control terminal of the fourth transistor is connected to the first node. The first terminal of the third transistor receives the frequency sweep control signal, the first terminal of the fourth transistor receives the third voltage signal, and the second terminals of the third transistor and the second terminal of the fourth transistor are connected to the output terminal of the gating module.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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