A semiconductor manufacturing method
By setting a silicon coating and applying a reverse voltage during dry etching, the low-frequency power of the lower electrode is reduced, thus solving the problem of sidewall stripes during the etching of the hard mask layer and achieving smooth hard mask layer sidewalls and good material filling effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU FULLSEMI SEMICON CO LTD
- Filing Date
- 2024-12-09
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, sidewall stripe morphology is easily generated during the etching process of hard mask layers, which leads to incomplete material filling in subsequent processes and affects the electrical parameters of devices.
During the dry etching process, a silicon coating is applied and a reverse voltage is applied to form a protective layer to protect the patterned photoresist layer. At the same time, the low-frequency power of the lower electrode is reduced to decrease the free energy and bombardment intensity of the plasma, thereby avoiding photoresist layer loss and the generation of sidewall stripes in the hard mask layer.
It effectively protects the photoresist layer, avoids the generation of sidewall stripes in the hard mask layer, ensures complete material filling in subsequent processes, and improves the electrical parameters of the device.
Smart Images
Figure CN119650427B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a semiconductor process method. Background Technology
[0002] SI-CAP (silicon capacitor) operates at 5V. Its size after photoresist exposure is smaller than other products. Therefore, when etching the hard mask layer using the exposed photoresist as a mask, plasma energy bombardment easily damages the right-angled top of the photoresist and causes pitting and striped morphology on the sides. After etching the hard mask layer, as... Figure 1 As shown, measurements of key dimensions reveal that the sidewall A of the hard mask layer 11 exhibits an uneven stripe morphology, and the FA (failure analysis) cross-section results also show numerous stripe patterns on the sidewalls. The presence of sidewall stripes can lead to the formation of the same stripe morphology when etching the layer to be etched using the hard mask layer as a mask. This can result in incomplete material filling during subsequent processes when filling oxide layers or other substances, affecting the electrical parameters of the device.
[0003] Current methods involve etching using a traditional approach of high power and low pressure to open the hard mask layer. This method primarily relies on the high mean free energy of ions to penetrate the hard mask at high speed through strong, low-frequency power. However, this etching method results in deep, difficult-to-eliminate streaks on the sidewalls caused by the high-speed downward bombardment of ions. Furthermore, it tends to generate significant amounts of polymer, especially at low exposure rates, where the polymer adheres to the sidewall surface and is difficult to remove, further complicating the streak removal process.
[0004] Therefore, how to reduce or avoid the formation of stripe morphology on the sidewalls when etching hard mask layers to form trenches is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a semiconductor process method to solve the problem of stripe morphology in the etching process of hard mask layers in the prior art.
[0006] To address the aforementioned technical problems, this invention provides a semiconductor process method, comprising the following steps:
[0007] A hard mask layer and a patterned photoresist layer are sequentially formed on the layer to be etched.
[0008] Using the patterned photoresist layer as a mask, a dry etching process is employed to etch the hard mask layer to form trenches exposing the layer to be etched; wherein,
[0009] In the dry etching process, a silicon coating is placed in the reaction chamber, a DC voltage is applied to the silicon coating and the silicon coating is subjected to a reverse voltage, and the silicon coating is bombarded by plasma to release silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer to protect the patterned photoresist layer.
[0010] Optionally, in the dry etching process, the low-frequency power of the lower electrode is less than or equal to 3000W.
[0011] Optionally, in the dry etching process, the low-frequency power of the lower electrode is between 1000W and 3000W.
[0012] Optionally, in the dry etching process, the pressure in the reaction chamber is between 10mT and 100mT, and the low-frequency power of the upper electrode is between 250W and 800W.
[0013] Optionally, the voltage applied to the silicon coating is between 100V and 400V.
[0014] Optionally, in the dry etching process, the reaction gas includes an etching gas and a dilution gas. The etching gas includes at least one of CF4, CH2F2, CHF3, or C4F8, and the dilution gas includes N2 or Ar.
[0015] Optionally, the flow rate of the reactant gas is between 5 sccm and 1500 sccm.
[0016] Optionally, the reactant gas may also include O2.
[0017] Optionally, O2 is introduced into the reaction chamber through two pipes, with the flow rate of O2 in the first pipe between 5 sccm and 30 sccm, and the flow rate of O2 in the second pipe between 5 sccm and 200 sccm.
[0018] Optionally, the material of the hard mask layer comprises silicon dioxide, and the material of the layer to be etched comprises silicon.
[0019] Compared with the prior art, the technical solution of the present invention has at least the following technical effects:
[0020] In the semiconductor process method provided by this invention, a patterned photoresist layer is used as a mask. During the process of dry etching the hard mask layer to form trenches exposing the layer to be etched, a silicon coating is placed in the reaction chamber. A DC voltage is applied to the silicon coating, and the silicon coating is subjected to a reverse voltage. The silicon coating is bombarded by ions, releasing silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer. Silicon is denser than photoresist, which can effectively protect the patterned photoresist layer and prevent it from being damaged during dry etching. At the same time, the electrons released by the silicon coating modify and harden the patterned photoresist layer to resist the consumption of the apex corners of the patterned photoresist layer by high-energy bombardment. This allows the patterned photoresist layer to effectively protect the hard mask layer below it, thereby avoiding the generation of trench sidewall stripes.
[0021] In addition, in dry etching, the low-frequency power of the lower electrode is less than or equal to 3000W. Compared with the existing technology, the low-frequency power of the lower electrode is reduced, thereby reducing the free energy of the plasma and the intensity of bombardment of the hard mask layer. This can reduce the rate and distribution range of polymer generation and reduce the loss at the top corner of the patterned photoresist layer, thereby further avoiding the generation of trench sidewall stripes. Attached Figure Description
[0022] Figure 1 This is a magnified micrograph of the striped morphology formed on the sidewalls after dry etching of a hard mask layer in existing technology.
[0023] Figure 2 This is a schematic flowchart of a semiconductor process method provided in an embodiment of the present invention.
[0024] Figures 3 to 5 This is a schematic diagram of the steps of a semiconductor process method provided in an embodiment of the present invention.
[0025] Figure 6 This is a magnified micrograph of the structure with smooth sidewalls after dry etching of the hard mask layer in the semiconductor process method of this application.
[0026] Explanation of reference numerals in the attached figures:
[0027] 10-Layer to be etched; 11-Hard mask layer; 12-Patterned photoresist layer; 13-Trench; 14-Silicon coating; 15-Protective layer. Detailed Implementation
[0028] To address the aforementioned technical problems, this invention provides a semiconductor process method. Using a patterned photoresist layer as a mask, during the dry etching process of the hard mask layer to form trenches exposing the layer to be etched, a silicon coating is placed in the reaction chamber. A DC voltage is applied to the silicon coating, and the voltage applied is reversed. The silicon coating is bombarded by ions, releasing silicon that adheres to the upper surface of the patterned photoresist layer, forming a protective layer. Silicon is denser than photoresist, effectively protecting the patterned photoresist layer and preventing damage during dry etching. Simultaneously, the electrons released from the silicon coating modify and harden the patterned photoresist layer, resisting the high-energy bombardment's impact on the apex corners of the patterned photoresist layer. This allows the patterned photoresist layer to effectively protect the underlying hard mask layer, thereby preventing the formation of trench sidewall streaks.
[0029] In addition, in dry etching, the low-frequency power of the lower electrode is less than or equal to 3000W. Compared with the existing technology, the low-frequency power of the lower electrode is reduced, thereby reducing the free energy of the plasma and the intensity of bombardment of the hard mask layer. This can reduce the rate and distribution range of polymer generation and reduce the loss at the top corner of the patterned photoresist layer, thereby further avoiding the generation of trench sidewall stripes.
[0030] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of the invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0031] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0032] Figure 2 This is a schematic flowchart of a semiconductor process method provided in an embodiment of the present invention. Figure 2 As shown, the semiconductor process method provided in this embodiment includes the following steps:
[0033] S1: A hard mask layer and a patterned photoresist layer are sequentially formed on the layer to be etched;
[0034] S2: Using the patterned photoresist layer as a mask, a dry etching process is used to etch the hard mask layer to form trenches that expose the layer to be etched; wherein, in the dry etching, a silicon coating is placed in the reaction chamber, a DC voltage is applied to the silicon coating and the silicon coating is subjected to a reverse voltage, and the silicon coating is bombarded by plasma to release silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer to protect the patterned photoresist layer.
[0035] Figures 3 to 5 This is a schematic diagram of the structural steps of a semiconductor process method provided in an embodiment of the present invention. Next, we will combine... Figure 2 , Figures 3 to 5 The semiconductor process method provided in the embodiments of the present invention will be described in detail.
[0036] In step S1, please refer to Figure 3 As shown, a hard mask layer 11 and a patterned photoresist layer 12 are sequentially formed on the layer to be etched 10.
[0037] In this embodiment, a hard mask layer 11 and a photoresist layer (not shown) are sequentially formed on the layer to be etched 10. Then, the photoresist layer is exposed and developed to form a patterned photoresist layer 12.
[0038] In one embodiment of the present invention, an anti-reflection layer (not shown) is further disposed between the hard mask layer 11 and the patterned photoresist layer 12 to reduce light reflection during photolithography. Specifically, during photolithography of the photoresist layer, light reflection may occur on the surface of the hard mask layer 11. When light shines on the surface of the hard mask layer 11, part of the light is reflected, while the rest penetrates the hard mask layer 11 and enters the surface of the underlying etchable layer 10. The light reflected from the hard mask layer 11 and the etchable layer 10 will be reflected back to the photoresist layer, potentially causing overexposure of the photoresist layer and resulting in problems such as blurring and distortion of the final etched pattern. To avoid this situation, an anti-reflection layer is formed between the hard mask layer 11 and the photoresist layer. The anti-reflection layer can absorb or interfere with the reflected light to reduce light reflection during photolithography. The anti-reflection layer can be an organic anti-reflection layer or an inorganic anti-reflection layer.
[0039] In this embodiment, the layer to be etched 10 can be any layer that needs to be etched. For example, the layer to be etched 10 can be a substrate, such as a silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate substrate, or a silicon-on-insulator substrate or a germanium-on-insulator substrate. The layer to be etched 10 can also be an epitaxial layer formed on a substrate, and the present invention does not limit this.
[0040] The hard mask layer 11 is made of silicon dioxide, but is not limited to it. The hard mask layer 11 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. For example, in this embodiment, the thickness of the hard mask layer 11 is, for example, 3.5 μm, and the thickness of the patterned photoresist layer 12 is, for example, 2.4 μm.
[0041] In step S2, please refer to Figure 5 As shown, using the patterned photoresist layer 12 as a mask, a dry etching process is employed to etch the hard mask layer 11 to form trenches 13 exposing the layer 10 to be etched; wherein, in the dry etching process, please refer to... Figure 4 As shown, a silicon coating 14 is disposed in the reaction chamber. A DC voltage is applied to the silicon coating 14, which is a reverse voltage. The silicon coating 14 is bombarded by plasma, releasing silicon that adheres to the upper surface of the patterned photoresist layer 12 to form a protective layer 15 to protect the patterned photoresist layer 12. At the same time, the silicon coating 14 releases electrons, causing the patterned photoresist layer 12 to be modified and hardened.
[0042] In this embodiment, a dry etching process is used to etch the hard mask layer 11 through the upper surface of the patterned photoresist layer 12 to form a trench 13 in the hard mask layer 11, and the trench 13 exposes the layer 10 to be etched.
[0043] During dry etching, a silicon coating 14 is placed in the reaction chamber. A DC voltage is applied to the silicon coating 14, and the voltage is reversed, meaning the silicon coating 14 is connected to the negative terminal of the DC power supply, while the positive terminal of the DC power supply is grounded. The silicon coating 14 is subjected to a reverse voltage, and the dissociated plasma (such as...) in the reaction chamber... Figure 4 The plasma (+) is attracted to the silicon coating 14 and bombards the silicon coating 14, after which the silicon coating 14 releases silicon (e.g., Figure 4 The silicon coating 14 (as in the photoresist layer 12) forms a protective layer 15 on the upper surface of the patterned photoresist layer 12. Silicon is denser than photoresist, effectively protecting the patterned photoresist layer 12 and preventing it from being damaged during dry etching. Simultaneously, the silicon coating 14 releases electrons (such as...). Figure 4 ions e in -This process modifies and hardens the patterned photoresist layer 12 to resist the consumption of the apex corner (i.e. the angle formed by the top surface and the sidewall in the patterned photoresist layer 12) by high-energy bombardment, so that the patterned photoresist layer 12 can effectively protect the hard mask layer 11 below it, thereby avoiding the generation of stripes on the sidewall of the hard mask layer 11 (i.e. the sidewall of the trench 13).
[0044] In one embodiment of the present invention, the voltage applied to the silicon coating 14 is between 100V and 400V, but is not limited to this.
[0045] In one embodiment of the present invention, the low-frequency power of the lower electrode is less than or equal to 3000W during the dry etching process. Compared with the prior art, the present invention reduces the low-frequency power of the lower electrode, thereby reducing the free energy of the plasma and the intensity of bombardment of the hard mask layer 11. This reduces the rate and distribution range of polymer generation and the loss at the apex of the patterned photoresist layer 12, further preventing the generation of sidewall stripes in the trench 13. Furthermore, the reduction in the low-frequency power of the lower electrode in the present invention extends the lifespan of the components within the cavity to some extent.
[0046] In one embodiment of the present invention, in the dry etching, the pressure in the reaction chamber is between 10mT and 100mT, the low-frequency power of the upper electrode is between 250W and 800W, and the low-frequency power of the lower electrode is between 1000W and 3000W, but it is not limited to these.
[0047] In one embodiment of the present invention, in the dry etching process, the reaction gas includes an etching gas and a dilution gas. The etching gas includes at least one of CF4, CH2F2, CHF3, or C4F8, but is not limited to these. The etching gas is ionized into plasma, which reacts chemically with the hard mask layer 11 to produce volatile products, thereby removing the etched hard mask layer 11. The dilution gas includes N2 or Ar, used to dilute the etching gas to adjust the gas concentration in the reaction chamber, thereby controlling the etching rate and uniformity. The flow rate of the reaction gas is between 5 sccm and 1500 sccm, but is not limited to this, and can be determined according to the actual etching conditions and process conditions.
[0048] The reactive gas also includes O2. During the dry etching process, O2 is introduced to better purge the polymer away from the etched sidewalls, reducing the stripe morphology caused by plasma bombardment of the polymer on the sidewalls and resulting in a smooth sidewall morphology within the hard mask layer 11. For example, O2 is introduced into the reaction chamber through two pipes: the flow rate of O2 in the first pipe is between 5 sccm and 30 sccm, and the flow rate of O2 in the second pipe is between 5 sccm and 200 sccm.
[0049] Figure 6 This is a magnified micrograph of the structure with smooth sidewalls after dry etching of the hard mask layer in the semiconductor process described in this application. Please refer to... Figure 6 As shown, using the semiconductor process method described in this invention, a smooth sidewall morphology B is obtained after dry etching of the hard mask layer 11.
[0050] In one embodiment of the present invention, when an anti-reflection layer is provided between the hard mask layer 11 and the patterned photoresist layer 12, the anti-reflection layer above the hard mask layer 11 to be etched is removed before etching the hard mask layer 11.
[0051] It should be noted that the protective layer 15 formed on the patterned photoresist layer 12 is inevitably etched during the dry etching process. Simultaneously, silicon is continuously released from the silicon coating 14 and adheres to the upper surface of the patterned photoresist layer 12, forming the protective layer 15. At the end of the dry etching process, the protective layer 15 on the patterned photoresist layer 12 may be removed, resulting in a layer as shown below. Figure 5 The structure shown may also include a partial thickness of the protective layer 15 on the patterned photoresist layer 12. The protective layer 15 can be removed at the same time as the patterned photoresist layer 12, and the protective layer 15 will not affect the subsequent process.
[0052] In one embodiment of the present invention, after forming the trench 13 exposing the layer 10 to be etched within the hard mask layer 11, the method further includes using the hard mask layer 11 as a mask to etch the layer 10 to be etched to form the trench, and then filling the trench with an oxide layer or other substances. Since the sidewalls of the hard mask layer 11 are smooth and without stripe morphology, no stripe morphology will appear on the sidewalls when the layer 10 to be etched is etched using the hard mask layer 11 as a mask, thereby avoiding the problem of incomplete filling in the subsequent filling process and avoiding affecting the electrical parameters of the device.
[0053] In one embodiment of the present invention, when the hard mask layer 11 is used as a mask to etch the layer 10 to be etched to form a trench, the semiconductor process method described in the present invention can also be used to etch the layer 10 to be etched. However, different adaptive adjustments need to be made to the process parameters of dry etching and the etching gas to achieve the etching effect of the layer 10 to be etched.
[0054] Of course, the patterned photoresist layer 12 can be removed before etching the layer 10 to be etched using the hard mask layer 11 as a mask, or the patterned photoresist layer 12 can be removed after etching the layer 10 to be etched.
[0055] In summary, in the semiconductor process provided by this invention, during the process of dry etching a hard mask layer to form trenches exposing the layer to be etched, using a patterned photoresist layer as a mask, a silicon coating is placed in the reaction chamber. A DC voltage is applied to the silicon coating, and the silicon coating is subjected to a reverse voltage. The silicon coating is bombarded by ions, releasing silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer. Silicon is denser than photoresist, which can effectively protect the patterned photoresist layer and prevent it from being damaged during dry etching. At the same time, the electrons released by the silicon coating modify and harden the patterned photoresist layer to resist the consumption of the apex corners of the patterned photoresist layer by high-energy bombardment. This allows the patterned photoresist layer to effectively protect the hard mask layer underneath, thereby preventing the generation of trench sidewall stripes.
[0056] In addition, in dry etching, the low-frequency power of the lower electrode is less than or equal to 3000W. Compared with the existing technology, the low-frequency power of the lower electrode is reduced, thereby reducing the free energy of the plasma and the intensity of bombardment of the hard mask layer. This can reduce the rate and distribution range of polymer generation and reduce the loss at the top corner of the patterned photoresist layer, thereby further avoiding the generation of trench sidewall stripes.
[0057] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A semiconductor manufacturing method, characterized in that, Includes the following steps: A hard mask layer and a patterned photoresist layer are sequentially formed on the layer to be etched. Using the patterned photoresist layer as a mask, a dry etching process is employed to etch the hard mask layer to form trenches exposing the layer to be etched; wherein, In the dry etching process, a silicon coating is placed in the reaction chamber. A DC voltage is applied to the silicon coating, and the silicon coating is subjected to a reverse voltage. The silicon coating is bombarded by plasma, releasing silicon that adheres to the upper surface of the patterned photoresist layer to form a protective layer to protect the patterned photoresist layer. At the same time, the silicon coating releases electrons, which modifies and hardens the patterned photoresist layer. The protective layer formed on the patterned photoresist layer is etched during dry etching, while silicon is continuously released from the silicon coating and adheres to the surface of the patterned photoresist layer to form a protective layer.
2. The semiconductor manufacturing method according to claim 1, characterized in that, In the dry etching process, the low-frequency power of the lower electrode is less than or equal to 3000W.
3. The semiconductor manufacturing method according to claim 2, characterized in that, In the dry etching process, the low-frequency power of the lower electrode is between 1000W and 3000W.
4. The semiconductor manufacturing method according to claim 1, characterized in that, In the dry etching process, the pressure in the reaction chamber is between 10mT and 100mT, and the low-frequency power of the upper electrode is between 250W and 800W.
5. The semiconductor manufacturing method according to claim 1, characterized in that, The voltage applied to the silicon coating is between 100V and 400V.
6. The semiconductor manufacturing method according to claim 1, characterized in that, In the dry etching process, the reaction gas includes an etching gas and a dilution gas. The etching gas includes at least one of CF4, CH2F2, CHF3, or C4F8, and the dilution gas includes N2 or Ar.
7. The semiconductor manufacturing method according to claim 6, characterized in that, The flow rate of the reactant gas is between 5 sccm and 1500 sccm.
8. The semiconductor manufacturing method according to claim 6, characterized in that, The reacting gas also includes O2.
9. The semiconductor manufacturing method according to claim 8, characterized in that, O2 is introduced into the reaction chamber through two pipes. The flow rate of O2 in the first pipe is between 5 sccm and 30 sccm, and the flow rate of O2 in the second pipe is between 5 sccm and 200 sccm.
10. The semiconductor manufacturing method according to any one of claims 1 to 9, characterized in that, The material of the hard mask layer comprises silicon dioxide, and the material of the layer to be etched comprises silicon.