Bonding method, wafer stacking structure and chip structure
By testing and screening the chip area of the C2W stacking structure, chips with good functions are selected and bonded to the second wafer, the problem of the reduction in the yield of multi-layer wafer stacking in the prior art is solved, and the yield maintenance and loss reduction of high-layer stacking is achieved.
CN119650511APending Publication Date: 2025-03-18WUHAN XINXIN SEMICON MFG CO LTD
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Patent Information
- Application Number
- CN202311168510.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-08
- Publication Date
- 2025-03-18
AI Technical Summary
Technical Problem
The existing C2W stacking structure is difficult to maintain a yield of 100% during multi-layer wafer stacking. As the number of layers increases, the yield of the bonded wafer stacking structure gradually decreases, resulting in an increase in losses.
Method used
Provided a bonding method, including providing at least one first wafer stack structure, testing each of its chip areas, cutting to form a corresponding chip, and bonding a well-functioning chip to the second wafer to form a multi-layer stack structure.
Benefits of technology
By testing and screening chips with better functions on each chip area of a smaller layer wafer stack structure, a higher number of chip-wafer stacking is achieved, maintaining a higher yield and reducing losses.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention provides a bonding method, a wafer stacking structure and a chip structure. The bonding method comprises the following steps: providing at least one first wafer stacking structure, and testing each chip area in the first wafer stacking structure; wherein the first wafer stacking structure comprises a plurality of first wafers which are bonded together; cutting the first wafer stacking structure to form a chip corresponding to the chip area; and bonding the chip with good function determined by the test with a second wafer. According to the method, after screening and testing, a small number of layers of chips with good functions are determined and then are further stacked, the bonded multi-layer stacked structure can be maintained at a high yield, the performance is achieved, and the loss is reduced.
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