Dual-mode switching Buck converter and control method

Abstract

The invention is applicable to the technical field of switching power supplies, and provides a dual-mode switching Buck converter, which realizes a system protection function and a low power consumption mode by adding an HVT (High Voltage Threshold) module in a loop to control the on and off of a power tube. The HVT module compares output feedback voltage VFB with reference voltage Vref, upper and lower power tubes can be quickly turned off in a soft start stage, and chip burning caused by transient overvoltage of a system is effectively avoided; in the PFM mode, the conduction loss is reduced by turning off a power tube, and the low-power-consumption mode is started; meanwhile, when a current-limiting ILIM mechanism is triggered, the upper power tube is closed, the lower power tube is opened, and redundant current in a loop is released to prevent a backflow phenomenon. According to the invention, a heavy-load PWM and light-load PFM dual-mode switching control strategy of the Buck converter is realized, the overall working efficiency is improved, the stability of the converter can be effectively improved, an ECO (energy-saving) mode is increased, and the power consumption of the system is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of power electronic converters, and in particular to a dual-mode switching Buck converter. Background Art

[0002] In recent years, various portable electronic products have been continuously innovated, and consumer electronic products such as mobile phones and wearable devices have been continuously integrated into people's lives. The power management chip is the heart of electronic products. It is mainly responsible for stably providing the voltage required by the system to ensure the normal operation of the system. As the cornerstone of future social and technological development, its core position is unshakable.

[0003] As the demand for low power consumption continues to increase, in order to ensure high efficiency while extending battery life, Buck converters have emerged as the main force in the power consumption market. At present, some Buck converters use a single control strategy, such as pure PWM mode or pure PFM mode. The PWM mode has a simple control loop, small output ripple, good frequency response, and high linearity. Especially under heavy load conditions, it has excellent efficiency performance, but poor efficiency under light load conditions. This control mode causes the power tube to bear greater voltage and current stress. In contrast, the PFM mode has high light load efficiency, but large ripple. At the same time, the general ripple spectrum is scattered irregularly, resulting in a more complex filter circuit design. This control mode cannot be applied to low-noise scenarios.

[0004] Therefore, in view of the shortcomings of a single control mode, a new logic circuit is designed to combine the two modes to complement each other's advantages and disadvantages. At the same time, the existing topology is optimized and a more complete Buck converter system architecture is designed to reduce overall power consumption and enhance system stability and conversion efficiency. Summary of the invention

[0005] To solve the above problems, the present invention proposes a dual-mode switching Buck converter. By setting up an HVT module and changing the trigger mechanism of ZCD, the converter can adaptively switch the working mode with the load, thereby improving the overall efficiency, enhancing the stability and reducing the power consumption of the system.

[0006] The technical solution of the present invention is:

[0007] A dual-mode switching Buck converter includes a logic drive circuit, a gate drive unit, a power tube, an input / output circuit, and also includes an HVT (High Voltage Threshold) module, a ZCD (zero crossing detection) circuit, an RS trigger, a PWM comparator, an error amplifier, an inductor current detection circuit, a slope compensation circuit, an oscillator, a current limiting module, a D trigger, an inverter, an AND gate, an NOR gate, and a NOT gate; wherein the positive input terminal of the error amplifier is connected to an internal reference voltage, the negative input terminal is connected to a feedback voltage, and the output terminal of the error amplifier is connected to the negative input terminal of the PWM comparator; the source terminal of the upper power tube is connected to the input voltage, the source terminal of the lower power tube is grounded, and the drain terminals of the upper and lower power tubes are connected; the inductor current detection circuit samples the current flowing through the power tube, and the output terminal is connected to the slope compensation circuit; one output terminal of the oscillator is connected to an input terminal of the AND gate, and the other output terminal is connected to the slope compensation circuit; the output terminal of the slope compensation circuit is connected to the PWM comparator, and the output terminal of the PWM comparator is connected to the R input terminal of the RS trigger; the positive input terminal of the ZCD is connected to The drain end of the power tube and the negative input end are grounded, one output end is connected to the D input end of the D flip-flop, and the other output end is connected to the input end of the NOT gate; one input end of the HVT module is connected to the internal reference voltage, the other input end is connected to the feedback voltage, and the output end is connected to the input end of the NOR gate; the output end of the NOR gate is connected to the other input end of the NOR gate; the output end of the NOR gate is connected to the other input end of the AND gate; the output end of the AND gate is connected to the S input end of the RS flip-flop; the gate of the upper power tube is connected to the input end of the inverter, and the output end of the inverter is connected to the CLK end of the D flip-flop; the input end of the current limiting module is connected to the drain end of the power tube; the Q output end of the RS flip-flop, the Q output end of the D flip-flop and the output end of the current limiting module are all connected to the input end of the logic drive circuit, and under the synergistic effect of the three, a pulse signal is output to the gate drive unit; the gate drive unit is respectively connected to the gate ends of the upper and lower power tubes, and the drain end of the power tube is connected to the output circuit.

[0008] Furthermore, the current limiting module ILIM works in the PFM mode. When the inductor current value is higher than the set threshold current, the system is regulated by turning on the lower power tube and turning off the upper power tube.

[0009] Furthermore, the slope compensation circuit intervenes at the end of the system frequency reduction startup and the oscillator outputs a normal operating frequency.

[0010] Furthermore, the clock of the D flip-flop is obtained by collecting the inverted voltage of the upper power tube switch signal, and the output signal of the ZCD is used as the D terminal input.

[0011] Furthermore, the output of the PWM comparator is a primary RESET signal, and the current limiting module ILIM is a secondary RESET signal in the case of output overcurrent. The primary RESET signal and the secondary RESET signal adapt to different working modes of the system by turning off the power tube.

[0012] Furthermore, the ZCD (zero crossing detection) circuit and the D flip-flop together form a control circuit for switching the PWM mode to the PFM mode. By setting a reasonable number of times, the system determines that it has entered a light load state and enters the PFM working mode.

[0013] Further, the HYT module includes ten PMOS tubes, fifteen NMOS tubes, and three resistors, wherein: the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the fifth PMOS tube MP5, the source of the sixth PMOS tube MP6, the source of the seventh NMOS tube MN7, the source of the eighth MOS tube MP8, the source of the ninth PMOS tube MP9, and the source of the tenth PMOS tube are connected to the power supply VCC; the source of the third NMOS tube MN3, the source of the second NMOS tube MN2, the source of the fifth NMOS tube MN5, the source of the eighth NMOS tube MN8, the source of the eleventh NMOS tube MN11, the source of the fourteenth NMOS tube MN14, and the source of the fifteenth NMOS tube MN15 are connected to the ground; the gate of the third NMOS tube MN3, the gate of the fifth NMOS tube MN5, and the gate of the eighth NMOS tube MN8 are connected to the gate of the eleventh NMOS tube.

[0014] The first PMOS tube MP1 has a gate connected to the gate of the second PMOS tube MP2, and a source connected to the bias voltage IBIAS; the second PMOS tube MP2 has a drain connected to the source of the third PMOS tube MP3; the third PMOS tube MP3 has a gate connected to the gate of the second PMOS tube MP2, and a drain connected to the drain of the first NMOS tube MN1; the first NMOS tube MN1 has a gate connected to a drain, and a source connected to the drain of the third NMOS tube MN3; the gate and drain of the third NMOS tube MN3 are connected; the fourth PMOS tube MP4 has a gate connected to the output terminal VOUT, a source connected to the drain of the sixth PMOS tube MP6, and a drain connected to the drain of the second NMOS tube MN2; the second The gate of the NMOS tube MN2 is connected to the gate of the first NMOS tube MN1; the drain of the fourth NMOS tube MN4 is connected to the drain of the sixth PMOS tube MP6, and the gate is connected to the gate of the first NMOS tube MN1; the drain of the fifth NMOS tube MN5 is connected to the drain of the sixth PMOS tube MP6; the first resistor R1 is connected between the source of the fourth PMOS tube MP4, the drain of the fourth NMOS tube MN4, the drain of the fifth NMOS tube MN5 and the drain of the sixth PMOS tube MP6; the gate of the fifth PMOS tube MP5 is connected to the drain, and the drain is connected to the drain of the sixth NMOS tube MN6; the second resistor R2 is connected between the drain of the fifth PMOS tube MP5 and the drain of the sixth NMOS tube MN6. 6; the sixth PMOS tube MP6, the gate is connected to the drain, and the drain is connected to the drain of the seventh NMOS tube MN7; the third resistor R3 is connected between the drain of the sixth PMOS tube MP6 and the drain of the seventh NMOS tube MN7; the sixth NMOS tube MN6, the gate is connected to the input signal VIP, and the source is connected to the source of the seventh NMOS tube MN7; the seventh NMOS tube MN7, the gate is connected to the input signal VIN; the eighth NMOS tube MN8, the drain is connected to the source of the sixth NMOS tube MN6 and the source of the seventh NMOS tube MN7; the seventh PMOS tube MP7, the gate is connected to the gate of the tenth PMOS tube MP10, and the drain is connected to the drain of the ninth NMOS tube MN9 The eighth PMOS tube MP8 has a gate connected to a drain, and the drain is connected to the drain of the tenth NMOS tube MN10; the ninth NMOS tube MN9 has a gate connected to the drain of the seventh NMOS tube, and a source connected to the source of the tenth NMOS tube MN10; the tenth NMOS tube MN10 has a gate connected to the drain of the sixth NMOS tube MN6; the eleventh NMOS tube MN11 has a source connected to the source of the ninth NMOS tube MN9 and the source of the tenth NMOS tube; the ninth PMOS tube MP9 has a gate connected to the gate of the eighth PMOS tube MP8, and a drain connected to the drain of the twelfth NMOS tube MN12; the tenth PMOS tube MP10 has a drain connected to the drain of the thirteenth NMOS tube MN13;The gate of the twelfth NMOS tube MN12 is connected to the drain, and the source is connected to the drain of the fourteenth NMOS tube MN14; the gate of the thirteenth NMOS tube MN13 is connected to the gate of the twelfth NMOS tube MN12, and the source is connected to the drain of the fifteenth NMOS tube MN15; the drain of the fourteenth NMOS tube MN14 is connected to the gate; the gate of the fifteenth NMOS tube MN15 is connected to the gate of the fourteenth NMOS tube MN14; the output terminal VOUT is drawn between the drain of the tenth PMOS tube MP10 and the drain of the thirteenth NMOS tube MN13.;

[0015] Furthermore, the HVT module compares the feedback voltage VFB and the reference voltage Vref, and the output is switched at a threshold of ±102.3% of the reference voltage. In the PFM working mode, when the voltage is higher than the upper threshold, HVT=1, the chip is turned off and enters the ECO (energy saving) mode; when the voltage is lower than the lower threshold, HVT=0, and the system works normally.

[0016] Furthermore, the S terminal of the RS trigger is normally connected to the voltage signal output by the oscillator. When a transient overvoltage occurs in the system, VFB is higher than the voltage threshold of the HVT module, HVT=1, and the power tube is turned off to prevent the chip from burning due to overvoltage.

[0017] The beneficial effects of this application are:

[0018] After adopting the circuit of the present application, the system can adaptively switch to work in different output environments, realize heavy-load PWM mode and light-load PFM mode, greatly improve the overall working efficiency and reduce output ripple; by changing the number of times the output signal of the ZCD (zero-crossing detection circuit) touches zero, the system judgment accuracy is improved, and the PFM mode can be accurately entered; by adding an HVT module, the system can be effectively prevented from burning the chip due to transient overvoltage; the system can be made to enter the ECO (energy-saving) mode in the PFM mode to reduce the overall power consumption; at the same time, when the current-limiting ILIM mechanism is triggered, the upper power tube can be turned off and the lower power tube can be turned on to release the excess current in the loop to prevent backflow. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a circuit diagram of the present invention.

[0020] Figure 2 Shown are the key waveforms from PWM mode to PFM mode.

[0021] Figure 3 Shown is a circuit diagram of the HVT module of the present invention.

[0022] Figure 4 Shown is the key waveform of the inductor current in PFM mode. DETAILED DESCRIPTION

[0023] In the following description, specific details such as specific system structures and technologies are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details that obscure the description of the present application.

[0024] The present invention is described in detail below with reference to the accompanying drawings.

[0025] The dual-mode switching Buck converter control architecture of the present invention realizes system protection function and low power consumption mode by adding an HVT (High Voltage Threshold) module in the loop to control the conduction and shutdown of the power tube. The HVT module can quickly shut down the upper and lower power tubes in the soft start stage by comparing the output feedback voltage VFB with the reference voltage Vref, effectively avoiding the burning of the chip when the system has transient overvoltage; in the PFM mode, the low power consumption mode is turned on by turning off the power tube to reduce the conduction loss; at the same time, when the current limiting ILIM mechanism is triggered, the upper power tube can be turned off and the lower power tube can be turned on to release the excess current in the loop to prevent the backflow phenomenon. The present invention realizes the Buck converter heavy-load PWM and light-load PFM dual-mode switching control strategy, which can effectively improve the stability of the converter while improving the overall working efficiency, and add the ECO (energy saving) mode to reduce the system power consumption.

[0026] See also Figure 1 When the system is powered on normally, the upper power tube is turned on and the lower power tube is turned off. The converter works in the charging stage (on duty). The voltage is generated by the drain of the power tube through the inductor 117 and the capacitor C OUT Energy storage, output voltage V OUT The output voltage gradually rises, and at this time, the output voltage is divided by R1 and R2 to output the system feedback voltage VFB. The system's OSC oscillator 105 mainly outputs three waveforms. First, in the soft start phase, a low-frequency signal is output, the purpose of which is to avoid the startup phase due to the output V OUT It has not been formally established yet. The insufficient discharge capacity of the lower power tube causes the inductor to generate surge current. When V OUTGradually rising, when the feedback voltage VFB reaches 200mV, OSC switches to the normal working frequency output; at the same time, a triangle wave is provided to the slope compensation circuit 104. The error amplifier (EA) 101 compares the reference voltage Vref and the feedback voltage VFB, and sends the comparison result to the inverting input terminal (-) of the PWM comparator 116. The error amplifier also plays a clamping role in the soft start stage to prevent the system from working in a loop-out state. The inductor current detection circuit 106 converts the inductor current into a voltage signal and sends it to the slope compensation circuit 104. The signal is sent to the positive input terminal (+) of the PWM comparator 116 after slope compensation. The two signals are compared by the PWM comparator 116 to generate a reset signal RESET1. The S terminal of the RS trigger 103 receives the working frequency pulse signal in the normal working mode, and the Q terminal outputs a logic pulse signal to the Logic Drive driving logic unit, turning off the upper power tube and turning on the lower power tube. The converter works in the discharge stage (off duty). Then the S input terminal of the RS trigger waits for the VSET signal to enter the next cycle. During the entire system soft start phase, the control system is forced to operate in PWM mode until the system soft start module outputs the SSDN (Soft Start Done) signal, after which the system will adaptively switch modes according to changes in load current.

[0027] UGB_SNS is a voltage signal obtained by inverting the gate voltage of the upper power tube. This signal is sent to the CLK terminal of the D flip-flop 109. The voltage at the switch SW is sent to the positive input terminal (+) of the ZCD (zero crossing detection circuit) 110, and the negative input terminal is grounded. The ZCD determines the number of zero crossings of the inductor current and sends the output signal to the D input port of the D flip-flop 109. Figure 2 When the system is officially started, the load at the output end changes, and the output current drops below 100mA. The system turns on the detection ZCD through the Buck high-side power tube. RB is the internal counter signal of the D flip-flop 109. When ZCD is triggered 27 times in succession, the Q end of the D flip-flop 109 outputs a high level; if a ZCD signal is lost, the counter will be reset. The Q output end of the D flip-flop 109 sends the PFM signal to the Logic Drive drive logic unit, and the overall system switches to the PFM working mode. Before the ILIM mechanism is triggered, the system turns off the power tube at the same time and enters the ECO (energy saving) mode, which greatly reduces the conduction loss of the power tube.

[0028] See also Figure 3, including a constant bias current IBIAS, ten PMOS tubes, fifteen NMOS tubes, and three resistors. The circuit mainly consists of three parts. The first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the first NMOS tube MN1, and the third NMOS tube MN3 together form a bias circuit 301. The source of the first PMOS tube MP1 is connected to the bias current IBIAS, and its gate is connected to the gates of the second PMOS tube MP2 and the third PMOS tube MP3, forming a current mirror structure to replicate the IBIAS current. The gate and drain of the first NMOS tube MN1 are connected to provide a bias voltage to the second NMOS tube MN2 and the fourth NMOS tube MN4. The gate and drain of the third NMOS tube are connected to provide a bias voltage to the current tail tubes such as the fifth NMOS tube MN5, the eighth NMOS tube MN8, and the eleventh NMOS tube MN11; the fourth PMOS tube MP4, the second NMOS tube MP2, the fourth NMOS tube MN4, and the fifth NMOS tube MN5 constitute the HVT auxiliary functional circuit 302. The source of the fourth PMOS tube MP4 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the source of the fifth PMOS tube. A current path is drawn from the comparison circuit 303 module, and its gate is directly connected to the output terminal VOUT of the HVT module. The hysteresis time of the output terminal VOUT is controlled by changing the width-to-length ratio of the fourth PMOS tube MP4. The second NMOS tube MN2, the fourth NMOS tube MN4 and the fifth NMOS tube work together to optimize the circuit PVT performance by reasonably setting the width-to-length ratio; the 303 part is a secondary comparator circuit, in which the gate of the sixth NMOS tube MN6 is a positive input port, which is externally connected to the reference voltage Vref, and the gate of the seventh NMOS tube MN7 is a negative input port, which is externally connected to the feedback voltage VFB. The gates of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected to the drain, which is a diode load. The gates of the ninth NMOS tube MN9 and the tenth NMOS tube are the input terminals of the second-stage comparator, which are respectively connected to the drains of the seventh NMOS tube MN7 and the sixth NMOS tube MN6. The two-stage comparator can gradually amplify the signal, optimize the signal processing method, and has a faster response speed; the graded gain method can greatly improve the input sensitivity of the comparator; at the same time, it can improve the common mode rejection ratio (CMRR) and the noise suppression ratio, and improve the reliability of the system in a complex electromagnetic environment; and it can dynamically optimize the power consumption under different working conditions and extend the working time of the system. Therefore, the structure of the two-stage comparator is very suitable for the application scenarios of the Buck system and battery power supply in this application. The input terminal VIP of the HVT module is connected to the Vref voltage, and the input terminal VIN is connected to the feedback voltage VFB. The two voltages are compared, and the output is switched at the threshold of ±102.3% of the reference voltage. When it is higher than the upper threshold voltage, HVT=1, and the chip is turned off; when it is lower than the lower threshold voltage, HVT=0, and the system works normally.

[0029] The HYT module plays two main functions in the system: protection and energy saving. First, during the startup phase of the Buck converter, the system experiences transient overvoltage. At this time, the output voltage is much higher than the rated output voltage. If the converter continues to work, the power tube will be burned due to overcurrent and overvoltage. The feedback voltage VFB is sent to the negative input of the HVT module. Since VFB is greater than 102.3% of the reference voltage, HYT = 1, the chip is turned off until the VFB voltage drops to the normal voltage range, HVT = 0, and the system continues to work; when the converter is in the normal working stage, the internal power is sufficient, and it is detected that the VFB voltage is greater than the set threshold voltage, HVT = 1, the power tube is turned off, and the system enters the ECO (energy saving) mode, which can effectively reduce the system power consumption; when the system works in PFM mode, ILIM is the main control logic, controlling the conduction and shutdown of the upper and lower power tubes, Figure 4 It is the key waveform of the inductor current in the PFM mode. Before the third peak of the inductor current arrives, the HVT signal detects that the feedback voltage is too high, HVT = 1, and intervenes in advance, turning off the upper power tube and turning on the lower power tube to release the excess current in the loop to prevent backflow.

[0030] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A dual-mode switching Buck converter, comprising a logic drive circuit, a gate drive unit, a power tube, and an input / output circuit, characterized in that: The positive input of the error amplifier is connected to the internal reference voltage, the negative input is connected to the feedback voltage, and the output of the error amplifier is connected to the negative input of the PWM comparator; the source of the upper power tube is connected to the input voltage, the source of the lower power tube is grounded, and the drains of the upper and lower power tubes are connected; the inductor current detection circuit samples the current flowing through the power tube, and the output is connected to the slope compensation circuit; one output of the oscillator is connected to one input of the AND gate, and the other output is connected to the slope compensation circuit; the output of the slope compensation circuit is connected to the PWM comparator, and the output of the PWM comparator is connected to the R input of the RS trigger; the positive input of the ZCD is connected to the drain of the power tube, the negative input is grounded, one output is connected to the D input of the D trigger, and the other output is connected to the input of the NOT gate; HVT module One input terminal is connected to the internal reference voltage, the other input terminal is connected to the feedback voltage, and the output terminal is connected to the input terminal of the NOR gate; the output terminal of the NOR gate is connected to the other input terminal of the NOR gate; the output terminal of the NOR gate is connected to the other input terminal of the AND gate; the output terminal of the AND gate is connected to the S input terminal of the RS trigger; the gate of the upper power tube is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the CLK terminal of the D trigger; the input terminal of the current limiting module is connected to the drain terminal of the power tube; the Q output terminal of the RS trigger, the Q output terminal of the D trigger and the output terminal of the current limiting module are all connected to the input terminal of the logic drive circuit, and under the coordinated action of the three, a pulse signal is output to the gate drive unit; the gate drive unit is respectively connected to the gate terminals of the upper and lower power tubes, and the drain terminal of the power tube is connected to the output circuit.

2. A dual-mode switching Buck converter according to claim 1, characterized in that: The current limiting module works in the PFM mode. When the inductor current value is higher than the set threshold current, the system is regulated by turning on the lower power tube and turning off the upper power tube.

3. A dual-mode switching Buck converter according to claim 1, characterized in that: The slope compensation circuit intervenes when the system frequency reduction startup is completed and the oscillator outputs a normal operating frequency.

4. A dual-mode switching Buck converter according to claim 1, characterized in that: The clock of the D flip-flop is obtained by collecting the inverted voltage of the upper power tube switch signal, and the output signal of the ZCD is used as the D terminal input.

5. A dual-mode switching Buck converter according to claim 1, characterized in that: The output of the PWM comparator is a primary RESET signal, and the current limiting module is a secondary RESET signal in the case of output overcurrent. The primary RESET signal and the secondary RESET signal are adapted to different working modes of the system by turning off the power tube.

6. A dual-mode switching Buck converter according to claim 1, characterized in that: The ZCD circuit and the D trigger together form a control circuit for switching from PWM mode to PFM mode. By setting a reasonable number of times, the system determines that it has entered a light load state and enters the PFM working mode.

7. A dual-mode switching Buck converter according to claim 1, characterized in that: The HYT module includes ten PMOS tubes, fifteen NMOS tubes, and three resistors, wherein: the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the fifth PMOS tube MP5, the source of the sixth PMOS tube MP6, the source of the seventh NMOS tube MN7, the source of the eighth MOS tube MP8, the source of the ninth PMOS tube MP9, and the source of the tenth PMOS tube are connected to the power supply VCC; the source of the third NMOS tube MN3, the source of the second NMOS tube MN2, the source of the fifth NMOS tube MN5, the source of the eighth NMOS tube MN8, the source of the eleventh NMOS tube MN11, the source of the fourteenth NMOS tube MN14, and the source of the fifteenth NMOS tube MN15 are connected to the ground; the gate of the third NMOS tube MN3, the gate of the fifth NMOS tube MN5, and the gate of the eighth NMOS tube MN8 are connected to the gate of the eleventh NMOS tube; The first PMOS tube MP1 has a gate connected to the gate of the second PMOS tube MP2, and a source connected to the bias voltage IBIAS; the second PMOS tube MP2 has a drain connected to the source of the third PMOS tube MP3; the third PMOS tube MP3 has a gate connected to the gate of the second PMOS tube MP2, and a drain connected to the drain of the first NMOS tube MN1; the first NMOS tube MN1 has a gate connected to a drain, and a source connected to the drain of the third NMOS tube MN3; the gate and drain of the third NMOS tube MN3 are connected; the fourth PMOS tube MP4 has a gate connected to the output terminal VOUT, a source connected to the drain of the sixth PMOS tube MP6, and a drain connected to the drain of the second NMOS tube MN2; the second The gate of the NMOS tube MN2 is connected to the gate of the first NMOS tube MN1; the drain of the fourth NMOS tube MN4 is connected to the drain of the sixth PMOS tube MP6, and the gate is connected to the gate of the first NMOS tube MN1; the drain of the fifth NMOS tube MN5 is connected to the drain of the sixth PMOS tube MP6; the first resistor R1 is connected between the source of the fourth PMOS tube MP4, the drain of the fourth NMOS tube MN4, the drain of the fifth NMOS tube MN5 and the drain of the sixth PMOS tube MP6; the gate of the fifth PMOS tube MP5 is connected to the drain, and the drain is connected to the drain of the sixth NMOS tube MN6; the second resistor R2 is connected between the drain of the fifth PMOS tube MP5 and the drain of the sixth NMOS tube MN6. 6; the sixth PMOS tube MP6, the gate is connected to the drain, and the drain is connected to the drain of the seventh NMOS tube MN7; the third resistor R3 is connected between the drain of the sixth PMOS tube MP6 and the drain of the seventh NMOS tube MN7; the sixth NMOS tube MN6, the gate is connected to the input signal VIP, and the source is connected to the source of the seventh NMOS tube MN7; the seventh NMOS tube MN7, the gate is connected to the input signal VIN; the eighth NMOS tube MN8, the drain is connected to the source of the sixth NMOS tube MN6 and the source of the seventh NMOS tube MN7; the seventh PMOS tube MP7, the gate is connected to the gate of the tenth PMOS tube MP10, and the drain is connected to the drain of the ninth NMOS tube MN9 The eighth PMOS tube MP8 has a gate connected to a drain, and the drain is connected to the drain of the tenth NMOS tube MN10; the ninth NMOS tube MN9 has a gate connected to the drain of the seventh NMOS tube, and a source connected to the source of the tenth NMOS tube MN10; the tenth NMOS tube MN10 has a gate connected to the drain of the sixth NMOS tube MN6; the eleventh NMOS tube MN11 has a source connected to the source of the ninth NMOS tube MN9 and the source of the tenth NMOS tube; the ninth PMOS tube MP9 has a gate connected to the gate of the eighth PMOS tube MP8, and a drain connected to the drain of the twelfth NMOS tube MN12; the tenth PMOS tube MP10 has a drain connected to the drain of the thirteenth NMOS tube MN13;The gate of the twelfth NMOS tube MN12 is connected to the drain, and the source is connected to the drain of the fourteenth NMOS tube MN14; the gate of the thirteenth NMOS tube MN13 is connected to the gate of the twelfth NMOS tube MN12, and the source is connected to the drain of the fifteenth NMOS tube MN15; the drain of the fourteenth NMOS tube MN14 is connected to the gate; the gate of the fifteenth NMOS tube MN15 is connected to the gate of the fourteenth NMOS tube MN14; the output terminal VOUT is drawn between the drain of the tenth PMOS tube MP10 and the drain of the thirteenth NMOS tube MN13.; 8. A dual-mode switching Buck converter according to claim 7, characterized in that: The HVT module compares the feedback voltage VFB with the reference voltage Vref, and outputs a threshold switch at ±102.3% of the reference voltage. In the PFM working mode, when the voltage is higher than the upper threshold, HVT=1, the chip is turned off and enters the ECO (energy saving) mode; when the voltage is lower than the lower threshold, HVT=0, and the system works normally.

9. A dual-mode switching Buck converter according to claim 7, characterized in that: The S terminal of the RS trigger is normally connected to the voltage signal output by the oscillator. When a transient overvoltage occurs in the system, VFB is higher than the voltage threshold of the HVT module, HVT=1, and the power tube is turned off to prevent the chip from burning due to overvoltage.

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