A multi-rate convolutional code sequence decoder and decoding method

Abstract

The present application discloses a multi-rate convolutional code sequence decoder and decoding method, which relates to the field of communication decoding technology. The decoder includes: a data storage module, a branch metric module, a parallel processing module, a shift register, a convolutional coding module, and a main control module; receiving and storing a coding rate identification bit and data to be decoded in input data; selecting a non-systematic code generator according to the coding rate identification bit, performing convolution processing on the non-systematic code generator according to a preset number of shift data and the non-systematic code generator to obtain a convolutional code; obtaining the data to be decoded according to the non-systematic code generator, calculating a branch metric value according to the coding rate identification bit, the data to be decoded, and the convolutional code; determining a decoding result of the data to be decoded according to the branch metric value and the total metric value, and updating the total metric value; updating the shift data in the shift register according to the updated total metric value; and storing the shift data. The present invention can efficiently process input data and improve the overall data processing speed and efficiency.

Description

Technical Field

[0001] The present application relates to the field of communication decoding technology, and more specifically, to a multi-rate convolutional code sequence decoder and a decoding method. Background Art

[0002] Low-frequency (10kHz-100kHz) radio waves propagate in the Earth-ionosphere waveguide. They offer stable transmission, are unaffected by nuclear explosions and ionospheric disturbances, and exhibit minimal atmospheric attenuation (-3dB / 1000km). They can penetrate deep ocean waters and the ground, making them suitable for long-distance, underwater, and through-the-ground communications. However, due to long-distance transmission and attenuation in ocean water, low-frequency signals are already extremely weak, resulting in a low signal-to-noise ratio. Therefore, when processing low-frequency signals, it is crucial to select a decoder and decoding method with superior performance to improve communication reliability.

[0003] Existing convolutional code decoding techniques can be roughly divided into two categories: algebraic decoding and probabilistic decoding. Generally, algebraic decoding has a specific algebraic structure, is simple to implement, and easy to implement; probabilistic decoding offers strong error correction capabilities. The widely used Viterbi decoding method, also known as maximum likelihood decoding, is a type of probabilistic decoding. Its advantages include strong error correction capabilities and, when decoding constraints are small, lower computational complexity than other probabilistic decoding methods.

[0004] However, the existing convolutional code decoding technology has high decoding complexity and takes a long time to implement in conventional DSPs and CPUs, which cannot meet the requirements of low-frequency communication systems. In some high-speed communication scenarios, the computational complexity is still too high to meet the needs of real-time decoding. Therefore, further improvements are needed to significantly reduce the computational complexity without affecting the error correction capability, so as to achieve fast and real-time decoding and output data. Summary of the Invention

[0005] In response to at least one defect or improvement need in the prior art, the present invention provides a multi-rate convolutional code sequence decoder and decoding method, which are used to solve the problems in the prior art that the convolutional code decoding technology has high decoding complexity, is time-consuming when implemented in a conventional DSP or CPU, cannot meet the requirements of low-frequency communication systems, and cannot meet the needs of real-time decoding.

[0006] To achieve the above objectives, according to a first aspect of the present invention, a multi-rate convolutional code sequence decoder is provided, comprising: a data storage module, a branch metric module, a parallel processing module, a shift register, a convolutional encoding module, and a main control module; the main control module is respectively connected to the data storage module, the branch metric module, the parallel processing module, the shift register, and the convolutional encoding module; the parallel processing module is respectively connected to the branch metric module; and the convolutional encoding module is respectively connected to the branch metric module and the shift register.

[0007] The data storage module is used to receive and store the coding rate identification bit and the data to be decoded in the input data;

[0008] The convolutional coding module is used to select a non-systematic code generator according to the coding rate identification bit, and perform convolution processing on the non-systematic code generator according to the shift data of a preset number of bits to obtain a convolutional code;

[0009] The branch metric module is used to obtain the data to be decoded according to the non-systematic code generator, and calculate the branch metric value according to the coding rate flag, the data to be decoded and the convolutional code;

[0010] The parallel processing module is used to determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0011] The main control module is used to update the shift data in the shift register according to the updated total measurement value;

[0012] The shift register is used to store the shifted data.

[0013] According to a second aspect of the present invention, a multi-rate convolutional code sequence decoding method is also provided, based on the multi-rate convolutional code sequence decoder as described above, comprising:

[0014] Receive and store the coding rate identification bit and the data to be decoded in the input data;

[0015] Selecting a non-systematic code generator according to the coding rate identifier, and obtaining data to be decoded according to the non-systematic code generator;

[0016] Performing convolution processing on the shift data of a preset number of bits and a non-systematic code generator to obtain a convolution code;

[0017] Calculating a branch metric value according to a coding rate flag, data to be decoded, and a convolutional code;

[0018] Determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0019] The shift data in the shift register is updated according to the updated total metric value.

[0020] In one possible implementation, receiving and storing a coding rate identifier and data to be decoded in input data, and then initializing parameters of a multi-rate convolutional code sequence decoder, specifically including:

[0021] Initialize the shift register to zero; initialize the number of nodes and the number of calculations stored in the main control module to zero; initialize the total metric value stored in the parallel processing module to zero; and set a preset total metric value change.

[0022] In one possible implementation, selecting a non-systematic code generator according to a coding rate indicator, and obtaining data to be decoded according to the non-systematic code generator include:

[0023] When selecting a non-systematic code generator of a first rate according to the coding rate identifier, obtaining a first amount of data to be decoded;

[0024] When selecting a non-systematic code generator of a second rate according to the coding rate identifier, obtaining a second amount of data to be decoded;

[0025] When a non-systematic code generator of a third rate is selected according to the coding rate identifier, a third amount of data to be decoded is obtained.

[0026] In one possible implementation, performing convolution processing on shift data of a preset number of bits and a non-systematic code generator to obtain convolution coding includes:

[0027] Convolution processing is performed on the shifted data of a preset number of bits and a non-systematic code generator to obtain a first convolution code;

[0028] A first value and a second value are respectively added to the left end of the shifted data of the preset number of bits and convolved with a non-systematic code generator to obtain a second convolutional code and a third convolutional code.

[0029] In one possible implementation, calculating a branch metric value according to a coding rate indicator, data to be decoded, and convolutional coding includes:

[0030] Calculating a first branch metric value based on a first rate, a first amount of data to be decoded, and a convolutional code;

[0031] Calculating a second branch metric value based on a second rate, a second amount of data to be decoded, and the convolutional code;

[0032] A third branch metric value is calculated according to a third rate, a third amount of data to be decoded, and convolutional coding.

[0033] In one possible implementation, determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value, includes:

[0034] When the sum of the branch metric value of the second convolutional coding and the total metric value is greater than zero, the decoding result of the to-be-decoded data is zero, and the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional coding;

[0035] When the sum of the branch metric value of the second convolutional code and the total metric value is less than or equal to zero, and the sum of the branch metric value of the third convolutional code and the total metric value is greater than zero, the decoding result of the to-be-decoded data is one, and the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional code;

[0036] When neither of the above two situations is met, if the number of nodes is zero or the number of nodes is greater than zero and the difference between the total metric value and the branch metric value of the first convolutional code is less than zero, then the total metric value is updated by the sum of the total metric value and the preset total metric value change; otherwise, go back to the previous node and update the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code.

[0037] In a possible implementation, updating the shift data in the shift register according to the updated total metric value includes:

[0038] When the total metric value is updated by adding the sum of the total metric value and the branch metric value of the second convolutional code, zero is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0039] When the total metric value is updated by adding the sum of the total metric value and the branch metric value of the third convolutional code, one is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one.

[0040] When updating the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code, zero is shifted leftward into the shift register, the number of nodes is decremented by one, and the number of calculations is incremented by one;

[0041] When the total metric value is updated by adding the total metric value and the preset total metric value change, the number of calculations is incremented by one.

[0042] According to a third aspect of the present invention, a multi-rate convolutional code sequence decoding device is also provided, which includes at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit performs the steps of any one of the above-mentioned multi-rate convolutional code sequence decoding methods.

[0043] According to a fourth aspect of the present invention, a storage medium is also provided, which stores a computer program that can be executed by an access authentication device. When the computer program is run on the access authentication device, the access authentication device executes the steps of any one of the multi-rate convolutional code sequence decoding methods described above.

[0044] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0045] The present invention provides a multi-rate convolutional code sequence decoder. The data storage module can receive and store large amounts of input data, including coding rate identifiers and data to be decoded, providing a reliable data source for subsequent processing. The convolutional coding module selects non-systematic code generators based on the coding rate identifiers and performs convolution processing to generate convolutional codes. This allows the system to flexibly adjust to different coding rate requirements, thereby improving data processing efficiency. The branch metric module calculates branch metric values ​​based on the non-systematic code generators, coding rate identifiers, and data to be decoded, providing an accurate decoding basis for the parallel processing module. The parallel processing module uses the branch metric values ​​and the total metric value to determine the decoding result and update the total metric value. This parallel processing method improves decoding speed and accuracy and reduces decoding error rate. The main control module updates the shift data in the shift register based on the updated total metric value, achieving dynamic data updating and optimization. This enables the system to adaptively adjust to different decoding results and states, thereby improving system stability and performance. By integrating the data storage module, branch metric module, parallel processing module, shift register, convolutional coding module and main control module, it is possible to select non-systematic code generators according to different coding rate identification bits and support complex convolutional coding and decoding algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic structural diagram of an embodiment of a multi-rate convolutional code sequence decoder provided by the present invention;

[0048] Figure 2 A schematic diagram of a flow chart of an embodiment of a multi-rate convolutional code sequence decoding method provided by the present invention;

[0049] Figure 3 A schematic diagram of the structure of a multi-rate convolutional code sequence decoding device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0051] The terms "first," "second," "third," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0052] The present invention provides a multi-rate convolutional code sequence decoder and decoding method, which are described below respectively.

[0053] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of a multi-rate convolutional code sequence decoder provided by the present invention. In a specific embodiment of the present invention, a multi-rate convolutional code sequence decoder 100 is disclosed, comprising: a data storage module 110, a branch metric module 120, a parallel processing module 130, a shift register 140, a convolutional encoding module 150, and a main control module 160; the main control module 160 is connected to the data storage module 110, the branch metric module 120, the parallel processing module 130, the shift register 140, and the convolutional encoding module 150 respectively; the parallel processing module 130 is connected to the branch metric module 120; and the convolutional encoding module 150 is connected to the branch metric module 120 and the shift register 140 respectively.

[0054] The data storage module 110 is used to receive and store the coding rate identification bit and the data to be decoded in the input data;

[0055] The convolutional coding module 150 is configured to select a non-systematic code generator according to the coding rate identification bit, and perform convolution processing on the non-systematic code generator according to the shift data of a preset number of bits to obtain a convolutional code;

[0056] The branch metric module 120 is used to obtain the data to be decoded according to the non-systematic code generator, and calculate the branch metric value according to the coding rate flag, the data to be decoded and the convolutional code;

[0057] The parallel processing module 130 is used to determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0058] The main control module 160 is used to update the shift data in the shift register 140 according to the updated total metric value;

[0059] The shift register 140 is used to store shift data.

[0060] In the above embodiment, data storage module 110 is responsible for receiving and properly storing external data input, including the coding rate identifier and the data to be decoded. The coding rate identifier is a key identifier for distinguishing different coding rates and is crucial for selecting non-systematic symbol generators in subsequent steps. The data to be decoded is the core information that requires decoding and is securely stored within the module for rapid access during subsequent processing.

[0061] The convolutional coding module 150 intelligently selects the corresponding non-systematic code generator based on the received coding rate identification bit, and then uses the shifted data of a preset number of bits and the non-systematic code generator to accurately generate the convolution code through complex convolution operations. This not only enhances the redundancy of the data and improves the anti-interference ability, but also provides important reference information for the subsequent decoding process.

[0062] The branch metric module 120 first extracts the data to be decoded from the data storage module 110 based on the non-systematic code generator. Then, combining the coding rate identifier, the data to be decoded, and the convolutional coding, it calculates the branch metric value through precise calculation. The metric value provides strong support for subsequent decoding decisions.

[0063] The parallel processing module 130 makes full use of the parallel processing capabilities of modern computing technology and can simultaneously process branch metric values ​​and total metric values ​​of multiple coding rates with different rates, and update the total metric value in real time through the branch metric values ​​and total metric values. This parallel processing method greatly improves the decoding speed and efficiency, ensuring the real-time and accuracy of the decoding process.

[0064] The main control module 160 is responsible for coordinating the data interaction and collaborative work between various modules. It dynamically adjusts the shift data in the shift register 140 according to the updated total metric value to ensure that the decoder can adaptively adjust and optimize according to the current decoding status and results, thereby further improving the decoding performance.

[0065] The shift register 140 is a data storage unit in the decoding process. It is responsible for storing and managing shift data. These data are continuously updated and optimized during the decoding process. Through the continuous iteration and update of the shift register 140, the decoder can gradually approach the actual decoding result, thereby improving the accuracy and reliability of the decoding.

[0066] Compared to the prior art, this embodiment provides a multi-rate convolutional code sequence decoder 100. The data storage module 110 can receive and store large amounts of input data, including coding rate identifiers and data to be decoded, providing a reliable data source for subsequent processing. The convolutional coding module 150 selects non-systematic code generators based on the coding rate identifiers and performs convolution processing to generate convolutional codes. This allows the system to flexibly adjust to different coding rate requirements, improving data processing efficiency. The branch metric module 120 calculates branch metrics based on the non-systematic code generators, coding rate identifiers, and data to be decoded, providing accurate decoding information for the parallel processing module 130. The parallel processing module 130 uses the branch metrics and total metrics to determine the decoding result and update the total metric. This parallel processing approach improves decoding speed and accuracy and reduces decoding error rates. The main control module 160 updates the shift data in the shift register 140 based on the updated total metric value, achieving dynamic data updating and optimization. This allows the system to adaptively adjust to different decoding results and states, improving system stability and performance. By integrating the data storage module 110, the branch metric module 120, the parallel processing module 130, the shift register 140, the convolutional coding module 150 and the main control module 160, it is possible to select non-systematic code generators according to different coding rate identification bits and support complex convolutional coding and decoding algorithms.

[0067] See also Figure 2 , Figure 2 This is a flow chart of an embodiment of a method for decoding a multi-rate convolutional code sequence provided by the present invention. According to a second aspect of the present invention, a multi-rate convolutional code sequence decoding method is also provided. The method is based on the multi-rate convolutional code sequence decoder 100 as described above and includes:

[0068] S201, receiving and storing the coding rate identification bit and the data to be decoded in the input data;

[0069] S202: Select a non-systematic code generator according to the coding rate flag, and obtain data to be decoded according to the non-systematic code generator;

[0070] S203, performing convolution processing on the shift data of a preset number of bits and a non-systematic code generator to obtain a convolution code;

[0071] S204, calculating a branch metric value according to the coding rate flag, the data to be decoded, and the convolutional coding;

[0072] S205, determining a decoding result of the data to be decoded according to the branch metric value and the total metric value, and updating the total metric value;

[0073] S206: Update the shift data in the shift register according to the updated total metric value.

[0074] In the above embodiment, the decoder first receives a data stream from an external source, which includes a coding rate identifier and data to be decoded. The coding rate identifier can distinguish different coding rates and is crucial for selecting non-systematic code generators in subsequent steps. The data to be decoded is the core information that needs to be decoded and is securely stored in the data storage module 110 for easy invocation and processing in subsequent steps.

[0075] The input data also includes the decoding information length, which refers to the actual length of the data sequence to be decoded. It is crucial for the decoder to correctly understand and process the input data. The decoding information length helps the decoder determine the data range to be processed. After receiving the input data, the decoder extracts the corresponding length of the data to be decoded from the input data based on the decoding information length. Without a clear decoding information length, the decoder may continue to process subsequent irrelevant data in the input data, resulting in misdecoding. Therefore, the decoding information length is a crucial factor in ensuring decoding accuracy.

[0076] After receiving the coding rate identifier, the decoder selects the corresponding non-systematic code generator from a preset codebook based on this information. Non-systematic code generators are key parameters in the convolutional encoding and decoding processes, determining encoding redundancy and decoding accuracy. Simultaneously, based on the selected non-systematic code generator, the decoder extracts the corresponding data to be decoded from data storage module 110, preparing for subsequent convolution processing and branch metric calculation.

[0077] The decoder performs convolution processing based on the preset shift data (these data usually come from the shift register 140) and the non-systematic code generator. Convolution processing is a linear operation that generates redundant convolution codes by performing specific combinations and shift operations on the data to be decoded and the non-systematic code generator. This not only enhances the data's anti-interference ability, but also provides important reference information for the subsequent decoding process.

[0078] After obtaining the convolutional code, the decoder will calculate the branch metric value based on the coding rate identifier, the data to be decoded, and the convolutional code. The branch metric value is an important indicator to measure the degree of match between the data to be decoded and the convolutional code. By calculating the branch metric values ​​at different coding rates, it provides a basis for subsequent decoding decisions.

[0079] After obtaining all possible branch metric values, the decoder will use the parallel processing module 130 to compare and screen these branch metric values. By comparing the branch metric values ​​and the total metric value of different coding rates, the decoder can determine the decoding result of the data to be decoded and update the total metric value to reflect this result, thereby determining the accuracy and reliability of the decoding result.

[0080] After determining the decoding result of the data to be decoded and updating the total metric value, the decoder will update the shift data in the shift register 140 based on this information. The updated data will serve as the input for the next convolution processing and decoding process, thus forming a closed-loop iterative process. By continuously updating the shift data, the decoder can gradually approach the actual decoding result and improve the accuracy and efficiency of decoding.

[0081] In some embodiments of the present invention, receiving and storing the coding rate identifier and the data to be decoded in the input data, and then initializing the parameters of the multi-rate convolutional code sequence decoder 100, specifically including:

[0082] Initialize the shift register 140 to zero; initialize the number of nodes and the number of calculations stored in the main control module 160 to zero; initialize the total metric value stored in the parallel processing module 130 to zero; and set a preset total metric value change.

[0083] In the above embodiment, the length of the shift register 140 is N bits, and the shift register 140 is initialized to zero. The shift register 140 is used to store and manage the shift data in the decoding process. These data will be continuously updated during the decoding process. Initialization to zero can ensure that the decoding process starts from a clean state and avoid previous data from interfering with the current decoding.

[0084] The node number Num and calculation count T stored in the main control module 160 are initialized to zero. The node number Num represents the number of nodes to be considered during the decoding process, and the calculation count T records the number of calculations performed during the decoding process. Initializing them to zero ensures that the decoding process starts from a fresh state and accurately records every calculation and every node in the decoding process.

[0085] The total metric value Tsum stored in the parallel processing module 130 is initialized to zero. The total metric value Tsum is used to evaluate the decoding result of the data to be decoded. Initializing it to zero ensures that the decoding process starts from an unbiased state. By gradually calculating and comparing the metric values ​​of different paths, the decoding result of the data to be decoded is finally determined.

[0086] The total metric value variation delta can be set according to actual needs, and the present invention does not impose further restrictions on this. As a preferred embodiment, the total metric value variation delta in the present invention is set to 3.

[0087] In some embodiments of the present invention, selecting a non-systematic code generator according to a coding rate indicator, and obtaining data to be decoded according to the non-systematic code generator includes:

[0088] When selecting a non-systematic code generator of a first rate according to the coding rate identifier, obtaining a first amount of data to be decoded;

[0089] When selecting a non-systematic code generator of a second rate according to the coding rate identifier, obtaining a second amount of data to be decoded;

[0090] When a non-systematic code generator of a third rate is selected according to the coding rate identifier, a third amount of data to be decoded is obtained.

[0091] In the above embodiment, the first rate, second rate, and third rate are 1 / 2 rate, 1 / 3 rate, and 1 / 4 rate, respectively, and the first quantity, second quantity, and third quantity are 2, 3, and 4, respectively. That is, when a 1 / 2 rate non-systematic code generator is selected, two data to be decoded are extracted and recorded as D0D1; when a 1 / 3 rate non-systematic code generator is selected, three data to be decoded are extracted and recorded as D0D1D2; and when a 1 / 4 rate non-systematic code generator is selected, four data to be decoded are extracted and recorded as D0D1D2D3.

[0092] In some embodiments of the present invention, performing convolution processing on shift data of a preset number of bits and a non-systematic code generator to obtain convolution coding includes:

[0093] Convolution processing is performed on the shifted data of a preset number of bits and a non-systematic code generator to obtain a first convolution code;

[0094] A first value and a second value are respectively added to the left end of the shifted data of the preset number of bits and convolved with a non-systematic code generator to obtain a second convolutional code and a third convolutional code.

[0095] In the above embodiment, the preset number of bits may be 1-N, the first value and the second value are 0 and 1 respectively, the convolutional coding module 150 takes the 1st to Nth bit data in the shift register 140, adds 0 or 1 to the left end of the data respectively, and performs convolution with the non-systematic code generator to obtain two groups of convolutional codes, which are respectively denoted as Tu0' (second convolutional code) and Tu1' (third convolutional code); the convolutional coding module 150 takes the 1st to Nth bit data in the shift register 140, performs convolution with the non-systematic code generator, and obtains a group of convolutional codes, which is denoted as Td' (first convolutional code); when the 1 / 2 rate non-systematic code generator is selected, Tu0', Tu1' and Td' are all 2-bit data consisting of 0 or 1, respectively denoted as (Tu When the 1 / 3 rate non-systematic code generator is selected, Tu0', Tu1' and Td' are all 3-bit data consisting of 0 or 1, and are recorded as (Tu00, Tu01, Tu02), (Tu10, Tu11, Tu12) and (Td0, Td1, Td2) respectively; when the 1 / 4 rate non-systematic code generator is selected, Tu0', Tu1' and Td' are all 4-bit data consisting of 0 or 1, and are recorded as (Tu00, Tu01, Tu02, Tu03), (Tu10, Tu11, Tu12, Tu13) and (Td0, Td1, Td2, Td3) respectively.

[0096] In some embodiments of the present invention, calculating a branch metric value based on a coding rate indicator, data to be decoded, and convolutional coding includes:

[0097] Calculating a first branch metric value based on a first rate, a first amount of data to be decoded, and a convolutional code;

[0098] Calculating a second branch metric value based on a second rate, a second amount of data to be decoded, and the convolutional code;

[0099] A third branch metric value is calculated according to a third rate, a third amount of data to be decoded, and convolutional coding.

[0100] In the above embodiment, when a non-systematic code generator of rate 1 / 2 is selected, the branch metrics corresponding to Tu0′, Tu1′, and Td′ can be respectively expressed as:

[0101] Tu0=(2×Tu00-1)×D0+(2×Tu01-1)×D1;

[0102] Tu1=(2×Tu10-1)×D0+(2×Tu11-1)×D1;

[0103] Td=(2×Td0-1)×D0+(2×Td1-1)×D1;

[0104] When a non-systematic code generator with a rate of 1 / 3 is selected, the branch metrics corresponding to Tu0', Tu1', and Td' can be expressed as:

[0105] Tu0=(3×Tu00-1)×D0+(3×Tu01-1)×D1+(3×Tu02-1)×D2;

[0106] Tu1=(3×Tu10-1)×D0+(3×Tu11-1)×D1+(3×Tu12-1)×D2;

[0107] Td=(3×Td0-1)×D0+(3×Td1-1)×D1+(3×Td2-1)×D2;

[0108] When a 1 / 4 rate non-systematic code generator is selected, the branch metrics corresponding to Tu0', Tu1', and Td' can be expressed as:

[0109] Tu0=(4×Tu00-1)×D0+(4×Tu01-1)×D1+(4×Tu02-1)×D2+(4×Tu03-1)×D3;

[0110] Tu1=(4×Tu10-1)×D0+(4×Tu11-1)×D1+(4×Tu12-1)×D2+(4×Tu13-1)×D3;

[0111] Td=(4×Td0-1)×D0+(4×Td1-1)×D1+(4×Td2-1)×D2+(4×Td3-1)×D3.

[0112] Through the above calculation, three branch metric values ​​Tu0, Tu1, and Td can be obtained.

[0113] In some embodiments of the present invention, determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value, includes:

[0114] When the sum of the branch metric value of the second convolutional coding and the total metric value is greater than zero, the decoding result of the to-be-decoded data is zero, and the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional coding;

[0115] When the sum of the branch metric value of the second convolutional code and the total metric value is less than or equal to zero, and the sum of the branch metric value of the third convolutional code and the total metric value is greater than zero, the decoding result of the to-be-decoded data is one, and the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional code;

[0116] When neither of the above two situations is met, if the number of nodes is zero or the number of nodes is greater than zero and the difference between the total metric value and the branch metric value of the first convolutional code is less than zero, then the total metric value is updated by the sum of the total metric value and the preset total metric value change; otherwise, go back to the previous node and update the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code.

[0117] In the above embodiment, when Tu0+Tsum>0, the decoding result of the data to be decoded is 0, and Tsum=Tu0+Tsum;

[0118] When Tu0+Tsum≤0 and Tu1+Tsum>0, the decoding result of the data to be decoded is 1, Tsum=Tu1+Tsum;

[0119] When both of the above conditions are not satisfied, if (Num=0) or (Num>0 and Tsum-Td<0), then take Tsum=Tsum+delta; otherwise, go back to the previous node and take Tsum=Tsum-Td.

[0120] In some embodiments of the present invention, updating the shift data in the shift register 140 according to the updated total metric value includes:

[0121] When the total metric value is updated by adding the sum of the total metric value and the branch metric value of the second convolutional code, zero is shifted rightward into the shift register 140, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0122] When the total metric value is updated by adding the sum of the total metric value and the branch metric value of the third convolutional code, one is shifted rightward into the shift register 140, the number of nodes is incremented by one, and the number of calculations is incremented by one;

[0123] When the total metric value is updated by the difference between the total metric value and the branch metric value of the first convolutional code, zero is shifted leftward into the shift register 140, the number of nodes is decremented by one, and the number of calculations is incremented by one;

[0124] When the total metric value is updated by adding the total metric value and the preset total metric value change, the number of calculations is incremented by one.

[0125] In the above embodiment, when Tsum=Tu0+Tsum, 0 is shifted rightward into the shift register 140; the number of nodes Num is incremented by 1, and the number of calculations T is incremented by 1;

[0126] When Tsum=Tu1+Tsum, 1 is shifted rightward into the shift register 140; the number of nodes Num is incremented by 1, and the number of calculations T is incremented by 1;

[0127] When Tsum=Tsum-Td, 0 is shifted leftward into the shift register 140; the number of nodes Num is decremented by 1, and the number of calculations T is incremented by 1;

[0128] When Tsum=Tsum+delta, the number of calculations T is incremented by 1.

[0129] Determine whether the number of nodes Num is equal to the length of the decoded information. If so, the decoding is completed and the main control module 160 takes out the result in the shift register 140. Otherwise, determine whether the number of calculations T is less than the set threshold value. If so, re-acquire the data to be decoded and continue decoding. Otherwise, the decoding is considered unsuccessful and the main control module 160 gives a decoding overflow flag.

[0130] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of a multi-rate convolutional code sequence decoding device provided in an embodiment of the present invention. Based on the above-described multi-rate convolutional code sequence decoding method, the present invention also provides a multi-rate convolutional code sequence decoding device. The multi-rate convolutional code sequence decoding device can be a computing device such as a mobile terminal, desktop computer, notebook, PDA, or server. The multi-rate convolutional code sequence decoding device 300 includes a processor 310, a memory 320, and a display 330. Figure 3 Only some components of the synchronous tracking flying welding equipment for real-time measurement of battery height are shown, but it should be understood that it is not required to implement all the shown components, and more or fewer components may be implemented instead.

[0131] In some embodiments, the memory 320 may be an internal storage unit of the multi-rate convolutional code sequence decoding device 300, such as a hard disk or memory of the multi-rate convolutional code sequence decoding device 300. In other embodiments, the memory 320 may also be an external storage device of the multi-rate convolutional code sequence decoding device 300, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped with the multi-rate convolutional code sequence decoding device 300. Furthermore, the memory 320 may include both the internal storage unit of the multi-rate convolutional code sequence decoding device 300 and an external storage device. The memory 320 is used to store application software installed in the multi-rate convolutional code sequence decoding device 300 and various data, such as the program code for installing the multi-rate convolutional code sequence decoding device 300. The memory 320 may also be used to temporarily store data that has been output or is about to be output. In one embodiment, the memory 320 stores a multi-rate convolutional code sequence decoding program 340, which can be executed by the processor 310 to implement the multi-rate convolutional code sequence decoding method of each embodiment of the present application.

[0132] In some embodiments, the processor 310 may be a central processing unit (CPU), a microprocessor, or other data processing chip, configured to execute program codes stored in the memory 320 or process data, such as executing a multi-rate convolutional code sequence decoding method.

[0133] In some embodiments, display 330 can be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen. Display 330 is used to display information on multi-rate convolutional code sequence decoding device 300 and to display a visual user interface. Components 310-330 of multi-rate convolutional code sequence decoding device 300 communicate with each other via a system bus.

[0134] In one embodiment, when the processor 310 executes the multi-rate convolutional code sequence decoding program 340 in the memory 320 , the steps in the multi-rate convolutional code sequence decoding method described above are implemented.

[0135] This embodiment further provides a computer-readable storage medium having a multi-rate convolutional code sequence decoding program stored thereon. When the multi-rate convolutional code sequence decoding program is executed by a processor, the following steps are implemented:

[0136] Receive and store the coding rate identification bit and the data to be decoded in the input data;

[0137] Selecting a non-systematic code generator according to the coding rate identifier, and obtaining data to be decoded according to the non-systematic code generator;

[0138] Performing convolution processing on the shift data of a preset number of bits and a non-systematic code generator to obtain a convolution code;

[0139] Calculating a branch metric value according to a coding rate flag, data to be decoded, and a convolutional code;

[0140] Determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value;

[0141] The shift data in the shift register 140 is updated according to the updated total metric value.

[0142] In summary, the present invention provides a multi-rate convolutional code sequence decoder 100. The data storage module 110 is capable of receiving and storing large amounts of input data, including coding rate identifiers and data to be decoded, providing a reliable data source for subsequent processing. The convolutional coding module 150 selects non-systematic code generators based on the coding rate identifiers and performs convolution processing to generate convolutional codes. This allows the system to flexibly adjust to different coding rate requirements, improving data processing efficiency. The branch metric module 120 calculates branch metrics based on the non-systematic code generators, coding rate identifiers, and data to be decoded, providing accurate decoding information for the parallel processing module 130. The parallel processing module 130 uses the branch metrics and total metrics to determine the decoding result and update the total metric. This parallel processing approach improves decoding speed and accuracy and reduces decoding error rates. The main control module 160 updates the shift data in the shift register 140 based on the updated total metric value, achieving dynamic data updating and optimization. This enables the system to adaptively adjust to different decoding results and states, improving system stability and performance. By integrating the data storage module 110, the branch metric module 120, the parallel processing module 130, the shift register 140, the convolutional coding module 150 and the main control module 160, it is possible to select non-systematic code generators according to different coding rate identification bits and support complex convolutional coding and decoding algorithms.

[0143] The present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above method. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a microdrive, a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0144] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0145] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interface, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.

[0147] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0148] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0149] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0150] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0151] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure herein, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not recorded in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0152] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A multi-rate convolutional code sequence decoder, characterized in that: include: a data storage module, a branch metric module, a parallel processing module, a shift register, a convolutional coding module, and a main control module; the main control module is respectively connected to the data storage module, the branch metric module, the parallel processing module, the shift register, and the convolutional coding module; the parallel processing module is connected to the branch metric module; the convolutional coding module is respectively connected to the branch metric module and the shift register; Wherein, the data storage module is used to receive and store the coding rate identification bit and the data to be decoded in the input data; The convolutional coding module is configured to select a non-systematic code generator according to the coding rate identification bit, and perform convolution processing on the shifted data of a preset number of bits and the non-systematic code generator to obtain a convolutional code; The branch metric module is used to obtain the data to be decoded according to the non-systematic code generator, and calculate the branch metric value according to the coding rate identifier, the data to be decoded and the convolutional code; The parallel processing module is used to determine the decoding result of the data to be decoded according to the branch metric value and the total metric value, and update the total metric value; The main control module is used to update the shift data in the shift register according to the updated total metric value; The shift register is used to store shift data.

2. A method for decoding a multi-rate convolutional code sequence, based on the multi-rate convolutional code sequence decoder according to claim 1, characterized in that: include: Receive and store the coding rate identification bit and the data to be decoded in the input data; selecting a non-systematic code generator according to the coding rate identifier, and obtaining data to be decoded according to the non-systematic code generator; Performing convolution processing on the shift data of a preset number of bits and the non-systematic code generator to obtain convolution code; Calculating a branch metric value according to the coding rate identifier, the data to be decoded, and the convolutional coding; Determining a decoding result of the data to be decoded according to the branch metric value and the total metric value, and updating the total metric value; The shift data in the shift register is updated according to the updated total metric value.

3. The method for decoding a multi-rate convolutional code sequence according to claim 2, wherein: The receiving and storing of the coding rate identification bit and the data to be decoded in the input data, then includes: initializing the parameters of the multi-rate convolutional code sequence decoder; specifically including: Initialize the shift register to zero; initialize the number of nodes and the number of calculations stored in the main control module to zero; initialize the total metric value stored in the parallel processing module to zero; and set a preset total metric value change.

4. The method for decoding a multi-rate convolutional code sequence according to claim 3, wherein: The selecting a non-systematic code generator according to the coding rate identifier, and obtaining data to be decoded according to the non-systematic code generator, includes: When selecting a non-systematic code generator of a first rate according to the coding rate identifier, obtaining a first amount of data to be decoded; When selecting a non-systematic code generator of a second rate according to the coding rate identifier, obtaining a second amount of data to be decoded; When a non-systematic code generator of a third rate is selected according to the coding rate identifier, a third amount of data to be decoded is obtained.

5. The method for decoding a multi-rate convolutional code sequence according to claim 4, wherein: The convolution processing of the shifted data according to the preset number of bits and the non-systematic code generator to obtain the convolution code includes: Performing convolution processing on the shifted data of a preset number of bits and the non-systematic code generator to obtain a first convolution code; A first value and a second value are respectively added to the left end of the shifted data of the preset number of bits, and convolution processing is performed with the non-systematic code generator to obtain a second convolution code and a third convolution code.

6. The method for decoding a multi-rate convolutional code sequence according to claim 5, wherein: The calculating the branch metric value according to the coding rate identifier, the data to be decoded, and the convolutional coding includes: Calculating a first branch metric value based on the first rate, the first amount of data to be decoded, and the convolutional coding; calculating a second branch metric value based on the second rate, the second amount of data to be decoded, and the convolutional coding; A third branch metric value is calculated according to the third rate, the third amount of data to be decoded, and the convolutional coding.

7. The method for decoding a multi-rate convolutional code sequence according to claim 5, wherein: Determining a decoding result of the to-be-decoded data according to the branch metric value and the total metric value, and updating the total metric value, including: When the sum of the branch metric value of the second convolutional encoding and the total metric value is greater than zero, the decoding result of the to-be-decoded data is zero, and the total metric value is updated by the sum of the total metric value and the branch metric value of the second convolutional encoding; When the sum of the branch metric value and the total metric value of the second convolutional coding is less than or equal to zero, and the sum of the branch metric value and the total metric value of the third convolutional coding is greater than zero, the decoding result of the to-be-decoded data is one, and the total metric value is updated by the sum of the total metric value and the branch metric value of the third convolutional coding; When neither of the above two situations is met, if the number of nodes is zero or the number of nodes is greater than zero and the difference between the total metric value and the branch metric value of the first convolutional code is less than zero, then the total metric value is updated by the sum of the total metric value and the preset total metric value change; otherwise, go back to the previous node and update the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code.

8. The method for decoding a multi-rate convolutional code sequence according to claim 7, wherein: Updating the shift data in the shift register according to the updated total metric value includes: When updating the total metric value by adding the sum of the total metric value and the branch metric value of the second convolutional code, zero is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one; When updating the total metric value by the sum of the total metric value and the branch metric value of the third convolutional code, one is shifted rightward into the shift register, the number of nodes is incremented by one, and the number of calculations is incremented by one; When updating the total metric value by the difference between the total metric value and the branch metric value of the first convolutional code, zero is shifted leftward into the shift register, the number of nodes is decremented by one, and the number of calculations is incremented by one; When the total metric value is updated by the sum of the total metric value and the preset total metric value change, the number of calculations is increased by one.

9. A multi-rate convolutional code sequence decoding device, characterized in that: The method comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of the multi-rate convolutional code sequence decoding method according to any one of claims 2 to 8.

10. A storage medium, characterized in that: It stores a computer program executable by an access authentication device. When the computer program runs on the access authentication device, the access authentication device executes the steps of the multi-rate convolutional code sequence decoding method according to any one of claims 2 to 8.

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