Preparation method of solar cell and solar cell

Abstract

The invention provides a preparation method of a solar cell and the solar cell, and the method comprises the steps: firstly, providing an initial wafer; processing the initial wafer by adopting a laser process to obtain a substrate layer of which the first surface is provided with a plurality of groove regions and non-groove regions; a first tunneling dielectric layer is formed on the first surface, and the thickness of the first tunneling dielectric layer located in the groove area is larger than that of the first tunneling dielectric layer located in the non-groove area; then, an amorphous silicon layer is formed on the side, away from the substrate layer, of the first tunneling dielectric layer, and the thickness of the amorphous silicon layer located in the groove area is larger than that of the amorphous silicon layer located in the non-groove area; carrying out doping treatment on the amorphous silicon layer to obtain a doped layer; and finally, forming a first electrode on a part of the surface of the groove region. The preparation method of the solar cell can improve the performance of the solar cell.

Description

Technical Field

[0001] The present application relates to the field of solar cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] Tunnel Oxide Passivated Contact (TOPCON) is a technology used to improve the efficiency of solar cells. It forms a tunnel dielectric layer on the surface of the cell, thereby reducing surface recombination and improving the open circuit voltage and overall efficiency of the cell. Summary of the invention

[0003] The main purpose of the present invention is to provide a method for preparing a solar cell and a solar cell, so as to solve the problem of how to improve the performance of the solar cell in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a method for preparing a solar cell is provided, comprising: providing an initial wafer; processing the initial wafer by a laser process to obtain a base layer having a plurality of groove areas and non-groove areas on the first surface; forming a first tunneling dielectric layer on the first surface, wherein the thickness of the first tunneling dielectric layer located in the groove area is greater than the thickness of the first tunneling dielectric layer located in the non-groove area; forming an amorphous silicon layer on a side of the first tunneling dielectric layer away from the base layer, wherein the thickness of the amorphous silicon layer located in the groove area is greater than the thickness of the amorphous silicon layer located in the non-groove area; performing doping treatment on the amorphous silicon layer to obtain a doped layer; and forming a first electrode on a partial surface of the groove area.

[0005] Further, forming a first tunnel dielectric layer on the first surface includes: depositing a plurality of sub-dielectric layers on the first surface in sequence, the plurality of sub-dielectric layers forming the first tunnel dielectric layer, and in the formation process of two adjacent sub-dielectric layers, the deposition gas pressures corresponding to the sub-dielectric layers are different.

[0006] Furthermore, an amorphous silicon layer is formed on a side of the first tunneling dielectric layer away from the base layer, comprising: depositing a plurality of sub-amorphous silicon layers in sequence on the first surface, the plurality of sub-amorphous silicon layers forming the amorphous silicon layer, and in the formation process of two adjacent sub-amorphous silicon layers, the deposition gas pressures corresponding to the sub-amorphous silicon layers are different.

[0007] Furthermore, the amorphous silicon layer is doped to obtain a doped layer, including: doping the amorphous silicon layer located in the groove area to form a first doped area, the doping type of the first doped area is different from the doping type of the base layer; doping the amorphous silicon layer located in the non-groove area to form a second doped area, the doping type of the second doped area is different from the doping type of the base layer, the first doped area and the second doped area form the doped layer, and the doping concentration of the first doped area is greater than the doping concentration of the second doped area.

[0008] Furthermore, the method further comprises: sequentially forming a second tunnel dielectric layer, a passivation layer and a second electrode on the second surface, and the base layer has the first surface and the second surface opposite to each other.

[0009] Furthermore, the laser wavelength of the laser process is 500-560 nm, the laser power of the laser process is 20-40 W, the laser frequency of the laser process is 200-400 kHz, and the laser engraving speed of the laser process is 25000-35000 mm / s.

[0010] Furthermore, the depth of the groove area is 6-8 μm.

[0011] Furthermore, the thickness of the first tunnel dielectric layer in the groove region is 1.8 to 2.2 μm, and the thickness of the first tunnel dielectric layer in the non-groove region is 1.5 to 1.8 μm.

[0012] Furthermore, the thickness of the amorphous silicon layer in the groove area is 150-160 nm, and the thickness of the amorphous silicon layer in the non-groove area is 130-150 nm.

[0013] In order to achieve the above objective, according to one aspect of the present invention, a solar cell is provided. The solar cell is prepared by any one of the above methods for preparing a solar cell.

[0014] Applying the technical solution of the present invention, in the above-mentioned preparation method, first, an initial wafer is provided; the initial wafer is processed by a laser process to obtain a substrate layer having a plurality of groove areas and non-groove areas on the first surface; a first tunnel dielectric layer is formed on the first surface, wherein the thickness of the first tunnel dielectric layer in the groove area is greater than the thickness of the first tunnel dielectric layer in the non-groove area; then, an amorphous silicon layer is formed on the side of the first tunnel dielectric layer away from the substrate layer, wherein the thickness of the amorphous silicon layer in the groove area is greater than the thickness of the amorphous silicon layer in the non-groove area; the amorphous silicon layer is then doped to obtain a doped layer; finally, a first electrode is formed on a part of the surface of the groove area. In this solution, on the one hand, in the process of forming the first tunnel dielectric layer, the thickness of the first tunnel dielectric layer in the groove area is greater than the thickness of the first tunnel dielectric layer in the non-groove area, so that a thicker first tunnel dielectric layer can be formed in the groove area of ​​the substrate layer. Since surface recombination usually occurs at surface defects or interfaces, a thicker tunnel dielectric layer can passivate these defects, thereby reducing the surface recombination rate, which helps to improve the open circuit voltage and fill factor of the solar cell, thereby improving the overall photoelectric conversion efficiency. On the other hand, in the process of forming the amorphous silicon layer, the thickness of the amorphous silicon layer located in the groove area is greater than the thickness of the amorphous silicon layer located in the non-groove area, so that a thicker polysilicon layer can be formed in the groove area, and its crystal quality can be optimized and the defect density can be reduced to improve the carrier transmission characteristics, which is helpful to reduce the series resistance and reduce the energy loss in the transmission process, thereby increasing the short-circuit current density. On the other hand, by using a laser process to process the initial wafer, the back side is grooved to reserve the fine grid position, and the subsequent laser-assisted sintering of the fine grid can reduce the contact resistance and increase the carrier collection probability. The fine grid is hidden by coating and the main grid is printed after coating, thereby enhancing the contact performance between the fine grid and the metal electrode and the silicon substrate without changing the number of grid lines, reducing the back surface reflectivity, and improving the photoelectric conversion efficiency of the battery. The above method can improve the performance of solar cells by combining the improvement of photoelectric conversion efficiency and the improvement of short-circuit current density, and solves the problem of how to improve the performance of solar cells in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0016] Figure 1 A schematic diagram of a process for preparing a solar cell provided in accordance with an embodiment of the present application is shown;

[0017] Figure 2 A schematic structural diagram of a solar cell provided according to an embodiment of the present application is shown.

[0018] The above drawings include the following reference numerals:

[0019] 10. Base layer; 11. First tunnel dielectric layer; 12. Doping layer; 13. First electrode; 14. Second tunnel dielectric layer; 15. Passivation layer; 16. Second electrode. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] As introduced in the background technology, the performance of solar cells in the prior art is poor. In order to solve the above technical problems, the present application proposes a method for preparing a solar cell and a solar cell.

[0024] Figure 1 FIG. 1 is a flow chart of a method for preparing a solar cell according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0025] Step S201, providing an initial wafer;

[0026] Specifically, the material of the initial wafer may be a silicon substrate, and the material of the silicon substrate may include single crystal silicon, polycrystalline silicon, amorphous silicon and microcrystalline silicon.

[0027] Step S202, using a laser process to process the initial wafer to obtain a base layer 10 having a plurality of groove areas and non-groove areas on the first surface;

[0028] Specifically, the laser used in the laser process can be any one of infrared laser, green laser, and ultraviolet laser, and the laser used in the laser process can be any one of CO2 laser, excimer laser, titanium sapphire laser, and semiconductor laser. The substrate layer 10 is used to receive incident light and generate photogenerated carriers. In some embodiments, the solar cell is a double-sided cell, that is, the first surface and the opposite surface are both used to receive sunlight.

[0029] Step S203, forming a first tunnel dielectric layer 11 on the first surface, wherein the thickness of the first tunnel dielectric layer 11 in the groove area is greater than the thickness of the first tunnel dielectric layer 11 in the non-groove area;

[0030] In some embodiments, the first tunnel dielectric layer 11 may be formed by a deposition process, for example, a chemical vapor deposition process may be used. In other embodiments, when the material of the first tunnel dielectric layer 11 is silicon oxide, an in-situ growth process may be used to form the first tunnel dielectric layer 11, for example, a thermal oxidation process and a nitric acid passivation process may be used to in-situ generate the first tunnel dielectric layer 11 on the first surface. The first tunnel dielectric layer 11 may constitute a passivation contact layer together with the doping layer 12 formed subsequently, and the first tunnel dielectric layer 11 is used to achieve the interface passivation of the first surface, thereby achieving the effect of chemical passivation. Specifically, by saturating the dangling bonds of the first surface, the interface defect state density of the first surface is reduced, thereby reducing the recombination center of the first surface to reduce the carrier recombination rate. The material of the first tunnel dielectric layer 11 may be a dielectric material, for example, any one of silicon oxide, magnesium fluoride, silicon oxide, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide.

[0031] Step S204, forming an amorphous silicon layer on a side of the first tunnel dielectric layer 11 away from the base layer 10, wherein the thickness of the amorphous silicon layer in the groove area is greater than the thickness of the amorphous silicon layer in the non-groove area;

[0032] Specifically, the amorphous silicon layer is used for subsequent doping treatment to form a polycrystalline silicon layer.

[0033] Step S205, performing doping treatment on the amorphous silicon layer to obtain a doped layer 12;

[0034] Specifically, for example, a plasma chemical vapor deposition method can be used to form an amorphous silicon layer; and a doping process can be used to treat the amorphous silicon layer. The amorphous silicon layer is doped with P-type or N-type ions to transform it into a doped amorphous silicon layer. Specifically, the amorphous silicon layer can be doped by any process of ion implantation or thermal diffusion. It is understandable that in some embodiments, only an amorphous silicon layer can be formed, and then the amorphous silicon layer can be directly laser-treated to transform the amorphous silicon layer into a polycrystalline silicon layer, and then the polycrystalline silicon layer can be doped by a doping process to form a doped polycrystalline silicon layer.

[0035] Step S206, forming a first electrode 13 on a portion of the surface of the groove area, and obtaining Figure 2 The structure shown.

[0036] Specifically, the first electrode 13 is electrically connected to the above-mentioned doping layer 12, and the width of the above-mentioned doping layer 12 is not less than the width of the first electrode 13, so that the first electrode 13 can be covered by the doping layer 12, so that the side and bottom surfaces of the first electrode 13 are in contact with the doping layer 12, thereby further reducing the carrier recombination between the first electrode 13 and the doping layer 12, and improving the passivation effect. In addition, setting the width of the doping layer 12 to be larger is also conducive to increasing the process window for forming the contact between the first electrode 13 and the doping layer 12. The steps of forming the first electrode 13 are as follows: metallizing a portion of the surface of the groove area, including a screen printing process and a high-temperature sintering process, to form an electrical connection between the first electrode 13 and the doping layer 12. Specifically, a screen printing process can be used to print a metallization paste on a portion of the surface of the groove area and sinter to form the first electrode 13.

[0037] In the above preparation method, first, an initial wafer is provided; the initial wafer is processed by a laser process to obtain a substrate layer having a plurality of groove areas and non-groove areas on the first surface; a first tunnel dielectric layer is formed on the first surface, wherein the thickness of the first tunnel dielectric layer in the groove area is greater than the thickness of the first tunnel dielectric layer in the non-groove area; then, an amorphous silicon layer is formed on the side of the first tunnel dielectric layer away from the substrate layer, wherein the thickness of the amorphous silicon layer in the groove area is greater than the thickness of the amorphous silicon layer in the non-groove area; the amorphous silicon layer is then doped to obtain a doped layer; finally, a first electrode is formed on a portion of the surface of the groove area. In this scheme, on the one hand, in the process of forming the first tunnel dielectric layer, the thickness of the first tunnel dielectric layer in the groove area is greater than the thickness of the first tunnel dielectric layer in the non-groove area, so that a thicker first tunnel dielectric layer can be formed in the groove area of ​​the substrate layer. Since surface recombination usually occurs at surface defects or interfaces, a thicker tunnel dielectric layer can passivate these defects, thereby reducing the surface recombination rate, which helps to improve the open circuit voltage and fill factor of the solar cell, thereby improving the overall photoelectric conversion efficiency. On the other hand, in the process of forming the amorphous silicon layer, the thickness of the amorphous silicon layer located in the groove area is greater than the thickness of the amorphous silicon layer located in the non-groove area, so that a thicker polysilicon layer can be formed in the groove area, and its crystal quality can be optimized and the defect density can be reduced to improve the carrier transmission characteristics, which is helpful to reduce the series resistance and reduce the energy loss in the transmission process, thereby increasing the short-circuit current density. On the other hand, by using a laser process to process the initial wafer, the back side is grooved to reserve the fine grid position, and the subsequent laser-assisted sintering of the fine grid can reduce the contact resistance and increase the carrier collection probability. The fine grid is hidden by coating and the main grid is printed after coating, thereby enhancing the contact performance between the fine grid and the metal electrode and the silicon substrate without changing the number of grid lines, reducing the back surface reflectivity, and improving the photoelectric conversion efficiency of the battery. The above method can improve the performance of solar cells by combining the improvement of photoelectric conversion efficiency and the improvement of short-circuit current density, and solves the problem of how to improve the performance of solar cells in the prior art.

[0038] In a specific implementation of the present application, the above step S203 can be implemented by the following steps: Step S2031, depositing multiple sub-dielectric layers on the above first surface in sequence, the multiple sub-dielectric layers form the above first tunnel dielectric layer, and in the formation process of two adjacent sub-dielectric layers, the deposition gas pressures corresponding to the above sub-dielectric layers are different. This method can further improve the accuracy of forming the above first tunnel dielectric layer in the groove area and the non-groove area.

[0039] Specifically, the above-mentioned sub-dielectric layer can be deposited by LPECVD (Low Pressure / Pressure Enhanced Chemical Vapor Deposition). The LPECVD process is carried out at a relatively low pressure, which is conducive to increasing the mean free path of gas molecules, thereby increasing the deposition rate. At the same time, by precisely controlling the deposition conditions (such as pressure, temperature, gas flow rate, etc.), a first tunneling dielectric layer with better uniformity and higher quality can be deposited. In practical applications, the above-mentioned process can be repeated for multiple steps, and high and low pressures are alternately interlaced between adjacent process steps, so that the process gas in the furnace flows fully, and the deposition process of the sub-dielectric layer is finely controlled, thereby forming a differential thickness and quality in the groove area and the non-groove area, and finally forming multiple sub-dielectric layers. Specifically, the number of the above-mentioned sub-dielectric layers can be 3 to 5.

[0040] In another specific embodiment, the number of the above-mentioned sub-dielectric layers is 5, and the formation process of the above-mentioned first tunnel dielectric layer is as follows: the oxidation time of the first sub-dielectric layer is 60 to 90 seconds, the temperature is 580 to 590° C., the pressure is 760,000 mtorr, and the oxygen flow rate is 36,000 sccm; the oxidation time of the second sub-dielectric layer is 160 to 220 seconds, the temperature is 600 to 610° C., the pressure is 350,000 to 450,000 mtorr, and the oxygen flow rate is 10,000 to 15,000 sccm; the oxidation time of the third sub-dielectric layer is The oxidation time of the fourth sub-dielectric layer is 160-220s, the temperature is 610-620°C, the pressure is 550,000-650,000 mtorr, and the oxygen flow rate is 10,000-15,000 sccm; the oxidation time of the fifth sub-dielectric layer is 60-90s, the temperature is 600-610°C, the pressure is 760,000 mtorr, and the oxygen flow rate is 36,000 sccm.

[0041] In a specific implementation method of the present application, the above step S204 can be implemented by the following steps: Step S2041, depositing multiple sub-amorphous silicon layers on the above first surface in sequence, the multiple sub-amorphous silicon layers form the above amorphous silicon layer, and in the process of forming two adjacent sub-amorphous silicon layers, the deposition gas pressures corresponding to the above sub-amorphous silicon layers are different. This method can further improve the accuracy of forming the above amorphous silicon layer in the groove area and the non-groove area.

[0042] Specifically, the above-mentioned sub-amorphous silicon layer can be deposited by LPECVD. In practical applications, multiple steps of the above-mentioned process can be repeated, and high and low pressures are alternated between adjacent process steps, so that the process gas in the furnace flows fully, and the deposition process of the sub-amorphous silicon layer is finely controlled, so as to form a different thickness and quality in the groove area and the non-groove area, and finally form multiple amorphous silicon layers. Specifically, the number of the above-mentioned sub-amorphous silicon layers can be 3 to 5.

[0043] In another specific embodiment, the number of the above-mentioned amorphous silicon sub-layers is 5, and the formation process of the above-mentioned amorphous silicon layers is as follows: the oxidation time of the first amorphous silicon sub-layer is 100-300s, the temperature is 580-590°C, the pressure is 240-360mtorr, the flow rate of SiH4 at the furnace mouth is 500-600sccm, and the flow rate of SiH4 at the furnace tail is 700-800sccm; the oxidation time of the second amorphous silicon sub-layer is 50-150s, the temperature is 600-610°C, the pressure is 60-120mtorr, the flow rate of SiH4 at the furnace mouth is 350-450sccm, and the flow rate of SiH4 at the furnace tail is 550-650sccm; the oxidation time of the third amorphous silicon sub-layer is 300-600s, the temperature is 590- 600℃, pressure of 80~140mtorr, flow rate of SiH4 at furnace mouth is 350~450sccm, and flow rate of SiH4 at furnace tail is 550~650sccm; the oxidation time of the fourth sub-amorphous silicon layer is 150~250s, temperature is 610~620℃, pressure is 240~360mtorr, flow rate of SiH4 at furnace mouth is 500~600sccm, and flow rate of SiH4 at furnace tail is 700~800sccm; the oxidation time of the fifth sub-amorphous silicon layer is 600~900s, temperature is 600~610℃, pressure is 180~300mtorr, flow rate of SiH4 at furnace mouth is 400~500sccm, and flow rate of SiH4 at furnace tail is 600~700sccm.

[0044] The above step S205 can be specifically implemented by the following steps: step S2051, doping the above amorphous silicon layer located in the above groove area to form a first doping area, and the doping type of the above first doping area is different from the doping type of the above base layer; step S2052, doping the above amorphous silicon layer located in the above non-groove area to form a second doping area, and the doping type of the above second doping area is different from the doping type of the above base layer, and the above first doping area and the above second doping area form the above doping layer, and the doping concentration of the above first doping area is greater than the doping concentration of the above second doping area. The different doping concentrations of the above first doping area and the second doping area can further optimize the electrical performance of the battery and improve the photoelectric conversion efficiency.

[0045] Specifically, the above-mentioned doping treatment can be N-type doping ions, for example, it can be any one of phosphorus, arsenic or antimony. The above-mentioned different doping concentrations have different advantages in solar cells. The doping concentration of the above-mentioned first doping region is greater than the doping concentration of the above-mentioned second doping region. Therefore, the first doping region is a heavily doped region, which can significantly improve the conductivity and electrical properties, and the second doping region is a lightly doped region, which can improve the doping uniformity and stress. After doping amorphous silicon, a polycrystalline silicon layer is formed. Since polycrystalline silicon can form a good ohmic contact, the contact resistance is reduced and the current collection efficiency is improved. The heavily doped region can reduce the metal contact resistance and effectively improve the fill factor. The lightly doped region can reduce the recombination enhancement caused by the internal expansion of phosphorus doping, further reduce the recombination of carriers, and improve the open circuit voltage and short circuit current of the battery. In another specific embodiment, the above-mentioned amorphous silicon layer includes a plurality of sub-amorphous silicon layers, and multiple doping processes can be used to dope each of the above-mentioned sub-amorphous silicon layers in turn to obtain a plurality of sub-doped layers, and then form the above-mentioned doped layer.

[0046] The method further comprises: step S207, forming a second tunnel dielectric layer 14, a passivation layer 15 and a second electrode 16 in sequence on the second surface, wherein the base layer 10 has the first surface and the second surface opposite to each other, and obtaining Figure 2 The method further forms a second tunnel dielectric layer, a passivation layer and a second electrode on the second surface, which can further improve the integrity of the solar cell.

[0047] Specifically, in some embodiments, a deposition process can be used to form the second tunnel dielectric layer, for example, a chemical vapor deposition process can be used. In other embodiments, when the material of the second tunnel dielectric layer is silicon oxide, an in-situ growth process can also be used to form the second tunnel dielectric layer, for example, a thermal oxidation process and a nitric acid passivation process can be used to generate the second tunnel dielectric layer in situ on the first surface. The above-mentioned passivation layer can have a good passivation effect, so that the carrier concentration of the second surface is higher, the carrier recombination is suppressed, the open circuit voltage, short circuit current and fill factor of the solar cell are increased, and the double-sided photoelectric conversion rate is increased. In some embodiments, the material of the above-mentioned passivation layer can be one or more of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride or carbon nitride silicon oxide. Specifically, in some embodiments, the passivation layer can be a single-layer structure or a multi-layer structure. Specifically, the passivation layer can be formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) method. The steps of forming the second electrode are as follows: metallizing the surface of the second passivation layer, including screen printing and high temperature sintering, to form an electrical connection of the second electrode. Specifically, the metallization paste can be printed on the surface of the passivation layer by screen printing and sintering to form the second electrode.

[0048] In order to further improve the photoelectric conversion efficiency of solar cells, in a specific implementation of the present application, after the above step S202 and before the above step S203, it also includes: step S208, performing a texturing treatment on the above base layer.

[0049] In practical applications, the base layer can also be double-sided textured. For example, the pyramid velvet surface can be prepared by wet chemical etching, and the two surfaces of the base layer are set as pyramid velvet surfaces, so that the reflectivity of the two surfaces of the base layer to the incident light is small, so that the absorption utilization rate of the incident light is large, so that the photoelectric conversion efficiency of the solar cell is high. Specifically, in some embodiments, the base layer is an N-type semiconductor base, and an alkaline solution can be used for texture, for example, it can be a NaOH solution, and the corrosion of the NaOH solution is anisotropic, which is conducive to the preparation of a pyramid-shaped structure. In some embodiments, the pyramid-shaped structure can be a tetrahedron, a near-tetrahedron, a pentahedron, a near-pentahedron and other structures. It is understandable that in other embodiments, chemical etching, laser etching, mechanical method and plasma etching can also be used to prepare the pyramid velvet surface. After the texture is made, the base layer is cleaned to further remove impurities or foreign matter. In another embodiment, after the texture is made, high-temperature oxidation is performed to further repair laser damage, improve surface passivation, improve contact quality, enhance structural stability and optimize electrical properties.

[0050] In some specific embodiments, the laser wavelength of the above laser process is 500-560nm, the laser power of the above laser process is 20-40W, the laser frequency of the above laser process is 200-400kHz, and the laser engraving speed of the above laser process is 25000-35000mm / s. The laser wavelength, laser power, laser frequency and laser engraving speed of the above laser process will affect the depth of the laser reaching the initial wafer and the degree of crystallization. Setting the laser wavelength, laser power, laser frequency and laser engraving speed of the laser process within the above range can ensure that the laser used for laser heat treatment has sufficiently high heat, thereby further improving the grooving efficiency of forming the groove area.

[0051] In some embodiments, the laser wavelength may be, for example, 500-510 nm, 510-520 nm, 520-530 nm, 530-540 nm, and 540-550 nm, the laser power may be, for example, 20-30 W, 30-40 W, and 40-50 W, the laser frequency may be, for example, 200-250 kHz, 250-300 kHz, 300-350 kHz, and 350-400 kHz, and the laser engraving speed may be, for example, 25000-28000 mm / s, 28000-32000 mm / s, and 32000-35000 mm / s. In addition, within this range, the laser power should not be too large, so as to prevent the problem of damage to the surface of the initial wafer caused by excessive laser processing power. It is worth noting that the numerical ranges of laser wavelength, laser power, laser frequency and laser engraving speed referred to here are the laser wavelength range, laser power range, laser frequency range and laser engraving speed range for each laser processing, that is, no matter how many laser processes are performed, the laser wavelength, laser power, laser frequency and laser engraving speed range of each laser process are within the above numerical ranges.

[0052] In some other embodiments, the depth of the groove area is 6 to 8 μm. This method can further ensure that in the subsequent production process of the first electrode, the first electrode is directly filled into the groove area pre-made on the first surface of the substrate layer, which can significantly reduce the contact resistance between the metal and silicon, thereby further improving the overall performance of the cell.

[0053] Specifically, the depth of the groove area can be, for example, 6-7 μm and 7-8 μm. In addition, the depth range design of the groove area helps to enhance the bonding force between the metal electrode and the silicon wafer, so that the cell can still maintain good electrical performance and mechanical strength in harsh environments such as high temperature and high humidity. The width of the groove area ranges from 20 to 90 μm. In actual applications, the width and depth of the main grid and the fine grid are not the same. The width of the main grid is greater than the width of the fine grid, and the groove depth of the main grid is less than the groove depth of the fine grid.

[0054] In another embodiment, the thickness of the first tunnel dielectric layer in the groove region is 1.8 to 2.2 μm, and the thickness of the first tunnel dielectric layer in the non-groove region is 1.5 to 1.8 μm. Within the above thickness range, the first tunnel dielectric layer in the groove region will not be too thick, and the first tunnel dielectric layer in the non-groove region will not be too thin, while further taking into account the tunneling efficiency and photoelectric conversion efficiency of the solar cell.

[0055] Specifically, the thickness of the first tunnel dielectric layer in the groove region may be, for example, 1.8-1.9 μm, 1.9-2.0 μm, 2.0-2.1 μm, and 2.1-2.2 μm. The thickness of the first tunnel dielectric layer in the non-groove region may be, for example, 1.5-1.6 μm, 1.6-1.7 μm, and 1.7-1.8 μm. Specifically, the ratio of the thickness of the first tunnel dielectric layer in the groove region to the thickness of the first tunnel dielectric layer in the non-groove region may be in the range of 1.25-1.5.

[0056] In another embodiment, the thickness of the amorphous silicon layer in the groove area is 150-160 nm, and the thickness of the amorphous silicon layer in the non-groove area is 130-150 nm. Within the above thickness range, the thickness of the amorphous silicon layer is relatively large, and thus the thickness of the subsequently formed polycrystalline silicon layer is relatively large, thereby ensuring that when the metal electrode is subsequently formed, the metal electrode is not easy to penetrate the polycrystalline silicon layer, which is conducive to further maintaining the integrity of the formed solar cell.

[0057] Specifically, the thickness of the amorphous silicon layer located in the groove area can be, for example, 150-155nm and 155-160nm. The thickness of the amorphous silicon layer located in the non-groove area can be, for example, 130-135nm, 135nm-140nm, 140nm-145nm and 145nm-150nm. Specifically, the ratio of the thickness of the amorphous silicon layer located in the groove area to the thickness of the amorphous silicon layer located in the non-groove area can be in the range of 1.05-1.2. It can be understood that in the embodiment of the present application, the formed amorphous silicon layer is used as the basis for the subsequent formation of a multi-layer doped polycrystalline silicon layer. Therefore, the thickness of the amorphous silicon layer is set within this range, so that the thickness of the formed amorphous silicon layer is not too small, thereby providing more space for the subsequent formation of a polycrystalline silicon layer. In addition, within this range, the thickness of the amorphous silicon layer is not too large, so that the overall thickness of the polycrystalline silicon layer formed subsequently is not too large, which is conducive to the miniaturization of solar cells. In practical applications, the thickness of the polysilicon layer can be preset, and then the thickness of the amorphous silicon layer to be formed can be set based on the thickness of the polysilicon layer. In this way, the thickness of the polysilicon layer formed based on the amorphous silicon layer can meet expectations.

[0058] Figure 2 A schematic diagram of the structure of a solar cell provided in another embodiment of the present application.

[0059] like Figure 2 As shown, the solar cell comprises:

[0060] A base layer 10, wherein a first surface of the base layer 10 has a plurality of groove areas and a plurality of non-groove areas;

[0061] A first tunnel dielectric layer 11 is located on the first surface, wherein the thickness of the first tunnel dielectric layer 11 located in the groove area is greater than the thickness of the first tunnel dielectric layer 11 located in the non-groove area;

[0062] A doping layer 12 is located on a side of the first tunnel dielectric layer 11 away from the base layer 10, and a thickness of the doping layer 12 located in the groove region is greater than a thickness of the doping layer 12 located in the non-groove region;

[0063] The first electrode 13 is located in the groove area.

[0064] The solar cell comprises a substrate layer, a first tunnel dielectric layer, a doping layer and a first electrode, wherein the first surface of the substrate layer has a plurality of groove regions and a plurality of non-groove regions, the thickness of the first tunnel dielectric layer located in the groove region is greater than the thickness of the first tunnel dielectric layer located in the non-groove region, the thickness of the doping layer located in the groove region is greater than the thickness of the doping layer located in the non-groove region, and the first electrode is located in the groove region. In this scheme, on the one hand, since the thickness of the first tunnel dielectric layer located in the groove region is greater than the thickness of the first tunnel dielectric layer located in the non-groove region, a thicker first tunnel dielectric layer can be formed in the groove region of the substrate layer. Since surface recombination usually occurs at surface defects or interfaces, a thicker tunnel dielectric layer can passivate these defects, thereby reducing the surface recombination rate, which helps to improve the open circuit voltage and fill factor of the solar cell, thereby improving the overall photoelectric conversion efficiency. On the other hand, the thickness of the doping layer located in the groove region is greater than the thickness of the doping layer located in the non-groove region, which can optimize its crystal quality and reduce defect density to improve the carrier transmission characteristics, help reduce series resistance, reduce energy loss during transmission, and thus improve short-circuit current density. The above method can improve the performance of solar cells by combining the improvement of photoelectric conversion efficiency with the improvement of short-circuit current density, thus solving the problem of how to improve the performance of solar cells in the prior art.

[0065] like Figure 2 As shown, the solar cell further includes: a second tunnel dielectric layer 14, a passivation layer 15 and a second electrode 16 located on the second surface, and the substrate layer has the first surface and the second surface opposite to each other.

[0066] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0067] 1. The method for preparing a solar cell of the present application comprises the following steps: first, providing an initial wafer; processing the initial wafer by a laser process to obtain a substrate layer having a plurality of groove regions and non-groove regions on the first surface; forming a first tunnel dielectric layer on the first surface, wherein the thickness of the first tunnel dielectric layer in the groove region is greater than the thickness of the first tunnel dielectric layer in the non-groove region; then forming an amorphous silicon layer on the side of the first tunnel dielectric layer away from the substrate layer, wherein the thickness of the amorphous silicon layer in the groove region is greater than the thickness of the amorphous silicon layer in the non-groove region; then doping the amorphous silicon layer to obtain a doped layer; and finally forming a first electrode on a part of the surface of the groove region. In this scheme, on the one hand, in the process of forming the first tunnel dielectric layer, the thickness of the first tunnel dielectric layer in the groove region is greater than the thickness of the first tunnel dielectric layer in the non-groove region, so that a thicker first tunnel dielectric layer can be formed in the groove region of the substrate layer. Since surface recombination usually occurs at defects or interfaces on the surface, a thicker tunnel dielectric layer can passivate these defects, thereby reducing the surface recombination rate, which helps to improve the open circuit voltage and fill factor of the solar cell, thereby improving the overall photoelectric conversion efficiency. On the other hand, in the process of forming the amorphous silicon layer, the thickness of the amorphous silicon layer located in the groove area is greater than the thickness of the amorphous silicon layer located in the non-groove area, so that a thicker polysilicon layer can be formed in the groove area, and its crystal quality can be optimized and the defect density can be reduced to improve the carrier transmission characteristics, which is helpful to reduce the series resistance and reduce the energy loss in the transmission process, thereby increasing the short-circuit current density. On the other hand, by using a laser process to process the initial wafer, the back side is grooved to reserve the fine grid position, and the subsequent laser-assisted sintering of the fine grid can reduce the contact resistance and increase the carrier collection probability. The fine grid is hidden by coating and the main grid is printed after coating, thereby enhancing the contact performance between the fine grid and the metal electrode and the silicon substrate without changing the number of grid lines, reducing the back surface reflectivity, and improving the photoelectric conversion efficiency of the battery. The above method can improve the performance of solar cells by combining the improvement of photoelectric conversion efficiency and the improvement of short-circuit current density, and solves the problem of how to improve the performance of solar cells in the prior art.

[0068] 2. The solar cell of the present application comprises a substrate layer, a first tunnel dielectric layer, a doped layer and a first electrode, wherein the first surface of the substrate layer has a plurality of groove regions and a plurality of non-groove regions, the thickness of the first tunnel dielectric layer located in the groove region is greater than the thickness of the first tunnel dielectric layer located in the non-groove region, the thickness of the doped layer located in the groove region is greater than the thickness of the doped layer located in the non-groove region, and the first electrode is located in the groove region. In this scheme, on the one hand, since the thickness of the first tunnel dielectric layer located in the groove region is greater than the thickness of the first tunnel dielectric layer located in the non-groove region, a thicker first tunnel dielectric layer can be formed in the groove region of the substrate layer. Since surface recombination usually occurs at surface defects or interfaces, a thicker tunnel dielectric layer can passivate these defects, thereby reducing the surface recombination rate, which helps to improve the open circuit voltage and fill factor of the solar cell, and thus improve the overall photoelectric conversion efficiency. On the other hand, the thickness of the doped layer located in the groove region is greater than the thickness of the doped layer located in the non-groove region, which can optimize its crystal quality and reduce defect density to improve the carrier transmission characteristics, help reduce series resistance, reduce energy loss during transmission, and thus improve short-circuit current density. The above method can improve the performance of solar cells by combining the improvement of photoelectric conversion efficiency with the improvement of short-circuit current density, thus solving the problem of how to improve the performance of solar cells in the prior art.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing initial wafers; The initial wafer is processed by a laser process to obtain a base layer having a plurality of groove areas and non-groove areas on the first surface; Forming a first tunnel dielectric layer on the first surface, wherein the thickness of the first tunnel dielectric layer in the groove area is greater than the thickness of the first tunnel dielectric layer in the non-groove area; forming an amorphous silicon layer on a side of the first tunnel dielectric layer away from the base layer, wherein the thickness of the amorphous silicon layer located in the groove area is greater than the thickness of the amorphous silicon layer located in the non-groove area; Performing a doping treatment on the amorphous silicon layer to obtain a doped layer; A first electrode is formed on a portion of the surface of the recessed area.

2. The preparation method according to claim 1, characterized in that: Forming a first tunneling dielectric layer on the first surface includes: A plurality of sub-dielectric layers are sequentially deposited on the first surface, the plurality of sub-dielectric layers form the first tunneling dielectric layer, and during the formation of two adjacent sub-dielectric layers, the deposition gas pressures corresponding to the sub-dielectric layers are different.

3. The preparation method according to claim 1, characterized in that: An amorphous silicon layer is formed on a side of the first tunnel dielectric layer away from the base layer, comprising: A plurality of sub-amorphous silicon layers are sequentially deposited on the first surface, the plurality of sub-amorphous silicon layers form the amorphous silicon layer, and during the formation of two adjacent sub-amorphous silicon layers, the deposition gas pressures corresponding to the sub-amorphous silicon layers are different.

4. The preparation method according to claim 1, characterized in that: The amorphous silicon layer is doped to obtain a doped layer, comprising: Performing a doping treatment on the amorphous silicon layer located in the groove area to form a first doping area, wherein the doping type of the first doping area is different from the doping type of the base layer; The amorphous silicon layer located in the non-groove area is doped to form a second doping area, the doping type of the second doping area is different from the doping type of the base layer, the first doping area and the second doping area form the doping layer, and the doping concentration of the first doping area is greater than the doping concentration of the second doping area.

5. The preparation method according to claim 1, characterized in that: The method further comprises: A second tunneling dielectric layer, a passivation layer and a second electrode are sequentially formed on the second surface, and the base layer has the first surface and the second surface which are opposite to each other.

6. The preparation method according to any one of claims 1 to 5, characterized in that The laser wavelength of the laser process is 500-560nm, the laser power of the laser process is 20-40W, the laser frequency of the laser process is 200-400kHz, and the laser engraving speed of the laser process is 25000-35000mm / s.

7. The preparation method according to any one of claims 1 to 5, characterized in that The depth of the groove area is 6-8 μm.

8. The preparation method according to any one of claims 1 to 5, characterized in that The thickness of the first tunnel dielectric layer in the groove region is 1.8 to 2.2 μm, and the thickness of the first tunnel dielectric layer in the non-groove region is 1.5 to 1.8 μm.

9. The preparation method according to any one of claims 1 to 5, characterized in that The thickness of the amorphous silicon layer in the groove area is 150-160 nm, and the thickness of the amorphous silicon layer in the non-groove area is 130-150 nm.

10. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 9.

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