Balancing PEC in memory system

Abstract

Aspects of the present disclosure configure a memory subsystem controller to balance PEC across a die / plane of a memory subsystem. The memory subsystem controller determines that a first PEC of a first portion of a set of memory components is less than a second lifetime PEC of a second portion of the set of memory components. The memory subsystem controller performs a first memory operation on the first portion and the second portion in response to a first request associated with a block stripe. The memory subsystem controller erases the block stripe that includes the first portion and the second portion. The memory subsystem controller performs a second memory operation on the second portion of the set of memory components in response to a second request associated with the block stripe, without performing the second memory operation on the first portion of the set of memory components.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to providing adaptive media management for memory components such as memory dies. Background Art

[0002] The memory subsystem may be a storage system such as a solid state drive (SSD), and may include one or more memory components that store data. For example, the memory components may be non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data on the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 is a block diagram illustrating an example computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 is a block diagram of an example media operations manager according to some embodiments of the present disclosure.

[0006] Figure 3 is a block diagram of an example plane selection operation according to some embodiments of the present disclosure.

[0007] Figure 4 is a block diagram of an example plane selection table according to some embodiments of the present disclosure.

[0008] Figure 5 is a flow chart of an example method of performing PEC balancing according to some embodiments of the present disclosure.

[0009] Figure 6 is a block diagram illustrating a diagrammatic representation of a machine in the form of a computer system within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] Aspects of the present disclosure configure system components, such as a memory subsystem controller, to perform a program-erase count (PEC) balancing operation. The memory subsystem controller may determine a lifetime PEC for each of the components of a set of memory components, such as a memory die. Based on the lifetime PEC, the memory subsystem controller may selectively distribute memory operations across the memory components such that at one point in time, a first portion having a smaller lifetime PEC than a second portion is programmed with the second portion, and at a later point in time, the first portion having the smaller PEC is not programmed while the second portion is programmed. This ensures that the performance of the memory system remains optimal by increasing the current PECs of different memory components at different rates until the PECs of the memory components reach equilibrium (e.g., are equal to each other or correspond to a target PEC). At this point, the different components are always programmed and erased together. This improves the overall efficiency of operating the memory subsystem.

[0011] The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components, such as a memory device (e.g., a memory die or a plane across multiple memory dies) that stores data. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem, such as to store data at the memory subsystem and read data from the memory subsystem. Data (or data sets) specified by the host are hereinafter referred to as "host data," "application data," or "user data."

[0012] The memory subsystem may initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a junk collection management operation, the firmware of the memory subsystem may overwrite previously written host data from a location on the memory device to a new location. The data that is overwritten (e.g., as initiated by the firmware) is referred to hereinafter as "junk collection data." "User data" may include host data and junk collection data. "System data" hereinafter refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical to physical address mapping tables), data from log records, scratch pad data, etc.

[0013] Many different media management operations may be performed on a memory device. For example, media management operations may include different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near error error correction (ECC), and / or different dynamic data refresh. Wear leveling ensures that all blocks in a memory component approach their defined erase cycle budget at the same time, rather than some blocks approaching the erase cycle budget earlier. Read disturb management counts all read operations of a memory component. If a certain threshold is reached, the surrounding area is refreshed. Near error ECC refreshes all data read by an application that exceeds a configured error threshold. As a background operation, a dynamic data refresh scan reads all data and identifies the error status of all blocks. If a certain error threshold for each block or ECC unit is exceeded in this scan read, a refresh operation is triggered.

[0014] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies (or dies). Each die may include one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. For some memory devices, a block is the smallest area that can be erased. Each block includes a set of pages. Each page includes a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is managed externally by an external controller, for example. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0015] There are challenges in efficiently managing typical memory devices or performing media management operations on typical memory devices. Specifically, certain memory devices, such as NAND flash devices, include large die-to-die reliability (RWB) variations. As the technology scale of such memory devices continues to shrink, this die-to-die reliability variation becomes more significant and problematic when performing memory management. Current memory systems (e.g., SSD drives or die packaging systems) associate all memory devices or memory dies in the memory system with a certain reliability specification. In some cases, each block of each memory device is associated with a reliability level or specification for determining whether the block is a good block or a bad block. A good block is a block with a reliability level above a reliability threshold, while a bad block is a block with a reliability level below a reliability threshold. The reliability level can be set at the time of manufacture of the memory device or during its operation, such as by measuring data retention and / or error rates associated with a particular block.

[0016] Some memory systems assign a lifetime PEC to each block or memory die of the memory subsystem at the time of manufacture. This lifetime PEC represents the total number of times each memory die can be erased and programmed before the reliability of the memory die drops below a reliability threshold, at which point the memory die can no longer be used. In some cases, once the lifetime PEC of a memory die is reached, the memory subsystem stops programming that memory die, which effectively reduces the overall storage capacity of the memory subsystem. The memory system maintains a current count of the PEC for each memory die and increments this count each time all planes of a memory die are erased and / or programmed.

[0017] Typical memory systems utilize superblocks or block stripes (BS) that are sets of blocks across memory planes and / or dies. That is, each superblock may be of equal size and may include a corresponding set of blocks across multiple planes and / or dies. Superblocks, when allocated, allow the controller to simultaneously write data to a large portion of memory spanning multiple blocks (across multiple planes and / or dies) with a single address. Sometimes, a superblock includes memory dies associated with different life PECs. Typical systems program these superblocks without considering the PEC values ​​of the memory dies. This typically results in poor memory performance because performing memory operations on a first set of planes or dies with a lower life PEC value at the same rate as a second set of planes or dies with a higher life PEC value may cause the first set of planes to be decommissioned before the second set of planes, which may reduce the overall storage capacity of the memory subsystem. Thus, applying a one-size-fits-all approach to a memory system with a mix of PEC values ​​for different superblock portions is inefficient and results in poor or unreliable memory performance.

[0018] Aspects of the present disclosure address the above and other disadvantages by providing a memory controller that can balance PECs across different memory components (e.g., planes) of multiple memory dies implementing block striping. This ensures that the different memory components reach a target PEC at the same time, rather than the lifetime PEC of one set of components being depleted or reached before the lifetime PEC of another set of components. This ensures that the performance of the memory system remains optimal by increasing the current PECs of different memory components at different rates until the PECs of the memory components reach equilibrium (e.g., are equal to each other or correspond to the target PEC). At this point, the different components are always programmed and erased together. This improves the overall efficiency of operating the memory subsystem.

[0019] For example, the memory controller may determine that a first lifetime program-erase count (PEC) of a first portion of a group of memory components is less than a second lifetime PEC of a second portion of the group of memory components. The memory controller may perform a first memory operation on the first portion and the second portion of a group of memory components in response to a first request associated with a block stripe and erase a block stripe including the first portion and the second portion of a group of memory components after performing the first memory operation. After erasing the block stripe, the memory controller may perform a second memory operation on the second portion of a group of memory components in response to a second request associated with the block stripe without performing the second memory operation on the first portion of the group of memory components.

[0020] In some examples, the first memory operation and the second memory operation include writing (programming or erasing) respective data sets to a stripe of blocks.

[0021] In some examples, the memory controller accesses configuration data including a lifetime PEC for each of a set of memory components.A first portion of a set of memory components may include a first memory die and a second portion of the set of memory components may include a second memory die.

[0022] In some cases, a first portion of the set of memory components includes a set of planes in a plurality of planes of a first memory die and a second portion of the set of memory components includes a second memory die. In some examples, the set of planes is a first set of planes. In such cases, the memory controller programs the first set of planes in response to a first request associated with the block stripe and does not program a second set of planes in a plurality of planes of the first memory die. The memory controller programs the second set of planes in response to a second request associated with the block stripe and does not program the first set of planes.

[0023] In some examples, the memory controller alternates between selecting a first set of planes for programming and selecting a second set of planes for programming in response to each subsequent request associated with the block stripe. Specifically, the first portion of the set of memory components may include a set of planes from a number of planes. In such cases, the memory controller selects a target PEC for the set of memory components and forms a set of planes based on the target PEC, the number of planes, a first lifetime PEC for the first portion, and a second lifetime PEC for the second portion. For example, the set of planes may be formed based on a function including: Wherein a set of plane counts indicates how many planes there are in a set of planes, PC corresponds to the number of planes, the PEC of the first portion corresponds to the first lifetime PEC, and the PEC of the second portion corresponds to the second lifetime PEC.

[0024] In some examples, the memory controller may decrease the first lifespan PEC at a different rate than the second lifespan PEC in response to the first request and the second request, such as by incrementing the current PEC of each memory component relative to the corresponding lifespan PEC of the memory component.

[0025] In some cases, the memory controller may select a plane count associated with the first portion and calculate a target PEC based on the plane count that represents the number of remaining PECs for the first portion and the second portion after completing balancing the first life PEC with the second life PEC. The target PEC may be calculated according to: Wherein the PEC of the first portion corresponds to a first lifetime PEC, the PEC of the second portion corresponds to a second lifetime PEC, and the total plane count represents the number of planes in the memory die including the first portion.

[0026] In some examples, a memory controller may select a target PEC for a group of memory components. The memory controller may calculate a plurality of numbers of planes to select from a group of planes for each memory die in a plurality of memory dies based on the target PEC, a total number of planes in the group of planes, a first lifetime PEC of the first portion, and a second lifetime PEC of the second portion. The memory controller may determine a scaling factor for each of the plurality of numbers of planes and generate a plurality of plane selection tables based on the plurality of numbers of planes and the scaling factors, a first plane selection table in the plurality of plane selection tables corresponding to a first memory die in the plurality of memory dies, and a second plane selection table in the plurality of plane selection tables corresponding to a second memory die in the plurality of memory dies.

[0027] In some cases, the first plane selection table includes a first list of sequential times corresponding to a first number of scaling factors in a plurality of numbers, each sequential time in the first list of sequential times being associated with an identifier of a plane selected from a set of planes of a first memory die. The second plane selection table includes a second list of sequential times corresponding to a second number of scaling factors in a plurality of numbers, each sequential time in the second list of sequential times being associated with an identifier of a plane selected from a set of planes of a second memory die, the first list of sequential times and the second list of sequential times having different numbers of sequential times.

[0028] In some examples, the memory controller obtains a current PEC associated with a second portion of a set of memory components and divides the current PEC by a scaling factor of a first number of a plurality of numbers of first die to identify a remainder. The memory controller may identify an individual sequential time within a first plane selection table corresponding to the remainder. In some cases, the memory controller retrieves an identifier of a plane selected from a set of planes of the first memory die corresponding to the individual sequential time and performs the first memory operation on a first subset of planes of the first memory die corresponding to the retrieved identifier of the plane selected from the set of planes without performing the first memory operation on a second subset of planes of the first memory die.

[0029] In some examples, the memory controller may determine that a first current PEC of the first portion corresponds to a second current PEC of the second portion. In response to determining that the first current PEC corresponds to the second current PEC, the memory controller stops balancing the first lifetime PEC with the second lifetime PEC. Specifically, the memory controller may stop balancing by performing, on the first portion and the second portion of a group of memory components, each of a plurality of memory operations received after the first current PEC corresponds to the second current PEC.

[0030] Although various embodiments are described herein as being implemented with respect to a memory subsystem (eg, a controller of a memory subsystem), some or all portions of the embodiments may be implemented with respect to a host system (eg, a software application or operating system of the host system).

[0031] Figure 1 An example computing environment 100 including a memory subsystem 110 is illustrated according to some examples of the present disclosure. The memory subsystem 110 may include media, such as memory components 112A-112N (also referred to hereinafter as "memory devices"). The memory components 112A-112N may be volatile memory devices, non-volatile memory devices, or a combination thereof. The memory components 112A-112N may be implemented by individual dies, such that a first memory component 112A may be implemented by a first memory die (or a first set of memory dies) and a second memory component 112N may be implemented by a second memory die (or a second set of memory dies). Each memory die may include multiple planes in which data may be stored or programmed.

[0032] In some examples, a first memory component 112A, a block or page of a first memory component 112A, or a group of memory components including the first memory component 112A may be associated with a first reliability (capability) level, value, metric, or life PEC. The terms "reliability level," "value," and "metric" may be used interchangeably throughout and may have the same meaning. A second memory component 112N, or a group of memory components including the second memory component 112N, may be associated with a second reliability (capability) level, value, metric, or life PEC. In some examples, each memory component 112A to 112N may store corresponding configuration data specifying a respective reliability level and life PEC as well as a current PEC. In some examples, a memory or register may be associated with all memory components 112A to 112N, which may store a table mapping different groups, bins, or sets of memory components 112A to 112N to respective reliability levels, life PEC values, and / or current PEC values.

[0033] In some examples, a memory or register may be associated with all memory components 112A to 112N, which may store a table mapping pages across all memory components 112A to 112N associated with individual block stripes. Specifically, a set of blocks or pages within a first memory component 112A may be grouped together with a set of blocks or pages within a second memory component 112N to form a super block or block stripe. A super block (or block stripe) may be commonly addressed using a single address. In such a case, the LTP table may store an association between a single address and each of the sets of blocks or pages of the first memory component 112A and the second memory component 112N associated with the single address. In some embodiments, a first set of blocks or pages of a super block (or block stripe) implemented by the first memory component 112A may be associated with a first life PEC and a second set of blocks or pages of a super block (or block stripe) implemented by the second memory component 112N may be associated with a second life PEC. The second life PEC may be greater / larger than the first life PEC.

[0034] In some cases, the media operations manager 122 balances operations performed with respect to such block stripes so that a first group of blocks or pages reaches a target PEC at the same time as a second group of blocks or pages. To this end, the media operations manager 122 may perform media operations, such as programming and / or erasing operations, on the first group of blocks or pages at a different rate than on the second group of blocks or pages. For example, the media operations manager 122 may program a first group of first blocks or pages of the first memory component 112A at a first point in time without programming a second group of first blocks or pages of the first memory component 112A, while also programming a second group of blocks or pages of the second memory component 112N. At a later second point in time, the media operations manager 122 may program a second group of first blocks or pages of the first memory component 112A without programming the first group of first blocks or pages of the first memory component 112A, while still also programming a second group of blocks or pages of the second memory component 112N. Thus, the PEC value associated with the second memory component 112N may be incremented twice (once for each of the first and second time points), while the PEC value associated with the first memory component 112A is incremented only once (after the first and second groups of the first block or page of the first memory component 112A have been programmed after the first and second time points).

[0035] In some embodiments, the memory subsystem 110 is a storage system. The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0036] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0037] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 .

[0038] Memory components 112A-112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A-112N may include one or more memory cell arrays, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some embodiments, a particular memory component 112 may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., blocks) used by a host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A-112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of nonvolatile memory cells.

[0039] The cross-point array of non-volatile memory cells may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, in contrast to many flash-based memories, the cross-point non-volatile memory may perform write-in-place operations, where non-volatile memory cells may be programmed without previously erasing the non-volatile memory cells. Furthermore, the memory cells of the memory components 112A to 112N may be grouped into memory pages or blocks, which may refer to units of the memory components 112 for storing data. For example, a single first row spanning a first set of pages or blocks of the memory components 112A to 112N may correspond to or be grouped as a first block stripe and a single second row spanning a second set of pages or blocks of the memory components 112A to 112N may correspond to or be grouped as a second block stripe.

[0040] The memory subsystem controller 115 may communicate with the memory components 112A-112N to perform memory operations, such as reading data, writing data, or erasing data and other such operations at the memory components 112A-112N. The memory subsystem controller 115 may communicate with the memory components 112A-112N to perform various memory management operations, such as different scan rates, different scan frequencies, different wear leveling, different read disturb management, different near error ECC operations, and / or different dynamic data refresh.

[0041] The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communications between the memory subsystem 110 and the host system 120). In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although it has been described herein, the local memory 119 may be a memory register that stores memory pointers, extracted data, etc. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor 117 or controller separate from the memory subsystem 110).

[0042] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A-112N. In some examples, the commands or operations received from the host system 120 may specify configuration data for the memory components 112N-112N. The configuration data may describe lifetime PEC values ​​and / or reliability levels associated with different groups of memory components 112N-112N and / or different blocks within each of the memory components 112N-112N.

[0043] The memory subsystem controller 115 may be responsible for other memory management operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system 120 into command instructions to access the memory components 112A-112N and convert responses associated with the memory components 112A-112N into information for the host system 120.

[0044] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM or other temporary storage location or device) and address circuitry (e.g., a row decoder and a column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A-112N.

[0045] The memory device may be a raw memory device (e.g., NAND) that is externally managed, for example, by an external controller (e.g., memory subsystem controller 115). The memory device may be a managed memory device (e.g., managed NAND) that is a raw memory device combined with a local embedded controller (e.g., a local media controller) within the same memory device package for memory management. Any of the memory components 112A-112N may include a media controller (e.g., media controller 113A and media controller 113N) to manage memory cells of the memory component (e.g., perform one or more memory management operations), communicate with the memory subsystem controller 115, and execute memory requests (e.g., reads or writes) received from the memory subsystem controller 115.

[0046] The memory subsystem controller 115 may include a media operations manager 122. The media operations manager 122 may be configured to balance the PECs across different memory components 112A to 112N (e.g., planes) of multiple memory dies implementing block striping. This ensures that the different memory components 112A to 112N reach a target PEC at the same time, rather than the lifetime PEC of one set of components 112A being depleted or reached before the lifetime PEC of another set of components 112N. This ensures that the performance of the memory system remains optimal by increasing the current PECs of the different memory components 112A to 112N at different rates until the PECs of the memory components 112A to 112N reach a balance (e.g., equal to each other or corresponding to the target PEC). At this point, the different components 112A to 112N are always programmed and erased together. This improves the overall efficiency of operating the memory subsystem 110.

[0047] Depending on the embodiment, the media operations manager 122 may include logic (e.g., a set of transient or non-transient machine instructions, such as firmware) or one or more components that enable the media operations manager 122 to perform the operations described herein. The media operations manager 122 may include tangible or non-tangible units capable of performing the operations described herein. Additional details regarding the operation of the media operations manager 122 are described below.

[0048] Figure 2 2 is a block diagram of an example media operations manager 200 (corresponding to media operations manager 122) according to some embodiments of the present disclosure. As illustrated, media operations manager 200 includes configuration data 220, a PEC management module, and a plane selection module 240. Any discussion of plane selection may similarly apply to block and / or memory die selection. For some embodiments, components or arrangements of media operations manager 200 (e.g., fewer or more components) may be similar to those of FIG. Figure 2 The components or arrangements described in the examples are different.

[0049] Configuration data 220 accesses and / or stores configuration data associated with memory components 112A-112N. In some examples, configuration data 220 is programmed into media operations manager 200. For example, media operations manager 200 may communicate with memory components 112A-112N to obtain configuration data and store configuration data 220 locally on media operations manager 122. In some examples, media operations manager 122 communicates with host system 120. Host system 120 receives input from an operator or user specifying parameters including lifetime PEC values ​​for a collection of different bins, groups, blocks, block stripes, memory dies, and / or memory components 112A-112N. Media operations manager 122 receives configuration data from host system 120 and stores the configuration data in configuration data 220.

[0050] The PEC management module 230 may access the configuration data 220 to determine that a first lifetime PEC of a first portion of a group of memory components 112A is less than a second lifetime PEC of a second portion of the group of memory components 112N. Figure 3 , the PEC management module 230 identifies a plurality of memory dies including a first memory die 320, a second memory die 314, and a third memory die 316 of the individual block stripes 300. The first memory die 320 can be associated with a first lifetime PEC, the second memory die 314 can be associated with a second lifetime PEC, and the third die 316 can be associated with a third lifetime PEC. The first, second, and third lifetime PEC values ​​can all be the same, or can be partially different from one another in various combinations.

[0051] The PEC management module 230 may perform a first memory operation on the first portion and the second portion of a group of memory components in response to a first request associated with a block stripe and erase the block stripe including the first portion and the second portion of the group of memory components after performing the first memory operation. After erasing the block stripe, the memory controller may perform a second memory operation on a second portion of the group of memory components in response to a second request associated with the block stripe without performing the second memory operation on the first portion of the group of memory components.

[0052] Specifically, the PEC management module 230 determines that the first lifetime PEC of the first memory die 320 is less than the second lifetime PEC of the second memory die 314. In such a case, the PEC management module 230 selectively programs different plane groups of the first memory die 320 based on certain plane selection criteria. Specifically, in response to receiving a first request to write data to the block stripe 300, the PEC management module 230 communicates with the plane selection module 240 to identify and select which individual plane groups of the first memory die 320 are programmed and / or erased at a given time or cycle corresponding to the first request. For example, the PEC management module 230 may alternate between programming the first plane group 322 and the second plane group 324 at different points in time. That is, at the first point in time 310, the PEC management module 230 may select the first plane group 322 to be programmed along with the planes 330 of the second memory die 314 and the planes of the third memory die 316. In such a case, the PEC management module 230 prevents the second plane group 324 from being programmed while the first group of planes 322 are being programmed along with the planes 330 of the second memory die 314 and the planes of the third memory die 316. At this point, the PEC management module 230 updates or increments the current PEC value associated with the second memory die 314 and the third memory die 316, but has not yet updated or incremented the current PEC value associated with the first memory die 320. This is because, to date, not all planes of the first memory die 320 have been programmed (e.g., the second plane group 324 has not yet been programmed). That is, the current PEC value represents the cycles that each of the planes of a given memory die has been programmed and / or erased.

[0053] At a later point in time, the PEC management module 230 may perform trash collection and may erase all planes of written data for the block stripe 300. At a second point in time 350, a second request to write data to the block stripe 300 is received. In response, the PEC management module 230 communicates with the plane selection module 240 to identify and select another separate group of planes of the first memory die 320 for programming and / or erasing. For example, the PEC management module 230 may select the second group of planes 344 to be programmed with the planes 330 of the second memory die 314 and the planes of the third memory die 316 at the second point in time 350. In such a case, the PEC management module 230 prevents the first group of planes 342 from being programmed while the second group of planes 344 are being programmed with the planes 330 of the second memory die 314 and the planes of the third memory die 316. At this point, the PEC management module 230 again updates or increments the current PEC values ​​associated with the second memory die 314 and the third memory die 316 (eg, because all of their planes have been written to at the second point in time 350).

[0054] In some cases, the PEC management module 230 determines that all planes of the first memory die 320 are now programmed and therefore, the PEC management module 230 updates or increments the current PEC value associated with the first memory die 320. Thus, after the first time point 310 and the second time point 350, the current PEC values ​​of the second memory die 314 and the third memory die 316 have been updated or incremented twice, while the current PEC value of the first memory die 320 has been incremented once. Continuing these operations of alternating plane selection and incrementing the PEC values ​​of different memory dies at different rates ultimately balances the PEC values ​​of the block stripe 300. In this way, after receiving a threshold number of times or a threshold number of requests to write or program data into the block stripe 300, the current PEC value of the first memory die 320 will correspond to or be equal to the current PEC values ​​of the second memory die 314 and the third memory die 316. At this point, the PEC management module 230 programs and / or erases all planes (e.g., the first plane group 322 and the second plane group 324) together with the planes 330 of the second memory die 314 and the planes of the third memory die 316. In this way, all memory dies associated with the block stripe 300 will eventually reach their respective end-of-life PECs at the same time.

[0055] In some cases, rather than selecting specific plane groups of individual memory dies to write to at different points in time, the PEC management module 230 may alternately or completely skip programming and / or erasing individual memories. For example, at a first point in time 310, the PEC management module 230 may program and / or erase all planes (e.g., first plane group 322 and second plane group 324) of the first memory die 320 together with planes 330 of the second memory die 314 and planes of the third memory die 316 in response to a first memory operation request. At a second point in time 350, the PEC management module 230 may skip or prevent programming and / or erasing all planes (e.g., first plane group 322 and second plane group 324) of the first memory die 320 while programming and / or erasing all planes 330 of the second memory die 314 and all planes of the third memory die 316 in response to a second memory operation request. In this manner, the current PEC values ​​of the first memory die 320, the second memory die 314, and the third memory die 316 are updated or incremented at different rates. Thus, all of the memory dies associated with the block stripe 300 will eventually reach their respective lifetime PECs at the same time.

[0056] In some examples, the plane selection module 240 can select a target PEC for a group of memory elements and can form a group of planes according to the target PEC, the number of planes, the first life PEC of the first portion, and the second life PEC of the second portion as selected planes to be provided to the PEC management module 230 for programming and / or erasing. Specifically, the plane selection module 240 can form a group of planes according to the following function or equation 1:

[0057]

[0058] Wherein a set of plane counts indicates how many planes there are in a set of planes, PC corresponds to the number of planes, the PEC of the first portion corresponds to the first lifetime PEC, and the PEC of the second portion corresponds to the second lifetime PEC. That is, the plane selection module 240 may receive an input for selecting a target PEC. The target PEC may represent a PEC for balancing the PEC values ​​of different planes of the memory die. Once all memory dies reach the target PEC, all planes of the memory dies may be programmed and / or erased simultaneously.

[0059] In some examples, the plane selection module 240 can calculate the target PEC based on the number of planes selected from the total number of available planes of the individual memory die to be programmed and / or erased each time a memory operation is performed in association with the individual block stripe. The number of planes can be selected based on configuration information and / or input from the host. The target PEC can then be calculated according to Equation 2:

[0060]

[0061] Wherein the PEC of the first portion corresponds to a first lifetime PEC, the PEC of the second portion corresponds to a second lifetime PEC, and the total plane count represents the number of planes in the memory die including the first portion.

[0062] For example, if the plane count of a given memory die used each time a memory die is programmed during PEC balancing is 3 and the total number of planes included in the given memory die is 6, then the target PEC may be calculated based on the lifetime or current PEC value of the first memory die and the lifetime or current PEC value of the second memory die (e.g., the memory die with the larger lifetime PEC value). Specifically, the lifetime PEC value of the first memory die may be 7000 and the lifetime PEC value of the second memory die may be 10000. In such a case, the target PEC may be calculated to be equal to 4000 (e.g., (7000*6−10000*3) / (6−3)). That is, the PEC of the first portion corresponds to the lifetime PEC of the first memory die, the PEC of the second portion corresponds to the lifetime PEC of the second memory die, the total plane count corresponds to the total number of available planes in the memory die, and the selected plane count corresponds to the plane count of the given memory die used each time the memory die is programmed during PEC balancing. Once the current PEC values ​​of all memory dies reach the target PEC (at the same time or cycle), the PEC balancing operation can be terminated or stopped to perform subsequent program and / or erase operations across all planes of the block stripe.

[0063] In some examples, the plane selection module 240 selects a target PEC for a group of memory components and calculates a plurality of numbers of planes to select from a group of planes of each memory die in the plurality of memory dies according to the target PEC, the total number of planes in the group of planes, the first lifetime PEC of the first portion, and the second lifetime PEC of the second portion. The plane selection module 240 determines a scaling factor for each of the plurality of numbers of planes and generates a plurality of plane selection tables based on the plurality of numbers of planes and the scaling factors, a first plane selection table in the plurality of plane selection tables corresponding to a first memory die in the plurality of memory dies, and a second plane selection table in the plurality of plane selection tables corresponding to a second memory die in the plurality of memory dies. The first plane selection table may include a first sequential time list corresponding to a first number of scaling factors in the plurality of numbers, each sequential time in the first sequential time list being associated with an identifier of a plane selected from a group of planes of the first memory die. The second plane selection table may include a second sequential time list corresponding to a second number of scaling factors in the plurality of numbers, each sequential time in the second sequential time list being associated with an identifier of a plane selected from a group of planes of the second memory die, the first sequential time list and the second sequential time list having different numbers of sequential times.

[0064] For example, Figure 4A block diagram showing an example plane selection table 400 generated by the plane selection module 240 according to some embodiments of the present disclosure. To generate the plane selection table 400 for a first memory die or a first group of memory die, the plane selection module 240 determines the total number of planes available in each memory die, and a subject PEC for a particular memory die (e.g., a memory die in a group of memory die having a maximum PEC value greater than the PEC values ​​of all other memory die in the group of memory die). The plane selection module 240 also selects a target PEC.

[0065] According to Equation 1, the plane selection module 240 obtains the number of planes (PlaneCntSelected) of the total number of planes that can be selected at a time and for each memory die. This can be performed based on the lifetime PEC value of each memory die relative to the subject PEC of the particular memory die. In a specific example, the total number of planes can be 6, the subject PEC (e.g., of memory die 7) can be 11000, and the target PEC can be 1000. In such a case, the plane selection module 240 generates the initial plane count indicator table shown below:

[0066] Die 0 Bare Die 1 Bare Die 2 Die 3 Bare Die 5 Bare Die 6 Bare chip 7 PEC 10000 7000 10000 8000 10000 6000 11000 PlaneCntSelected 5.4 3.6 5.4 4.2 5.4 3 6 Integer Factors 10 10 10 10 10 2 1 TotalPlaneCountPerTimes 54 36 54 42 54 6 6

[0067] In some cases, the calculation of PlaneCntSelected (representing the number of planes of a given memory die that are programmed and / or erased at each particular time that a block stripe is programmed and / or erased) output by Equation 1 is a non-integer value or an integer value that is below a threshold. In such cases, the plane selection module 240 applies a scaling factor (e.g., an integer factor) to PlaneCntSelected to generate a TotalPlaneCountPerTimes value. The scaling factor may vary between each of the memory dies. For example, the result of applying Equation 1 to memory die 0 may be 5.4, in which case a scaling factor of 10 is applied to calculate a TotalPlaneCountPerTimes value of 54. As another example, the result of applying Equation 1 to memory die 6 may be 3 (which is below a threshold), in which case a scaling factor of 2 is applied to calculate a TotalPlaneCountPerTimes value of 6.

[0068] The plane selection module 240 uses the scaling factor to control the time included in the time list of each plane selection table generated for each corresponding memory die. Figure 4, the plane selection module 240 generates a plane selection table 400 corresponding to memory dies 0, 2, and 5 because they all have the same lifetime PEC value. The plane selection table 400 includes a representation of the memory die 410 to which the plane selection table 400 corresponds. The plane selection table 400 includes a sequential time list 420 representing different sequential times at which the same block stripe is programmed and / or erased. The number of sequential times 420 included in the plane selection table corresponds to the scaling factor. For example, the scaling factor for memory dies 0, 2, and 5 may be 10, in which case the plane selection table includes a list of 10 sequential times. After the block stripe is programmed and / or erased a number of times corresponding to the sequential time list 420 (e.g., once the last time in the sequential time list 420 is used to select the corresponding plane group), the plane selection module 240 completes one cycle.

[0069] The plane selection module 240 stores, in association with each time listed in the sequential time list 420, a selected plane count value 430 indicating the number of planes in a set of planes selected from the total number of available planes of the memory die 410. This selected plane count value 530 may be calculated based on Equation 1. The plane selection module 240 stores, in association with each time listed in the sequential time list 420, a starting plane value 440 and a selected plane identifier 450. The starting plane value 440 identifies which plane of a set of planes (selected to be programmed and / or erased) is to be used as the first plane in the plane array or set. The selected plane identifier 450 represents an identifier of a set of planes selected to be programmed and / or erased at each corresponding time that a block stripe is programmed and / or erased.

[0070] In some cases, the starting plane value 440 is calculated according to Equation 3: StartPlane = (LastStartPlane + PlaneCntSelected) % PlaneCnt, where StartPlane represents the starting plane value 440, LastStartPlane represents the value of the starting plane value 440 in the immediately preceding time in the sequential time list 420, PlaneCntSelected represents the number of planes of a given memory die that are programmed and / or erased at each particular time that a block stripe is programmed and / or erased, as output by Equation 1, and PlaneCnt (or total plane count) represents the total number of planes in the memory die. The selected plane identifier 450 may be calculated according to Equation 4: Plane = (StartPlane + Offset) % PlaneCnt.

[0071] The plane selection module 240 may also calculate a ratio of PECs 460 representing the ratio of lifetime PECs of a first memory die (e.g., memory die 0, 2, and 5) to a second memory die (e.g., memory die 7). This represents the number of times the first memory die will be programmed and / or erased relative to the second memory die. In some examples, the plane selection module 240 prevents the storage of the starting plane value 440 and the selected plane identifier 450 for each memory die. Instead, the plane selection module 240 calculates these values ​​in real time in response to identifying a particular time from the sequential time list 420.

[0072] Specifically, the plane selection module 240 may access the current PEC value of the second memory die. Based on the current PEC value of the second memory die, the plane selection module 240 may derive or calculate a specific time instance in the sequential time list 420. The plane selection module 240 divides the current PEC value of the second memory die by the scaling factor associated with the first memory die. The plane selection module 240 may use the remainder resulting from the division as an index into the plane selection table 400, specifically to identify a given time 422 from within the sequential time list 420. Once the given time 422 is identified, the plane selection module 240 may obtain the corresponding selected plane count value 432. Using the selected plane count value 432, the plane selection module 240 may calculate a selected plane identifier 450 using equations 3 and 4.

[0073] Figure 5 5 is a flow chart of an example method 500 of PEC balancing operation according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The media operations manager 122 of the embodiment of the present invention is executed. Although the processes are shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0074] Reference Figure 5, the method (or process) 500 begins at operation 505, where a media operations manager 122 of a memory subsystem (e.g., memory subsystem 110) determines that a first lifetime program-erase count (PEC) of a first portion of a group of memory components is less than a second lifetime PEC of a second portion of the group of memory components. Next, at operation 510, the media operations manager 122 of the memory subsystem performs a first memory operation on the first portion and the second portion of the group of memory components in response to a first request associated with a block stripe. Thereafter, at operation 515, the media operations manager 122 erases the block stripe including the first portion and the second portion of the group of memory components after performing the first memory operation. At operation 520, the media operations manager 122 performs a second memory operation on the second portion of the group of memory components in response to a second request associated with the block stripe after erasing the block stripe, without performing the second memory operation on the first portion of the group of memory components.

[0075] In view of the above disclosure, various examples are set forth below. It should be noted that one or more features of the examples taken alone or in combination should be considered within the disclosure of the present application.

[0076] Example 1: A system comprising: a set of memory components grouped into a block stripe of a memory subsystem; and a processing device operably coupled to the set of memory components, the processing device configured to perform operations, the operations comprising: determining that a first lifetime program-erase count (PEC) of a first portion of the set of memory components is less than a second lifetime PEC of a second portion of the set of memory components; performing a first memory operation on the first portion and the second portion of the set of memory components in response to a first request associated with the block stripe; erasing the block stripe including the first portion and the second portion of the set of memory components after performing the first memory operation; and performing a second memory operation on the second portion of the set of memory components in response to a second request associated with the block stripe after erasing the block stripe, without performing the second memory operation on the first portion of the set of memory components.

[0077] Example 2: The system of example 1, wherein the first memory operation and the second memory operation include writing respective data sets to the block stripe.

[0078] Example 3: The system of example 1 or 2, wherein the operations comprise accessing configuration data comprising a lifespan PEC for each of the set of memory components.

[0079] Example 4: The system of any of examples 1-3, wherein the first portion of the set of memory components includes a first memory die, and wherein the second portion of the set of memory components includes a second memory die.

[0080] Example 5: The system of any of examples 1-4, wherein the first portion of the set of memory components comprises a set of planes of a plurality of planes of a first memory die, and wherein the second portion of the set of memory components comprises a second memory die.

[0081] Example 6: The system of Example 5, wherein the set of planes is a first set of planes, and wherein the operations include: programming the first set of planes in response to the first request associated with the block stripe without programming a second set of planes in the plurality of planes of the first memory die; and programming the second set of planes in response to the second request associated with the block stripe without programming the first set of planes.

[0082] Example 7: The system of example 6, wherein the operations include alternating between selecting the first set of planes for programming and selecting the second set of planes for programming in response to each subsequent request associated with the block stripe.

[0083] Example 8: A system according to any one of Examples 1 to 7, wherein the first portion of the set of memory components includes a set of planes among a certain number of planes, and wherein the operation includes: selecting a target PEC for the set of memory components; and forming the set of planes based on the target PEC, the number of planes, the first lifetime PEC of the first portion, and the second lifetime PEC of the second portion.

[0084] Example 9: The system of example 8, wherein the set of planes is formed according to a function comprising: Wherein the set of plane counts indicates how many planes there are in the set of planes, PC corresponds to the number of planes, the PEC of the first portion corresponds to the first lifetime PEC, and the PEC of the second portion corresponds to the second lifetime PEC.

[0085] Example 10: The system of any of examples 1 to 9, wherein the operation comprises decreasing the first lifetime PEC at a different rate than the second lifetime PEC in response to the first request and the second request.

[0086] Example 11: A system according to any one of Examples 1 to 10, wherein the operation includes: selecting a plane count associated with the first portion; and calculating a target PEC representing the number of remaining PECs of the first portion and the second portion after completing balancing the first lifetime PEC and the second lifetime PEC based on the plane count.

[0087] Example 12: The system of Example 11, wherein the target PEC is calculated according to: wherein the PEC of the first portion corresponds to the first lifetime PEC, the PEC of the second portion corresponds to the second lifetime PEC, and a total plane count represents a number of planes in a memory die that includes the first portion.

[0088] Example 13: A system according to any of Examples 1 to 12, wherein the operations include: selecting a target PEC for the set of memory components; calculating a plurality of numbers of planes to select from a set of planes for each memory die in a plurality of memory dies based on the target PEC, the total number of planes in the set of planes, the first lifetime PEC of the first portion, and the second lifetime PEC of the second portion; determining a scaling factor for each of the plurality of numbers of planes; and generating a plurality of plane selection tables based on the plurality of numbers of planes and the scaling factors, a first plane selection table in the plurality of plane selection tables corresponding to a first memory die in the plurality of memory dies, and a second plane selection table in the plurality of plane selection tables corresponding to a second memory die in the plurality of memory dies.

[0089] Example 14: According to the system of Example 13, the first plane selection table includes a first sequential time list corresponding to the scaling factors of a first number among the multiple numbers, each sequential time in the first sequential time list is associated with an identifier of the plane selected from the set of planes of the first memory die; and the second plane selection table includes a second sequential time list corresponding to the scaling factors of a second number among the multiple numbers, each sequential time in the second sequential time list is associated with an identifier of the plane selected from the set of planes of the second memory die, the first sequential time list and the second sequential time list having different numbers of sequential times.

[0090] Example 15: A system according to Example 14, wherein the operation includes: obtaining a current PEC associated with the second portion of the set of memory components; dividing the current PEC by the scaling factor of the first number of the multiple numbers of the first die to identify a remainder; and identifying individual sequential times within the first plane selection table corresponding to the remainder.

[0091] Example 16: A system according to Example 15, wherein the operation includes: retrieving the identifier of the plane selected from the set of planes of the first memory die corresponding to the individual sequential times; and performing the first memory operation on a first subset of planes of the first memory die corresponding to the retrieved identifiers of the planes selected from the set of planes, without performing the first memory operation on a second subset of planes of the first memory die.

[0092] Example 17: A system according to any one of Examples 1 to 16, wherein the operation includes: determining that a first current PEC of the first portion corresponds to a second current PEC of the second portion; and in response to determining that the first current PEC corresponds to the second current PEC, stopping the balancing of the first lifetime PEC and the second lifetime PEC.

[0093] Example 18: The system of example 17, wherein stopping balancing comprises performing each of a plurality of memory operations received after the first current PEC corresponds to the second current PEC on the first portion and the second portion of the set of memory components.

[0094] Methods and computer-readable storage media having instructions for performing any of the above examples.

[0095] Figure 6 An example machine is illustrated in the form of a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0096] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a network switch, a network bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0097] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0098] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device 602 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0099] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside completely or at least partially within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0100] In one embodiment, instruction 626 implements the Figure 1 The functionality of the media operations manager 122 of the present disclosure. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be taken to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0101] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common usage reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0102] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0103] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards; or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0104] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description above. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0105] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0106] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be appreciated that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: a set of memory components grouped into block stripes of the memory subsystem; and a processing device operably coupled to the set of memory components, the processing device configured to perform operations comprising: determining that a first lifetime program-erase count (PEC) of a first portion of the set of memory components is less than a second lifetime PEC of a second portion of the set of memory components; performing a first memory operation on the first portion and the second portion of the set of memory components in response to a first request associated with the block stripe; erasing the block stripe including the first portion and the second portion of the set of memory components after performing the first memory operation; and After erasing the block stripe, a second memory operation is performed on the second portion of the set of memory components in response to a second request associated with the block stripe, and the second memory operation is not performed on the first portion of the set of memory components. 2 . The system of claim 1 , wherein the first memory operation and the second memory operation include writing respective data sets to the block stripe.

3. The system of claim 1, wherein the operations comprise: Configuration data including a lifespan PEC for each of the set of memory components is accessed.

4. The system of claim 1, wherein the first portion of the set of memory components comprises a first memory die, and wherein the second portion of the set of memory components comprises a second memory die.

5. The system of claim 1, wherein the first portion of the set of memory components comprises a set of planes of a plurality of planes of a first memory die, and wherein the second portion of the set of memory components comprises a second memory die.

6. The system of claim 5, wherein the set of planes is a first set of planes, and wherein the operations comprise: programming the first set of planes in response to the first request associated with the block stripe without programming a second set of planes in the plurality of planes of the first memory die; and The second set of planes are programmed in response to the second request associated with the block stripe without programming the first set of planes.

7. The system of claim 6, wherein the operations include: Alternating between selecting the first set of planes for programming and selecting the second set of planes for programming in response to each subsequent request associated with the block stripe.

8. The system of claim 1 , wherein the first portion of the set of memory components comprises a set of planes among a number of planes, and wherein the operations comprise: selecting a target PEC for the set of memory components; and The set of planes is formed according to the target PEC, the number of planes, the first lifetime PEC of the first portion, and the second lifetime PEC of the second portion.

9. The system of claim 8, wherein the set of planes is formed according to a function comprising: Wherein a set of plane counts indicates how many planes there are in the set of planes, PC corresponds to the number of planes, the PEC of the first portion corresponds to the first lifetime PEC, and the PEC of the second portion corresponds to the second lifetime PEC.

10. The system of claim 1, wherein the operations comprise: The first lifetime PEC is decreased at a different rate than the second lifetime PEC in response to the first request and the second request.

11. The system of claim 1 , wherein the operations comprise: selecting a plane count associated with the first portion; and A target PEC representing the number of remaining PECs of the first portion and the second portion after completing balancing the first lifetime PEC and the second lifetime PEC is calculated based on the plane count.

12. The system of claim 11, wherein the target PEC is calculated according to: wherein the PEC of the first portion corresponds to the first lifetime PEC, the PEC of the second portion corresponds to the second lifetime PEC, and a total plane count represents a number of planes in a memory die that includes the first portion.

13. The system of claim 1, wherein the operations comprise: selecting a target PEC for the set of memory components; calculating a plurality of numbers of planes to select from a set of planes for each memory die of a plurality of memory dies based on the target PEC, a total number of planes in the set of planes, the first lifetime PEC of the first portion, and the second lifetime PEC of the second portion; determining a scaling factor for each of the plurality of numbers of planes; and A plurality of plane selection tables are generated based on the plurality of plane numbers and the scaling factor, a first plane selection table of the plurality of plane selection tables corresponding to a first memory die of the plurality of memory die, and a second plane selection table of the plurality of plane selection tables corresponding to a second memory die of the plurality of memory die.

14. The system of claim 13, wherein: the first plane selection table comprising a first sequential time list corresponding to a first number of the scaling factors in the plurality of numbers, each sequential time in the first sequential time list being associated with an identifier of the plane selected from the set of planes of the first memory die; and The second plane selection table includes a second sequential time list corresponding to a second number of the scaling factors among the multiple numbers, each sequential time in the second sequential time list is associated with an identifier of the plane selected from the set of planes of the second memory die, and the first sequential time list and the second sequential time list have different numbers of sequential times.

15. The system of claim 14, wherein the operations comprise: obtaining a current PEC associated with the second portion of the set of memory components; dividing the current PEC by the scaling factor of the first number of the plurality of numbers of the first die to identify a remainder; and Individual sequential times are identified within the first plane selection table corresponding to the remainders.

16. The system of claim 15, wherein the operations comprise: retrieving the identifier of the plane selected from the set of planes of the first memory die corresponding to the individual sequential times; and The first memory operation is performed on a first subset of planes of the first memory die corresponding to the retrieved identifiers of the planes selected from the set of planes, and the first memory operation is not performed on a second subset of planes of the first memory die.

17. The system of claim 1, wherein the operations comprise: determining that a first current PEC of the first portion corresponds to a second current PEC of the second portion; and In response to determining that the first current PEC corresponds to the second current PEC, balancing the first lifetime PEC with the second lifetime PEC is stopped.

18. The system of claim 17, wherein stopping balancing comprises performing each of a plurality of memory operations received after the first current PEC corresponds to the second current PEC on the first portion and the second portion of the set of memory components.

19. A computerized method comprising: determining that a first lifetime program-erase count (PEC) of a first portion of a group of memory components is less than a second lifetime PEC of a second portion of the group of memory components; performing a first memory operation on the first portion and the second portion of the set of memory components in response to a first request associated with a block stripe including the set of memory components; erasing the block stripe including the first portion and the second portion of the set of memory components after performing the first memory operation; and After erasing the block stripe, a second memory operation is performed on the second portion of the set of memory components in response to a second request associated with the block stripe, and the second memory operation is not performed on the first portion of the set of memory components.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining that a first lifetime program-erase count (PEC) of a first portion of a group of memory components is less than a second lifetime PEC of a second portion of the group of memory components; performing a first memory operation on the first portion and the second portion of the set of memory components in response to a first request associated with a block stripe including the set of memory components; erasing the block stripe including the first portion and the second portion of the set of memory components after performing the first memory operation; and After erasing the block stripe, a second memory operation is performed on the second portion of the set of memory components in response to a second request associated with the block stripe, and the second memory operation is not performed on the first portion of the set of memory components.

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