Task scheduling method and device, equipment and medium

Abstract

The invention discloses a task scheduling method and device, equipment and a medium, and relates to the field of task processing.The task scheduling method comprises the steps that when a universal graphics processor writes a current calculation task into a current task queue, a normalized task priority and task execution estimated duration corresponding to the current calculation task are determined, and the task execution estimated duration is determined; the queue utilization rate of the current task queue is determined; determining a current load rate based on the task priority, the task execution estimated duration and the queue usage rate, and determining a target computing core from computing cores of the universal graphics processor according to the current load rate; each computing core comprises a tensor computing core and a computing core based on a unified computing device architecture; according to the method, the current computing task is scheduled to the target computing core, and the target computing core is used for executing the general matrix multiplication operation on the target matrix contained in the current computing task, so that each computing core in the general graphics processor is fully utilized, and hardware resources in the general graphics processor are utilized in a balanced and efficient manner.

Description

Technical Field

[0001] The present invention relates to the field of task processing, and in particular to a task scheduling method, device, equipment and medium. Background Art

[0002] In the digital age, machine learning applications are experiencing explosive growth and are widely used in many fields such as image recognition, speech processing, and natural language processing. As a result, the demand for computing performance is also increasing. In order to significantly accelerate the execution efficiency of machine learning applications, general-purpose computing on graphics processing units (GPGPU) innovatively introduced the key component of tensor cores. Tensor cores are specifically optimized for general matrix multiplication (GEMM), and as the core part of deep learning operations, the improvement of GEMM's computing speed is of vital importance to the performance improvement of machine learning applications.

[0003] In this type of GPGPU architecture equipped with tensor computing cores, the CUDA (Compute Unified Device Architecture) core inside the processor originally has the ability to perform general computing tasks. However, when the tensor computing core is fully engaged in the execution of GEMM-related instructions, the CUDA core is often idle, making it impossible to use the hardware resources inside the GPGPU in a balanced and efficient manner, resulting in low overall resource utilization and waste of hardware resources. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a task scheduling method, device, equipment and medium, which can calculate the current load rate of the current computing task in real time, and schedule the current computing task to the corresponding computing core in the general-purpose graphics processor according to the current load rate, so as to make full use of each computing core in the general-purpose graphics processor, so that the hardware resources in the general-purpose graphics processor can be used in a balanced and efficient manner. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a task scheduling method, which is applied to a general-purpose graphics processor, comprising:

[0006] When writing the current computing task into the current task queue, determining the normalized task priority and the estimated task execution duration corresponding to the current computing task, and determining the queue utilization rate of the current task queue;

[0007] Determine a current load rate based on the task priority, the estimated execution time of the task and the queue usage rate, and determine a target computing core from each computing core of the general-purpose graphics processor according to the current load rate; each computing core includes a tensor computing core and a computing core based on a unified computing device architecture;

[0008] The current computing task is dispatched to the target computing core so as to perform a general matrix multiplication operation on a target matrix included in the current computing task through the target computing core.

[0009] Optionally, determining a normalized task priority corresponding to the current computing task includes:

[0010] Obtaining a priority identifier of the current computing task, and determining a corresponding current priority value based on the priority identifier; wherein the priority value is positively correlated with the priority;

[0011] The current priority value is normalized using a preset maximum priority value and a preset minimum priority value to obtain a normalized task priority.

[0012] Optionally, determining a normalized estimated task execution duration corresponding to the current computing task includes:

[0013] Obtaining each target matrix that needs to participate in the general matrix multiplication operation from the current computing task, and determining the total number of elements of all elements contained in each target matrix;

[0014] The total number of elements is normalized using a preset maximum number of elements and a preset minimum number of elements to obtain a normalized result, and the normalized result is determined as the normalized estimated task execution duration.

[0015] Optionally, determining the total number of elements of all elements included in each target matrix includes:

[0016] Determine the dimension information corresponding to each of the target matrices; wherein the dimension information includes the number of matrix rows and the number of matrix columns;

[0017] The number of elements of all elements contained in the corresponding target matrix is ​​determined based on each of the dimensional information, and the number of elements of each of the target matrices is accumulated to obtain the total number of elements.

[0018] Optionally, determining the queue usage rate of the current task queue includes:

[0019] The total number of tasks of the pending computing tasks is obtained from the current task queue, and the queue utilization rate of the current task queue is determined based on the total number of tasks and the maximum number of tasks that can be stored in the current task queue.

[0020] Optionally, determining the target computing core from the computing cores of the general-purpose graphics processor according to the current load rate includes:

[0021] Determining whether the current load rate is less than a preset threshold;

[0022] If the current load rate is less than the preset threshold, determining the tensor computing core in the general-purpose graphics processor as the target computing core;

[0023] If the current load rate is not less than the preset threshold, a computing core based on a unified computing device architecture in the general-purpose graphics processor is determined as a target computing core.

[0024] Optionally, the step of scheduling the current computing task to the target computing core so as to perform a general matrix multiplication operation on a target matrix included in the current computing task through the target computing core includes:

[0025] When the target computing core is the tensor computing core, sending the matrix operation instruction corresponding to the current computing task to the tensor computing core, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the tensor computing core;

[0026] When the target computing core is the computing core based on the unified computing device architecture, instruction conversion is performed on the matrix operation instruction, and the converted instruction is sent to the computing core based on the unified computing device architecture, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the computing core based on the unified computing device architecture.

[0027] In a second aspect, the present application provides a task scheduling device, which is applied to a general-purpose graphics processor, comprising:

[0028] The first determination module is used to determine the normalized task priority and task execution estimated duration corresponding to the current computing task when writing the current computing task into the current task queue, and to determine the queue utilization rate of the current task queue

[0029] a second determination module, configured to determine a current load rate based on the task priority, the estimated execution time of the task, and the queue usage rate, and determine a target computing core from the computing cores of the general-purpose graphics processor according to the current load rate; the computing cores include a tensor computing core and a computing core based on a unified computing device architecture;

[0030] The task scheduling module is used to schedule the current computing task to the target computing core so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the target computing core.

[0031] In a third aspect, the present application provides an electronic device, including:

[0032] Memory, used to store computer programs;

[0033] The processor is used to execute the computer program to implement the aforementioned task scheduling method.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, wherein the computer program implements the aforementioned task scheduling method when executed by a processor.

[0035] In the present application, when a general-purpose graphics processor writes a current computing task into a current task queue, it determines the normalized task priority and estimated task execution duration corresponding to the current computing task, and determines the queue utilization rate of the current task queue; determines the current load rate based on the task priority, the estimated task execution duration, and the queue utilization rate, and determines a target computing core from among the computing cores of the general-purpose graphics processor according to the current load rate; the computing cores include tensor computing cores and computing cores based on a unified computing device architecture; and schedules the current computing task to the target computing core so as to perform a general matrix multiplication operation on the target matrix contained in the current computing task through the target computing core. It can be seen that when writing the current computing task into the task queue, the present application comprehensively determines the current load rate through the task priority, the estimated task execution time and the queue utilization rate, and schedules the current computing task to the corresponding computing core in the general-purpose graphics processor according to the current load rate, so as to make full use of each computing core in the general-purpose graphics processor, which can not only make the hardware resources in the general-purpose graphics processor be used in a balanced and efficient manner, reduce the waste of hardware resources, and improve the overall resource utilization, but also improve the overall throughput of the general-purpose graphics processor through multiple computing cores; moreover, the present application can also ensure the execution efficiency of each computing task through multiple computing cores, and ensure that the highest possible performance level is achieved when executing each computing task. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A flowchart of a task scheduling method disclosed in this application;

[0038] Figure 2 A general graphics processor architecture diagram disclosed in this application;

[0039] Figure 3 A specific task scheduling flow chart disclosed in this application;

[0040] Figure 4 This is a structural schematic diagram of a task scheduling device disclosed in this application;

[0041] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In a GPGPU architecture equipped with a tensor computing core, the CUDA core inside the processor originally has the ability to perform general computing tasks. However, when the tensor computing core is fully engaged in the execution of GEMM-related instructions, the CUDA core is often idle, which makes it impossible to use the hardware resources inside the GPGPU in a balanced and efficient manner, resulting in low overall resource utilization and waste of hardware resources. To this end, the present application provides a task scheduling method, which calculates the current load rate of the current computing task in real time, and schedules the current computing task to the corresponding computing core in the general graphics processor according to the current load rate, so as to make full use of each computing core in the general graphics processor and make the hardware resources in the general graphics processor balanced and efficient.

[0044] See also Figure 1 As shown, an embodiment of the present invention discloses a task scheduling method, which is applied to a general-purpose graphics processor, comprising:

[0045] Step S11, when writing the current computing task into the current task queue, determining the normalized task priority and task execution estimated duration corresponding to the current computing task, and determining the queue utilization rate of the current task queue.

[0046] In an embodiment of the present invention, when the current computing task enters the current task queue, the normalized task priority corresponding to the current computing task is determined, the normalized task execution estimated duration corresponding to the current computing task is determined, and the queue utilization rate of the current task queue is determined.

[0047] For the normalized task priority corresponding to the current computing task, first obtain the priority identifier of the current computing task, and determine the corresponding current priority value based on the priority identifier of the current computing task; then use the preset maximum priority value and the preset minimum priority value to normalize the current priority value to obtain the normalized task priority.

[0048] Among them, different priority identifiers correspond to different priority values, and the priority value is positively correlated with the priority, that is, the larger the priority value, the higher the priority; the smaller the priority value, the lower the priority. It should be noted that the priority value can be set to a continuous value, for example, the priority value can be set to 1, 2, 3... and so on.

[0049] The normalization process of the current priority value may specifically be: calculating a first difference between the current priority value and the preset minimum priority value, and calculating a second difference between the preset maximum priority value and the preset minimum priority value, and then determining the normalized task priority based on the ratio of the first difference to the second difference. That is, the normalized task priority = (current priority value - preset minimum priority value) / (preset maximum priority value - preset minimum priority value).

[0050] For the normalized task execution estimated duration corresponding to the current computing task, first obtain each target matrix that needs to participate in the general matrix multiplication operation from the current computing task, and determine the total number of elements of all elements contained in each target matrix; then use the preset maximum number of elements and the preset minimum number of elements to normalize the total number of elements to obtain a normalized result, and determine the normalized result as the normalized task execution estimated duration.

[0051] Among them, for the total number of elements, first obtain each target matrix that needs to participate in the general matrix multiplication operation from the current computing task, and determine the dimension information corresponding to each target matrix, wherein the dimension information includes the number of matrix rows and the number of matrix columns; then determine the number of elements of all elements contained in the corresponding target matrix based on each dimension information, that is, determine the number of elements of all elements contained in the corresponding target matrix based on the product result between the number of matrix rows and the number of matrix columns. After obtaining the number of elements of each target matrix, accumulate the number of elements of each target matrix to obtain the total number of elements.

[0052] After obtaining the total number of elements, a third difference between the total number of elements and the preset minimum number of elements is calculated, and a fourth difference between the preset maximum number of elements and the preset minimum number of elements is calculated, and then a normalization processing result is determined based on the ratio of the third difference and the fourth difference, so that the normalization processing result is determined as the normalized task execution estimated duration. That is, the normalized task execution estimated duration = (total number of elements - preset minimum number of elements) / (preset maximum number of elements - preset minimum number of elements).

[0053] For the queue utilization rate of the current task queue, first obtain the total number of tasks of the pending computing tasks from the current task queue, and determine the queue utilization rate of the current task queue based on the total number of tasks and the maximum number of tasks that the current task queue can store. That is, the queue utilization rate of the current task queue = the total number of tasks of the pending computing tasks / the maximum number of tasks.

[0054] Step S12, determining the current load rate based on the task priority, the estimated execution time of the task and the queue usage rate, and determining the target computing core from the computing cores of the general-purpose graphics processor according to the current load rate; the computing cores include tensor computing cores and computing cores based on a unified computing device architecture.

[0055] In the embodiment of the present invention, after determining the normalized task priority, the normalized task execution estimated duration, and the queue utilization rate of the current task queue, the task priority, the task execution estimated duration, and the queue utilization rate are weighted based on a preset weight coefficient to obtain the current load rate. It should be noted that the task priority, the task execution estimated duration, and the queue utilization rate each correspond to a weight coefficient, and the sum of the three weight coefficients is 1.

[0056] Furthermore, after determining the current load rate, a target computing core is determined from each computing core of the general-purpose graphics processor according to the current load rate. Specifically, it is determined whether the current load rate is less than a preset threshold; if the current load rate is less than the preset threshold, the tensor computing core in the general-purpose graphics processor is determined as the target computing core; if the current load rate is not less than the preset threshold, the computing core based on the unified computing device architecture in the general-purpose graphics processor is determined as the target computing core.

[0057] Step S13: dispatching the current computing task to the target computing core, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the target computing core.

[0058] In an embodiment of the present invention, after determining the target computing core according to the current load rate, the current computing task is scheduled to the target computing core so that a general matrix multiplication operation is performed on the target matrix included in the current computing task through the target computing core.

[0059] It should be noted that when the target computing core is a tensor computing core, the matrix operation instruction corresponding to the current computing task is sent to the tensor computing core, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the tensor computing core;

[0060] It should also be noted that when the target computing core is a computing core based on a unified computing device architecture, instruction conversion is performed on the matrix operation instructions corresponding to the current computing task, and the converted instructions are sent to the computing core based on the unified computing device architecture, so that the computing core based on the unified computing device architecture can perform general matrix multiplication operations on the target matrix contained in the current computing task.

[0061] It can be found that the normalized task priority, the normalized task execution estimated duration, and the queue utilization rate of the current task queue in this embodiment are all between 0 and 1. The purpose is to more reasonably reflect the relative situation of computing tasks of different scales in the overall decision-making factors, thereby providing a key basis for task scheduling decisions, so that each computing core in the general-purpose graphics processor can be used in a balanced and efficient manner, avoiding the problem of excessive occupation of the resources of a computing core caused by running a computing core for a long time.

[0062] It can be seen that when writing the current computing task into the task queue, the present application comprehensively determines the current load rate through the task priority, the estimated task execution time and the queue utilization rate, and schedules the current computing task to the corresponding computing core in the general-purpose graphics processor according to the current load rate, so as to make full use of each computing core in the general-purpose graphics processor, which can not only make the hardware resources in the general-purpose graphics processor be used in a balanced and efficient manner, reduce the waste of hardware resources, and improve the overall resource utilization, but also improve the overall throughput of the general-purpose graphics processor through multiple computing cores; moreover, the present application can also ensure the execution efficiency of each computing task through multiple computing cores, and ensure that the highest possible performance level is achieved when executing each computing task.

[0063] See also Figure 2 and Figure 3 As shown, an embodiment of the present invention discloses a task scheduling method, which is applied to a general-purpose graphics processor, wherein the general-purpose graphics processor includes a task priority monitoring module, a matrix scale calculation module, a queue monitoring module, a load rate calculation module, a scheduler, an instruction converter, a Cuda computing core, and a tensor computing core; the task scheduling method specifically includes:

[0064] When the general-purpose graphics processor is started, the task priority monitoring module, matrix scale calculation module, and queue monitoring module are initialized to ensure that the initialized task priority monitoring module, matrix scale calculation module, and queue monitoring module can accurately collect and identify the corresponding data information. The load rate calculation module is initialized to store the weight coefficients corresponding to the task priority, task execution estimated duration, and queue utilization rate in the local register for subsequent calculations. At the same time, the scheduler is initialized to ensure that the initialized scheduler can receive the load rate sent by the load rate calculation module and determine the computing core that needs to be scheduled based on the load rate.

[0065] When the current computing task enters the current task queue, the priority identifier carried by the current computing task is immediately captured by the task priority monitoring module, and the corresponding current priority value is determined based on the priority identifier carried by the current computing task, and then the current priority value is normalized using the preset maximum priority value and the preset minimum priority value to obtain the normalized task priority; the normalized task priority is stored in a local register, and an interrupt signal is sent to the load rate calculation module to notify the load rate calculation module that there is a new task priority.

[0066] The matrix scale calculation module obtains each target matrix that needs to participate in the general matrix multiplication operation from the current computing task, and determines the dimension information including the number of matrix rows and the number of matrix columns corresponding to each target matrix, and then uses the hardware multiplier and determines the number of elements of all elements contained in the corresponding target matrix based on the dimension information, that is, the hardware multiplier calculates the product result between the number of matrix rows and the number of matrix columns in each dimension information, and determines the product result as the number of elements of all elements contained in the corresponding target matrix, and then accumulates the number of elements of each target matrix to obtain the total number of elements. Further, the matrix scale calculation module uses the preset maximum number of elements and the preset minimum number of elements to normalize the total number of elements to obtain the normalized processing result, and determines the normalized processing result as the normalized task execution estimated duration; the normalized task execution estimated duration is stored in the local register, and a data update signal is sent to the load rate calculation module to notify the load rate calculation module that there is a new task execution estimated duration.

[0067] The total number of tasks to be processed in the current task queue is obtained through the queue monitoring module, and the queue utilization rate of the current task queue is determined based on the total number of tasks and the maximum number of tasks that can be stored in the current task queue; the queue utilization rate of the current task queue is stored in a local register, and a load signal is sent to the load rate calculation module to notify the load rate calculation module of a new queue utilization rate. When the queue utilization rate is greater than the preset utilization rate, the load signal is a high load signal; when the queue utilization rate is less than or equal to the preset utilization rate, the load signal is a normal load signal.

[0068] After receiving the signals sent by the task priority monitoring module, the matrix scale calculation module and the queue monitoring module, the load rate calculation module reads the latest normalized task priority, the normalized task execution estimated duration, and the queue utilization rate of the current task queue from the registers of the task priority monitoring module, the registers of the matrix scale calculation module, and the registers of the queue monitoring module, respectively, and performs weighted calculation on the task priority, the task execution estimated duration, and the queue utilization rate based on the pre-stored weight coefficient to obtain the current load rate.

[0069] The scheduler continuously queries the load rate calculation module to obtain the current load rate and determines whether the current load rate is less than the preset threshold. If the current load rate is less than the preset threshold, the scheduler sends the matrix operation instruction corresponding to the current computing task to the tensor computing core, so that the tensor computing core performs a general matrix multiplication operation on the target matrix included in the current computing task; wherein the matrix operation instruction may be a WMMA (Warp-level Matrix Multiply Accumulate) instruction. If the current load rate is greater than or equal to the preset threshold, the scheduler uses the instruction converter to convert the matrix operation instruction corresponding to the current computing task, and sends the converted instruction to the Cuda computing core, so that the Cuda computing core performs a general matrix multiplication operation on the target matrix included in the current computing task; wherein, when the matrix operation instruction is a WMMA instruction, the converted instruction may be a MAC (Multiply Accumulate) instruction.

[0070] It can be seen that when writing the current computing task into the task queue, the present embodiment comprehensively determines the current load rate through the task priority, the estimated task execution time and the queue utilization rate, and schedules the current computing task to the corresponding computing core in the general-purpose graphics processor according to the current load rate, so as to make full use of each computing core in the general-purpose graphics processor, which can not only make the hardware resources in the general-purpose graphics processor be used in a balanced and efficient manner, reduce the waste of hardware resources, and improve the overall resource utilization, but also improve the overall throughput of the general-purpose graphics processor through multiple computing cores; and, the present embodiment can also ensure the execution efficiency of each computing task through multiple computing cores, and ensure that a higher performance level is achieved as much as possible when executing each computing task.

[0071] See also Figure 4 As shown, an embodiment of the present invention discloses a task scheduling device, which is applied to a general-purpose graphics processor, comprising:

[0072] A first determination module 11 is used to determine the normalized task priority and task execution estimated duration corresponding to the current computing task when writing the current computing task into the current task queue, and determine the queue utilization rate of the current task queue;

[0073] A second determination module 12 is used to determine a current load rate based on the task priority, the estimated execution time of the task and the queue usage rate, and determine a target computing core from each computing core of the general-purpose graphics processor according to the current load rate; each computing core includes a tensor computing core and a computing core based on a unified computing device architecture;

[0074] The task scheduling module 13 is used to schedule the current computing task to the target computing core so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the target computing core.

[0075] It can be seen that when writing the current computing task into the task queue, the present application comprehensively determines the current load rate through the task priority, the estimated task execution time and the queue utilization rate, and schedules the current computing task to the corresponding computing core in the general-purpose graphics processor according to the current load rate, so as to make full use of each computing core in the general-purpose graphics processor, which can not only make the hardware resources in the general-purpose graphics processor be used in a balanced and efficient manner, reduce the waste of hardware resources, and improve the overall resource utilization, but also improve the overall throughput of the general-purpose graphics processor through multiple computing cores; moreover, the present application can also ensure the execution efficiency of each computing task through multiple computing cores, and ensure that the highest possible performance level is achieved when executing each computing task.

[0076] In some specific embodiments, the first determining module 11 includes:

[0077] A priority value determination unit, used to obtain the priority identifier of the current computing task, and determine the corresponding current priority value based on the priority identifier; wherein the priority value is positively correlated with the priority;

[0078] The first normalization unit is used to normalize the current priority value by using a preset maximum priority value and a preset minimum priority value to obtain a normalized task priority.

[0079] In some specific embodiments, the first determining module 11 includes:

[0080] An element number determination submodule, used to obtain each target matrix that needs to participate in the general matrix multiplication operation from the current computing task, and determine the total number of elements of all elements contained in each target matrix;

[0081] The second normalization unit is used to normalize the total number of elements using a preset maximum number of elements and a preset minimum number of elements to obtain a normalized processing result, and determine the normalized processing result as the normalized task execution estimated duration.

[0082] In some specific embodiments, the element quantity determination submodule includes:

[0083] A dimension information determination unit, used to determine the dimension information corresponding to each of the target matrices; wherein the dimension information includes the number of matrix rows and the number of matrix columns;

[0084] The total number of elements determining unit is used to determine the number of elements of all elements contained in the corresponding target matrix based on each of the dimensional information, and accumulate the number of elements of each of the target matrices to obtain the total number of elements.

[0085] In some specific embodiments, the first determining module 11 includes:

[0086] The queue usage determination unit is used to obtain the total number of tasks of the pending computing tasks from the current task queue, and determine the queue usage of the current task queue based on the total number of tasks and the maximum number of tasks that can be stored in the current task queue.

[0087] In some specific embodiments, the second determining module 12 includes:

[0088] A load rate determination unit, used to determine whether the current load rate is less than a preset threshold;

[0089] a first computing core determining unit, configured to determine a tensor computing core in the general purpose graphics processor as a target computing core if the current load rate is less than the preset threshold;

[0090] The second computing core determining unit is configured to determine a computing core based on a unified computing device architecture in the general-purpose graphics processor as a target computing core if the current load rate is not less than the preset threshold.

[0091] In some specific embodiments, the task scheduling module 13 includes:

[0092] a first matrix operation unit, configured to send a matrix operation instruction corresponding to the current computing task to the tensor computing core when the target computing core is the tensor computing core, so as to perform a general matrix multiplication operation on a target matrix included in the current computing task through the tensor computing core;

[0093] The second matrix operation unit is used to perform instruction conversion on the matrix operation instruction when the target computing core is the computing core based on the unified computing device architecture, and send the converted instruction to the computing core based on the unified computing device architecture, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the computing core based on the unified computing device architecture.

[0094] Furthermore, the present application also discloses an electronic device. Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0095] Figure 5A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the task scheduling method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0096] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0097] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0098] The operating system 221 is used to manage and control the hardware devices on the electronic device 20 and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the task scheduling method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0099] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed task scheduling method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0100] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0101] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0102] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0103] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0104] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A task scheduling method, characterized in that: Applicable to general-purpose graphics processors, including: When writing the current computing task into the current task queue, determining the normalized task priority and the estimated task execution duration corresponding to the current computing task, and determining the queue utilization rate of the current task queue; Determine a current load rate based on the task priority, the estimated execution time of the task and the queue usage rate, and determine a target computing core from each computing core of the general-purpose graphics processor according to the current load rate; each computing core includes a tensor computing core and a computing core based on a unified computing device architecture; The current computing task is dispatched to the target computing core so as to perform a general matrix multiplication operation on a target matrix included in the current computing task through the target computing core.

2. The task scheduling method according to claim 1, characterized in that: Determining a normalized task priority corresponding to the current computing task includes: Obtaining a priority identifier of the current computing task, and determining a corresponding current priority value based on the priority identifier; wherein the priority value is positively correlated with the priority; The current priority value is normalized using a preset maximum priority value and a preset minimum priority value to obtain a normalized task priority.

3. The task scheduling method according to claim 1, characterized in that: Determining a normalized estimated task execution duration corresponding to the current computing task includes: Obtaining each target matrix that needs to participate in the general matrix multiplication operation from the current computing task, and determining the total number of elements of all elements contained in each target matrix; The total number of elements is normalized using a preset maximum number of elements and a preset minimum number of elements to obtain a normalized result, and the normalized result is determined as the normalized estimated task execution duration.

4. The task scheduling method according to claim 3, characterized in that: Determining the total number of elements of all elements contained in each target matrix includes: Determine the dimension information corresponding to each of the target matrices; wherein the dimension information includes the number of matrix rows and the number of matrix columns; The number of elements of all elements contained in the corresponding target matrix is ​​determined based on each of the dimensional information, and the number of elements of each of the target matrices is accumulated to obtain the total number of elements.

5. The task scheduling method according to claim 1, characterized in that: The determining the queue usage rate of the current task queue includes: The total number of tasks of the pending computing tasks is obtained from the current task queue, and the queue utilization rate of the current task queue is determined based on the total number of tasks and the maximum number of tasks that can be stored in the current task queue.

6. The task scheduling method according to claim 1, characterized in that: The step of determining a target computing core from among the computing cores of the general purpose graphics processor according to the current load rate includes: Determining whether the current load rate is less than a preset threshold; If the current load rate is less than the preset threshold, determining the tensor computing core in the general-purpose graphics processor as the target computing core; If the current load rate is not less than the preset threshold, a computing core based on a unified computing device architecture in the general-purpose graphics processor is determined as a target computing core.

7. The task scheduling method according to any one of claims 1 to 6, characterized in that: The step of dispatching the current computing task to the target computing core so as to perform a general matrix multiplication operation on a target matrix included in the current computing task through the target computing core includes: When the target computing core is the tensor computing core, sending the matrix operation instruction corresponding to the current computing task to the tensor computing core, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the tensor computing core; When the target computing core is the computing core based on the unified computing device architecture, instruction conversion is performed on the matrix operation instruction, and the converted instruction is sent to the computing core based on the unified computing device architecture, so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the computing core based on the unified computing device architecture.

8. A task scheduling device, characterized in that: Applicable to general-purpose graphics processors, including: A first determination module is used to determine the normalized task priority and task execution estimated duration corresponding to the current computing task when writing the current computing task into the current task queue, and determine the queue utilization rate of the current task queue; a second determination module, configured to determine a current load rate based on the task priority, the estimated execution time of the task, and the queue usage rate, and determine a target computing core from the computing cores of the general-purpose graphics processor according to the current load rate; the computing cores include a tensor computing core and a computing core based on a unified computing device architecture; The task scheduling module is used to schedule the current computing task to the target computing core so as to perform a general matrix multiplication operation on the target matrix included in the current computing task through the target computing core.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the task scheduling method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the task scheduling method according to any one of claims 1 to 7.

Images