High-speed hybrid floating point division and extraction operation system

Abstract

The invention provides a high-speed hybrid floating-point division and extraction operation system, which comprises a table look-up module for receiving and processing to-be-processed data and outputting initial approximate data of the to-be-processed data after floating-point operation; the iteration module is connected to the table look-up module, receives the initial approximate data, performs multiplication processing on the initial approximate data for at least two times, and obtains first approximate data; and the rounding module is connected with the iteration module, receives the first approximate data, adjusts the digits of the first approximate data according to the floating point operation as single-precision floating point operation or double-precision floating point operation, and obtains and outputs second approximate data. The invention provides a high-speed hybrid floating point division and extraction operation system, which realizes efficient error analysis while saving hardware resources, and considers the universality of hardware configuration.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a high-speed mixed floating-point division and square root operation system. Background Art

[0002] With the continuous development of the integrated circuit field, the demand for computer computing power for cutting-edge algorithms has increased significantly. As a common operation, floating-point arithmetic has also seen performance requirements rise with the development of the times and advancements in semiconductor technology. Floating-point arithmetic is real-number arithmetic. Because computers can only store integers, real numbers are approximate, resulting in slow calculation speeds and errors. For example, the different graphics rendering capabilities of different gaming machines are a reflection of the differences in floating-point computing power. Within a computer's central processing unit (CPU), the floating-point unit (FPU) supports specific floating-point arithmetic methods. Among these various arithmetic methods, floating-point division and square root operations have long been considered the most time-consuming and complex operations, and have long been hot topics in computer arithmetic.

[0003] Floating-point arithmetic methods are difficult to strike a balance between speed and accuracy. Applying floating-point arithmetic methods in the field of integrated circuit design makes it difficult to achieve efficient error analysis while saving hardware resources, and it is also difficult to strike a balance between universality and hardware configuration. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-speed hybrid floating-point division and square root operation system, which saves hardware resources, realizes efficient error analysis, and takes into account the universality of hardware configuration.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a high-speed hybrid floating-point division and square root operation system, comprising:

[0007] A table lookup module receives and processes the data to be processed, and outputs initial approximate data of the data to be processed after floating-point operation;

[0008] an iterative module connected to the table lookup module and receiving the initial approximate data, the iterative module performing at least two multiplication processes on the initial approximate data and obtaining first approximate data; and

[0009] A rounding module is connected to the iteration module and receives the first approximate data. According to whether the floating-point operation is a single-precision floating-point operation or a double-precision floating-point operation, the rounding module adjusts the number of bits of the first approximate data to obtain and output second approximate data.

[0010] In one embodiment of the present invention, the floating-point operation is a division operation or a square root operation, and the data to be processed is a dividend or a square root. When the data to be processed is the dividend, the initial approximate data is an approximate quotient of the dividend after the division operation; when the data to be processed is the square root, the initial approximate data is an approximate square root of the square root after the square root operation.

[0011] In one embodiment of the present invention, the table lookup module includes a dual-structure lookup table, and the dual-structure lookup table includes a first lookup table and a second lookup table, wherein the first lookup table and the second lookup table are respectively established based on partial bit data of the data to be processed, and a fitting result after subtracting the first lookup table from the second lookup table is used as the reciprocal approximation or reciprocal square root of the data to be processed, and the product of the reciprocal approximation and the data to be processed or the product of the reciprocal square root and the data to be processed is used as the initial approximation.

[0012] In one embodiment of the present invention, the table building data of the first lookup table includes the high-order data and the median data of the data to be processed, and the table building data of the second lookup table includes the high-order data and the low-order data of the data to be processed, wherein the high-order data is the portion of the bits on the left side of the bit width order of the data to be processed, the low-order data is the portion of the bits on the right side of the bit width order of the data to be processed, and the median data is the portion of the bits in the data to be processed that are located between the high-order data and the low-order data, wherein the number of bits of the high-order data, the median data and the low-order data are the same.

[0013] In one embodiment of the present invention, the iteration module includes at least four multipliers, and the four multipliers perform at least two multiplication iterations on the initial approximate data, wherein when the floating-point operation is a division operation, the first multiplier and the second multiplier are electrically connected to the table lookup module and operate in parallel within a first clock, and the third multiplier and the fourth multiplier are electrically connected to the first multiplier and the second multiplier and operate within a second clock.

[0014] In one embodiment of the present invention, the iteration module includes at least four multipliers, and the four multipliers perform at least two multiplication iterations on the initial approximate data. When the floating-point operation is a square root operation, the first multiplier is electrically connected to the table lookup module and operates within a first clock, the second multiplier is electrically connected to the first multiplier and operates within a second clock, and the third multiplier and the fourth multiplier are electrically connected to the second multiplier and operate within a third clock.

[0015] In one embodiment of the present invention, the iteration module includes at least one complementary precision multiplier, and the complementary precision multiplier is electrically connected to the third multiplier, the fourth multiplier and the rounding module through a control switch.

[0016] In one embodiment of the present invention, the operation system includes a controller. When the data accuracy output by the iteration module does not meet the accuracy requirement of the rounding module, the controller controls the control switch to close and connects at least one of the supplementary precision multipliers to the output ends of the third multiplier and the fourth multiplier and the access end of the rounding module.

[0017] In one embodiment of the present invention, the rounding module stores a rounding rule for the first approximate data, and the rounding rule includes the IEEE754 standard.

[0018] In one embodiment of the present invention, the rounding module includes a back-multiplication unit, which is electrically connected to an output end of the iteration module and receives the first approximate data. The back-multiplication unit outputs a product of the second approximate data and a divisor of the data to be processed as comparison data, and obtains a sign bit of the second approximate data based on a difference between the comparison data and the data to be processed.

[0019] As described above, the present invention provides a high-speed hybrid floating-point division and square root operation system, which truncates the bit width based on absolute error analysis, can reflect the convergence and accumulation of the iterative bit width truncation error, and impose different degrees of error range restrictions on errors of different properties, so as to minimize the redundant bit width of the intermediate iterative process while ensuring that the final calculation result meets the IEEE-754 rounding standard, thereby improving the calculation speed and reducing unnecessary computing resources. In addition, based on the proposed algorithm, the present invention proposes a dedicated hardware architecture to effectively tap the advantages of the algorithm. The algorithm proposed in the present invention is not only applicable to floating-point division operations, but also to floating-point square root operations, and can reasonably adjust the intermediate process iterative bit width of the two operations through error analysis to achieve the greatest possible resource reuse. The algorithm provided by the present invention uses the first iteration result as the result of single-precision floating-point division and square root operations, which can meet the single-precision rounding requirements, and uses the second iteration result as the result of double-precision floating-point division and square root operations, which can meet the double-precision rounding requirements. The single-precision floating-point operation is integrated into the double-precision floating-point operation, further improving resource reuse and optimizing circuit area. The present invention proposes a pipeline-based floating-point operation computing architecture that can maximize computing throughput and achieve higher computing efficiency.

[0020] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 FIG. 1 is a schematic diagram of the structure of an operation system in one embodiment of the present invention.

[0023] Figure 2 FIG. 1 is a structural diagram of a table lookup module in an embodiment of the present invention.

[0024] Figure 3 2 is a diagram illustrating the implementation principle of a dual-structure lookup table in one embodiment of the present invention.

[0025] Figure 4 FIG. 1 is a schematic diagram of the operating structure of an iterative module performing a single-precision division operation in one embodiment of the present invention.

[0026] Figure 5 FIG. 1 is a schematic diagram of the operating structure of an iterative module performing a double-precision division operation in one embodiment of the present invention.

[0027] Figure 6 FIG. 1 is a schematic diagram of the operating structure of an iterative module performing a single-precision square root operation in one embodiment of the present invention.

[0028] Figure 7 FIG. 1 is a schematic diagram of the operating structure of an iterative module performing a double-precision square root operation in one embodiment of the present invention.

[0029] In the figure: 100, operation system; 200, table lookup module; 210, first input unit; 220, dual-structure lookup table; 230, exponent and sign bit processor; 300, iteration module; 310, second input unit; 320, first multiplier; 330, second multiplier; 340, third multiplier; 350, fourth multiplier; 360, complementary precision multiplier; 361, fifth multiplier; 362, sixth multiplier; 370, controller; 400, rounding module; 410, back multiplication unit. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] Floating-point arithmetic methods include floating-point division and square root operations. Algorithms for implementing floating-point division and square root operations include bit-by-bit looping and function iteration algorithms. Bit-by-bit looping algorithms include restoring, non-restoring, and SRT algorithms. Limited by the linear growth of the quotient precision, bit-by-bit looping algorithms are slow. Function iteration algorithms include the Newton-Raphson algorithm and the Goldschmidt algorithm. In the Newton-Raphson algorithm, division is performed through multiple multiplications, starting with an approximation of the reciprocal of the divisor. Each iteration doubles the precision, ultimately multiplying the result with the dividend. In the Goldschmidt algorithm, the multiplications in the Newton-Raphson algorithm are converted into parallel, independent calculations, significantly reducing computational latency. However, the Goldschmidt algorithm can accumulate errors during iterations, leading to erroneous results, especially when hardware bit width is limited. Therefore, the application of the Goldschmidt algorithm relies on efficient error analysis to ensure accurate rounding while conserving hardware resources.

[0032] A variety of hardware can be developed based on floating-point arithmetic methods. However, the development and application of this hardware relies on efficient error analysis. For example, hardware dividers developed based on the Goldschmidt algorithm, including the AMD-K7 divider, utilize a lookup table before iteration to provide a high-precision initial reciprocal approximation, accelerating error convergence. During the iterative error analysis, the AMD-K7 divider overestimates the error to ensure the accuracy of the analysis results. However, this error analysis relies on a mechanical proof performed by a computer, requiring hundreds or even thousands of definitions and lemmas. Therefore, the AMD-K7 divider, based on error analysis, utilizes 7 bits of additional precision in its iterative calculations. Error analysis methods within floating-point arithmetic methods also include parameterized error analysis. These methods simplify the mathematical expressions used to describe the iterative process after the introduction of errors, utilizing various mathematical transformations and scaling techniques. Ultimately, they derive an analytical expression based on relative error that can be used to measure the magnitude of the accumulated error. Because the final result of the parameterized error analysis method includes a relatively complex sub-term, this method limits the accuracy of the intermediate results during the iteration process. Therefore, the parameterized error analysis method is not easy to generalize and analyze other hardware configurations. The error analysis method of the floating-point operation method also includes an error value method to obtain upper and lower error bounds. That is, the two iteration parameters in the iteration process are treated as fractions. When the error of the numerator and denominator is maximum and minimum, the upper error bound can be obtained. Otherwise, the lower error bound can be obtained. However, the error value method for obtaining upper and lower error bounds also limits the rounding method of some coefficients during the iteration.

[0033] See also Figure 1 As shown, the present invention provides a high-speed hybrid floating-point division and square root operation system. The operation system 100 includes a table lookup module 200, an iteration module 300, and a rounding module 400. The table lookup module 200 receives and processes the data to be processed and outputs initial approximate data after the floating-point operation. The iteration module 300 is connected to the table lookup module 200 and receives the initial approximate data. The iteration module 300 performs at least two multiplication operations on the initial approximate data to obtain first approximate data. The rounding module 400 is connected to the iteration module 300 and receives the first approximate data. Depending on whether the floating-point operation is a single-precision floating-point operation or a double-precision floating-point operation, the rounding module 400 adjusts the number of bits of the first approximate data to obtain and output second approximate data. The floating-point operation is either a division operation or a square root operation, and the data to be processed is the dividend. When the data to be processed is the dividend, the initial approximate data is the approximate quotient of the dividend after the division operation. When the data to be processed is the square root, the initial approximate data is the approximate square root of the square root after the square root operation.

[0034] See also Figure 1 and Figure 2 As shown, in the present invention, the table lookup module 200 includes a first input unit 210, a dual-structure lookup table 220, and an exponent and sign bit processor 230. The first input unit 210 is used to input data to be processed. When the floating-point operation is a division operation, the data to be processed may include a dividend and a divisor. When the floating-point operation is a square root operation, the data to be processed may include a square root. The dual-structure lookup table 220 includes a first lookup table and a second lookup table. The first lookup table and the second lookup table are respectively constructed based on partial bit data of the data to be processed, and the fitting result after subtracting the first lookup table and the second lookup table is used as the reciprocal approximation or reciprocal square root of the data to be processed, and the product of the reciprocal approximation and the data to be processed or the product of the reciprocal square root and the data to be processed is used as the initial approximation. Specifically, the reciprocal approximation or reciprocal square root of the data to be processed is obtained through the dual-structure lookup table 220. In the division operation, the product of the reciprocal approximate value of the data to be processed and the divisor, as well as the product of the reciprocal approximate value of the data to be processed and the dividend, is then obtained, thereby obtaining the initial approximate data of the data to be processed after the division operation. In the square root operation, the reciprocal square root of the radicand is obtained by using the exponent parity determination lookup table, and the reciprocal square root is then multiplied by the radicand to obtain a lower-precision root value, which is used as the initial approximate data of the data to be processed after the square root operation.

[0035] See also Figures 1 to 3As shown, in the present invention, the table building data of the first lookup table includes the high-order data and the median data of the data to be processed, and the table building data of the second lookup table includes the high-order data and the low-order data of the data to be processed, wherein the high-order data is the portion of the digits on the left of the bit width order of the data to be processed, the low-order data is the portion of the digits on the right of the bit width order of the data to be processed, and the median data is the portion of the digits in the data to be processed that is located between the high-order data and the low-order data. In this embodiment, the number of bits of the high-order data, the median data and the low-order data is the same. For example, for a single input of data with a bit width of 15 bits, the leftmost 5 bits of the data are high-order, and the rightmost 5 bits are low-order. In this embodiment, based on the calculation method of the lookup table, the first lookup table is obtained by the high-order data and the median data, and the first lookup table can reflect the absolute height of the fitting function in each value interval. The second lookup table is obtained by the high-order data and the low-order data, and the second lookup table can reflect the relative height of each value interval. Subtracting the value of the second lookup table from the first lookup table can obtain the initial approximate data. As shown Figure 3 As shown, Figure 3 The horizontal axis represents the data to be processed, where the blue curve represents the ideal function graph, and the red curve represents the fitted function graph of the reciprocal approximation or reciprocal square root obtained by the dual-body structure lookup table 220. The P value represents the absolute height of each value interval, while within a single value interval, the span of the red curve on the y-axis represents the relative height of the fitted function within that single value interval. The dual-body lookup table is suitable for smooth functions, so both the reciprocal approximation and the reciprocal square root can be obtained with higher accuracy using the dual-body lookup table. In this embodiment, the lookup table module 200200 can obtain initial error data with a relative error less than 2^{-14.6103}. In the present invention, the initial error data will decrease with subsequent iterations. It should be noted that the lookup table can be implemented in a circuit using combinational logic.

[0036] See also Figure 1 、 Figure 4 and Figure 6As shown, in the present invention, the iteration module 300 includes a second input unit 310 and at least four multipliers, and the four multipliers perform at least two multiplication iterations on the initial approximate data, thereby improving the calculation accuracy of the initial approximate data. The four multipliers are labeled as a first multiplier 320, a second multiplier 330, a third multiplier 340, and a fourth multiplier 350. In one embodiment of the present invention, when the floating-point operation is a division operation, the first multiplier 320 and the second multiplier 330 are electrically connected to the lookup table module 200 and operate in parallel within the first clock, and the third multiplier 340 and the fourth multiplier 350 are electrically connected to the first multiplier 320 and the second multiplier 330 and operate within the second clock. The time length of the first clock and the second clock is determined by the clock unit of the computer, wherein the first clock is located before the second clock, and the first clock and the second clock are continuous. Figure 4 FIG. 1 is a flow chart of a single-precision division operation circuit of a floating-point unit. The dividend as an input first passes through a lookup table to obtain a low-precision reciprocal approximation result. The table lookup result is then multiplied by the divisor and dividend respectively to obtain a low-precision quotient. The quotient is then iterated through a Goldschmidt algorithm to achieve quadratic convergence to obtain a higher-precision quotient. The quotient is then sent to the final rounding module 400 to obtain a floating-point division operation result that meets the rounding requirements. Figure 6 The figure is a flow chart of the floating-point unit double-precision division operation system 100. The dividend as input is first passed through a lookup table to obtain a low-precision reciprocal approximation. The table lookup result is then multiplied by the divisor and the dividend respectively to obtain a first quotient value with low precision. After one iteration of the Goldschmidt algorithm, it is converged twice to obtain a quotient with higher precision. However, the precision at this time can only meet the rounding requirements of single-precision floating-point numbers, and cannot meet the rounding requirements of double-precision floating-point numbers. Therefore, another iteration is required to further improve the precision and then send it to the final rounding module 400 to obtain a floating-point division operation result that meets the rounding requirements.

[0037] See also Figure 1 、 Figure 5 and Figure 7As shown, in the present invention, the iteration module 300 includes at least four multipliers, and the four multipliers perform at least two multiplication iterations on the initial approximate data, thereby improving the calculation accuracy of the initial approximate data. In another embodiment of the present invention, when the floating-point operation is a square root operation, the first multiplier 320 is electrically connected to the table lookup module 200 and operates within the first clock, the second multiplier 330 is electrically connected to the first multiplier 320 and operates within the second clock, and the third multiplier 340 and the fourth multiplier 350 are electrically connected to the second multiplier 330 and operate within the third clock. The time lengths of the first clock and the second clock are determined by the clock unit of the computer, wherein the first clock is located before the second clock, the second clock unit is located before the third clock unit, and the first clock, the second clock and the third clock are continuous. Figure 5 The present invention is a flow chart of a single-precision square root operation circuit of a floating-point unit. The radicand as an input is first checked for exponent parity by using a lookup table, and the reciprocal square root is obtained by looking up the table. The reciprocal square root is multiplied by the radicand to obtain a lower-precision root value. The Goldschmidt algorithm is then iterated once to achieve quadratic convergence to obtain a higher-precision root value. The higher-precision root value is then sent to the final rounding module 400 to obtain a floating-point square root operation result that meets the rounding requirements. Figure 7 The present invention is a schematic diagram of a double-precision square root operation circuit of a floating-point unit. The radicand as an input is first judged by the exponent parity and the use of a lookup table is used to obtain the reciprocal square root. The reciprocal square root is multiplied by the radicand to obtain a root value with lower precision. Then, through one iteration of the Goldschmidt algorithm, the quadratic convergence is achieved to obtain a root value with higher precision. However, the accuracy at this time can only meet the rounding requirements of single-precision floating-point numbers, and cannot meet the rounding requirements of double-precision floating-point numbers. Therefore, another iteration is required to further improve the accuracy and send it to the final rounding module 400 to obtain a floating-point square root operation result that meets the rounding requirements.

[0038] See also Figure 1 、 Figures 4 to 7As shown, in the present invention, the iteration module 300 includes at least one complementary precision multiplier 360, which is electrically connected to the third multiplier 340, the fourth multiplier 350, and the rounding module 400 through a control switch. In this embodiment, there are two complementary precision multipliers, which are recorded as a fifth multiplier 361 and a sixth multiplier 362. The input end of the fifth multiplier 361 is connected to the output ends of the third multiplier 340 and the fourth multiplier 350 through a control switch, and the input end of the fifth multiplier 361 is connected to the output ends of the third multiplier 340 and the fourth multiplier 350 through another control switch. The iteration module 300 includes a controller 370. When the accuracy of the data output by the iteration module 300 does not meet the accuracy requirements of the rounding module 400, the controller 370 controls at least one control switch to close and connects at least one supplementary precision multiplier 360 to the output terminals of the third multiplier 340 and the fourth multiplier 350 and to the input terminal of the rounding module 400. In the present invention, the operation of the iteration module 300 is based on the Goldschmidt algorithm.

[0039] In one embodiment of the present invention, in the square root operation, N is initialized. -1 =X,F -1 =RecSqrt. Initialization D0=M0×F -1 , When j takes the value from 1 to i, execute o j-1 =F j-1 -1, execute implement implement implement After the iteration, we get In the division operation, initialize N -1 =A, F -1 =Rec, D -1 =B, N0=N -1 ×F -1 , D0=D -1 ×F -1 , When j takes the value from 1 to i, execute o j-1 =F j-1 -1, implement implement After the iteration, we get

[0041] It should be noted that in the Goldschmidt iterative algorithm, and specifically in the division operation, the numerator and denominator are multiplied by the iteration coefficient at the same time. When the denominator approaches 1, the numerator approaches the quotient. Specifically in the square root operation, the principle is similar to the division, but the initial value of the numerator is the multiplication of the input square root and the approximate value of the reciprocal square root, and the initial value of the denominator is the multiplication of the input square root and the square of the approximate value of the reciprocal square root. In the iterative process, the numerator and denominator are also multiplied by the iteration coefficient at the same time. The denominator approaches 1 as the iteration progresses, and the numerator approaches the root value as the iteration progresses. In this embodiment, N i represents the molecular result after the i-th iteration, D i Represents the denominator result after the i-th iteration, M i Indicates the solution D i The intermediate result when F i Represents the iteration coefficient after iteration i. RecSqrt is the result of the square root lookup table, and Rec is the result of the division lookup table. The square root X is the unrounded square root, and Q is the unrounded quotient. Additionally, wavy lines or discounted superscripts in the numerator and denominator indicate truncated bit widths.

[0042] See also Figure 1 、 Figure 4 and Figure 5 As shown, in one embodiment of the present invention, rounding module 400 stores rounding rules for the first approximate data, including the IEEE 754 standard. Rounding module 400 includes a back-multiplication unit 410, which is electrically connected to the output of iteration module 300 and receives the first approximate data. Back-multiplication unit 410 outputs the product of the second approximate data and the divisor of the data to be processed as comparison data. The sign bit of the second approximate data is obtained based on the difference between the comparison data and the data to be processed. The initial approximate data is iterated using the Goldschmidt algorithm, achieving quadratic convergence to obtain the first approximate data. In one embodiment of the present invention, the first approximate data is a quotient with higher precision. The first approximate data is then sent to rounding module 400 to obtain a floating-point division result that meets the rounding requirements. In another embodiment of the present invention, the first approximate data is a root value with higher precision. The first approximate data is then sent to rounding module 400 to obtain a floating-point square root result that meets the rounding requirements.

[0043] In the iterative method provided by the present invention, in the square root operation, It can be expressed as formula (1) and (2).

[0044]

[0045] In one embodiment of the present invention, when obtaining Q tmp In the method, pj (i) can be expressed as formula (3), K j It can be expressed as formula (4), d jump It can be expressed as formula (5), m jtotal It can be expressed as formula (6), d jtotal It can be expressed as formula (7).

[0046]

[0047] In one embodiment of the present invention, when obtaining Q tmp In the method, q j (i) can be expressed as formula (8), n jtotal It can be expressed as formula (9).

[0048]

[0049] In equations (3) to (9), the lowercase letter n i is the denominator truncation error at the i-th iteration. The add and mul tables below are used to distinguish whether the error comes from addition or multiplication. i and m i are the truncation errors of Di and Mi respectively, and the meanings of add and mul are also used to distinguish the sources of errors. i Indicates F i The other variables are composed of the above variables and are used to construct the iterative expression. Equations (3) to (9) are the final root value expressions without rounding, considering the initial lookup table error and the iterative error of the intermediate result. This expression based on absolute error can not only reflect the convergence and accumulation of the error, but also reflect the impact of the introduction of truncation error on the final result.

[0050] In the iterative method provided by the present invention, in the division operation, Q tmp It can be expressed as formula (10) and (11). j (i) can be expressed as formula (12), K j It can be expressed as formula (13), d jtotal It can be expressed as formula (14), q j (i) can be expressed as formula (15), n jtotal It can be expressed as formula (16).

[0051] Q tmp =N i -n iadd (10).

[0052]

[0053] K j =Q(djadd -d j -i t0tal ) (13).

[0054]

[0055] n jtotal =n jadd +(ε' j -f j )n jmul (16).

[0056] The expression in the figure is the unrounded final quotient expression that takes into account the initial lookup table error and the iterative error of the intermediate result. This absolute error-based expression not only reflects the convergence and accumulation of errors, but also reflects the impact of the introduction of truncation error on the final result. The present invention can express the convergence error after the i-th iteration using Epsilon_i in the Goldschmidt algorithm.

[0057] In summary, the present invention provides a high-speed hybrid floating-point division and square root operation system, which truncates the bit width based on absolute error analysis, can reflect the convergence and accumulation of the iterative bit width truncation error, and imposes different degrees of error range restrictions on errors of different properties, so as to minimize the redundant bit width of the intermediate iterative process while ensuring that the final calculation result meets the IEEE-754 rounding standard, so as to improve the calculation speed and reduce unnecessary computing resources. In addition, based on the proposed algorithm, the present invention proposes a dedicated hardware architecture to effectively tap the advantages of the algorithm. The algorithm proposed in the present invention is not only applicable to floating-point division operations, but also to floating-point square root operations, and can reasonably adjust the intermediate process iterative bit width of the two operations through error analysis to achieve the greatest possible resource reuse. The algorithm provided by the present invention uses the first iteration result as the result of single-precision floating-point division and square root operations, which can meet the single-precision rounding requirements, and uses the second iteration result as the result of double-precision floating-point division and square root operations, which can meet the double-precision rounding requirements. The single-precision floating-point operation is integrated into the double-precision floating-point operation, further improving resource reuse and optimizing circuit area. The present invention proposes a pipeline-based floating-point operation computing architecture that can maximize computing throughput and achieve higher computing efficiency.

[0058] The embodiments of the present invention disclosed above are intended only to help illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A high-speed hybrid floating-point division and square root operation system, characterized in that: include: A table lookup module, which receives and processes the data to be processed, and outputs initial approximate data of the data to be processed after floating-point operation; an iteration module, connected to the table lookup module and receiving the initial approximate data, the iteration module performing at least two multiplication processes on the initial approximate data and obtaining first approximate data; and The rounding module is connected to the iteration module and receives the first approximate data. According to whether the floating point operation is a single-precision floating point operation or a double-precision floating point operation, the rounding module adjusts the number of bits of the first approximate data to obtain and output second approximate data.

2. A high-speed hybrid floating-point division and square root operation system according to claim 1, characterized in that: The floating-point operation is a division operation or a square root operation, and the data to be processed is a dividend or a square root. When the data to be processed is the dividend, the initial approximate data is an approximate quotient value of the dividend after the division operation, and when the data to be processed is the square root, the initial approximate data is an approximate square root of the square root after the square root operation.

3. A high-speed hybrid floating-point division and square root operation system according to claim 1, characterized in that: The table lookup module includes a dual-body structure lookup table, and the dual-body structure lookup table includes a first lookup table and a second lookup table, wherein the first lookup table and the second lookup table are respectively built based on partial bit data of the data to be processed, and a fitting result after subtracting the first lookup table from the second lookup table is used as the reciprocal approximation or reciprocal square root of the data to be processed, and the product of the reciprocal approximation and the data to be processed or the product of the reciprocal square root and the data to be processed is used as the initial approximation.

4. A high-speed hybrid floating-point division and square root operation system according to claim 3, characterized in that: The table building data of the first lookup table includes the high-order data and the median data of the data to be processed, and the table building data of the second lookup table includes the high-order data and the low-order data of the data to be processed, wherein the high-order data is the portion of the bits on the left side of the bit width order of the data to be processed, the low-order data is the portion of the bits on the right side of the bit width order of the data to be processed, and the median data is the portion of the bits in the data to be processed that are between the high-order data and the low-order data, wherein the number of bits of the high-order data, the median data and the low-order data are the same.

5. A high-speed hybrid floating-point division and square root operation system according to claim 1, characterized in that: The iteration module includes at least four multipliers, and the four multipliers perform at least two multiplication iterations on the initial approximate data, wherein when the floating-point operation is a division operation, the first multiplier and the second multiplier are electrically connected to the table lookup module and run in parallel within a first clock, and the third multiplier and the fourth multiplier are electrically connected to the first multiplier and the second multiplier and run within a second clock.

6. A high-speed hybrid floating-point division and square root operation system according to claim 1, characterized in that: The iteration module includes at least four multipliers, and the four multipliers perform at least two multiplication iterations on the initial approximate data. When the floating-point operation is a square root operation, the first multiplier is electrically connected to the table lookup module and runs within a first clock, the second multiplier is electrically connected to the first multiplier and runs within a second clock, and the third multiplier and the fourth multiplier are electrically connected to the second multiplier and run within a third clock.

7. A high-speed hybrid floating-point division and square root operation system according to claim 5 or 6, characterized in that: The iteration module includes at least one complementary precision multiplier, and the complementary precision multiplier is electrically connected to the third multiplier, the fourth multiplier and the rounding module through a control switch.

8. A high-speed hybrid floating-point division and square root operation system according to claim 7, characterized in that: The operation system includes a controller. When the data accuracy output by the iteration module does not meet the accuracy requirement of the rounding module, the controller controls the control switch to close and connects at least one of the supplementary precision multipliers to the output ends of the third multiplier and the fourth multiplier and the access end of the rounding module.

9. A high-speed hybrid floating-point division and square root operation system according to claim 6, characterized in that: The rounding module stores rounding rules for the first approximate data, and the rounding rules include IEEE754 standards.

10. A high-speed hybrid floating-point division and square root operation system according to claim 1, characterized in that: The rounding module includes a back-multiplication unit, which is electrically connected to the output end of the iteration module and receives the first approximate data. The back-multiplication unit outputs the product of the second approximate data and the divisor of the data to be processed as comparison data, and obtains the sign bit of the second approximate data according to the difference between the comparison data and the data to be processed.

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