A method and system for powering on CPLD configuration information based on dynamic voltage regulation

Abstract

The present invention provides a method and system for powering on CPLD configuration information based on dynamic voltage regulation in the field of CPLD management technology. The method comprises: step S1, a CPU generates an offset sub-address of each byte data in the configuration information based on an offset address; step S2, sending a protection mark, a first byte data, and a corresponding offset sub-address to an I2C slave controller to respectively write into a protection register, a data register, and an address register; step S3, after a logic controller verifies the protection mark written into the protection register, the I2C master controller controls the I2C master controller to read the byte data and the offset sub-address from the corresponding register to write the byte data into an EEPROM based on the offset sub-address, and executes the writing of the next byte data until all writing is completed; step S4, when the CPLD is powered on, the I2C master controller automatically loads the byte data stored in the EEPROM into the configuration register. The advantages of the present invention are: greatly improving the convenience, flexibility, safety, and reliability of CPLD configuration information loading.

Description

Technical Field

[0001] The invention relates to the technical field of CPLD management, and in particular to a method and system for powering on and loading CPLD configuration information based on dynamic voltage regulation. Background Art

[0002] CPLD (Complex Programmable Logic Device) is a programmable logic device that allows users to construct logic functions according to their needs. CPLD consists of multiple programmable logic units (PLDs), which are connected through programmable global interconnection resources. The operation of CPLD depends on configuration information, that is, the configuration information needs to be loaded correctly for the CPLD to operate normally. Traditionally, there are the following methods for loading CPLD configuration information:

[0003] Method 1 is to solidify the configuration information in the firmware burned into the CPLD so that the configuration information is automatically loaded when the CPLD is powered on. However, this method cannot flexibly modify the configuration information. To modify the configuration information, the firmware must be re-burned, resulting in many risks in the management and control of the firmware version, and the firmware version is easily fragmented.

[0004] The second method is to load the configuration information through the high and low levels of the IO pins. This method also cannot flexibly modify the configuration information. To modify the configuration information, the jumper resistance on the circuit board must be adjusted. In scenarios where the configuration information is large, a large number of IO pins are required, and the chassis needs to be opened to modify the configuration information.

[0005] In summary, the traditional method of loading CPLD configuration information is not convenient and flexible. In addition, no corresponding safety measures are taken for reading and writing configuration information, which poses certain safety risks. In the process of loading configuration information, the traditional method often fails to load due to fluctuations in electrical variables, such as unstable voltage. Therefore, how to provide a CPLD configuration information power-on loading method and system based on dynamic voltage regulation to improve the convenience, flexibility, safety and reliability of CPLD configuration information loading has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a method and system for powering on CPLD configuration information based on dynamic voltage regulation, so as to improve the convenience, flexibility, safety and reliability of CPLD configuration information loading.

[0007] In a first aspect, the present invention provides a method for powering on and loading CPLD configuration information based on dynamic voltage regulation, comprising the following steps:

[0008] Step S1, the CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte data in the configuration information based on the offset address;

[0009] Step S2, the CPU encrypts each of the byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively;

[0010] Step S3, the CPU sends a preset protection identifier, the first encrypted byte data, and an encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus;

[0011] Step S4, the I2C slave controller writes the received protection identifier, encrypted byte data and encrypted offset sub-address into the protection register, data register and address register respectively;

[0012] Step S5, after the logic controller of the CPLD verifies the protection identifier written into the protection register, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively;

[0013] Step S6, the I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain corresponding byte data and the offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address;

[0014] Step S7, the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until the writing of all the byte data is completed and the protection register is cleared;

[0015] Step S8, when the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time by the voltage sensor, the power supply voltage is dynamically adjusted by the voltage regulator to make the power supply voltage within a preset voltage range, the logic controller automatically sends a continuous read command to the I2C master controller, and the I2C master controller loads each byte of data stored in the EEPROM into the configuration register based on the received continuous read command to complete the automatic loading of the configuration information at power-on.

[0016] Furthermore, the step S2 is specifically as follows:

[0017] The CPU converts each of the byte data into first binary data, divides each of the first binary data in a ratio of 2:6 and swaps the order of the first and second binary data to obtain first intermediate data, and cyclically shifts each character of each of the first intermediate data to the right by 3 bits to obtain encrypted byte data;

[0018] The CPU converts each of the offset sub-addresses into second binary data, divides each of the second binary data in a ratio of 3:5 and swaps the order to obtain second intermediate data, and circularly shifts each character of each of the second intermediate data to the left by 2 bits to obtain an encrypted offset sub-address.

[0019] Furthermore, the step S4 is specifically as follows:

[0020] Based on the write instruction sent by the CPU, the I2C slave controller writes the received encrypted byte data and the encrypted offset sub-address into the data register and the address register in real time, writes the characters carried by the received protection identifier into the protection register in a preset standard write order, and records the actual write order;

[0021] The step S5 is specifically as follows:

[0022] The logic controller of the CPLD detects the setting status of the protection register in real time. When the protection register is set, a primary check is performed on the actual writing order based on the preset standard writing order, and then a secondary check is performed on the protection identifier written into the protection register through the protection identifier pre-stored locally, and then the I2C main controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

[0023] Furthermore, the step S6 is specifically as follows:

[0024] The I2C master controller circularly shifts each character of the encrypted byte data to the left by 3 bits to obtain first intermediate data, divides the first intermediate data at a ratio of 6:2 and swaps the order to obtain first binary data, converts the first binary data into plain text to obtain byte data, and completes the decryption of the encrypted byte data; circularly shifts each character of the encrypted offset sub-address to the right by 2 bits to obtain second intermediate data, divides the second intermediate data at a ratio of 5:3 and swaps the order to obtain second binary data, converts the second binary data into plain text to obtain an offset sub-address, and completes the decryption of the encrypted offset sub-address;

[0025] The I2C master controller writes one byte of byte data into the EEPROM in real time based on the offset sub-address.

[0026] Furthermore, the step S7 is specifically as follows:

[0027] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data are written, and sends a write completion notification to the logic controller through the I2C slave controller;

[0028] The logic controller clears the protection register based on the received write-end notification, reads the configuration information written by the EEPROM through the I2C main controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU;

[0029] The CPU performs integrity check on the configuration information writing based on the received CRC8 check value to obtain a check result, generates a write log based on the check result, write time, configuration information, offset address, and CPLD serial number, and stores and backs up the write log.

[0030] In a second aspect, the present invention provides a CPLD configuration information power-on loading system based on dynamic voltage regulation, comprising the following modules:

[0031] A configuration information preprocessing module is used for the CPU to obtain the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and to generate the offset sub-address of each byte data in the configuration information based on the offset address;

[0032] An encryption module, used for the CPU to encrypt each of the byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively;

[0033] The data sending module is used for the CPU to send a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus;

[0034] A data storage module, used for the I2C slave controller to write the received protection identifier, encrypted byte data and encrypted offset sub-address into a protection register, a data register and an address register respectively;

[0035] A protection identification verification module, which is used for the logic controller of the CPLD to verify the protection identification written into the protection register, and then control the I2C main controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively;

[0036] A first byte data writing module is used for the I2C master controller to decrypt the encrypted byte data and the encrypted offset sub-address, obtain the corresponding byte data and the offset sub-address, and write the byte data into the EEPROM based on the offset sub-address;

[0037] A second byte data writing module is used for the logic controller to forward the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte data until the writing of all the byte data is completed and the protection register is cleared;

[0038] The configuration information power-on loading module is used to monitor the power supply voltage in real time through the voltage sensor when the CPLD is powered on or the control register is set, and dynamically adjust the power supply voltage through the voltage regulator to make the power supply voltage within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C main controller, and the I2C main controller loads each byte of data stored in the EEPROM into the configuration register based on the received continuous read command to complete the automatic power-on loading of the configuration information.

[0039] Furthermore, the encryption module is specifically used for:

[0040] The CPU converts each of the byte data into first binary data, divides each of the first binary data in a ratio of 2:6 and swaps the order of the first and second binary data to obtain first intermediate data, and cyclically shifts each character of each of the first intermediate data to the right by 3 bits to obtain encrypted byte data;

[0041] The CPU converts each of the offset sub-addresses into second binary data, divides each of the second binary data in a ratio of 3:5 and swaps the order to obtain second intermediate data, and circularly shifts each character of each of the second intermediate data to the left by 2 bits to obtain an encrypted offset sub-address.

[0042] Furthermore, the data storage module is specifically used for:

[0043] Based on the write instruction sent by the CPU, the I2C slave controller writes the received encrypted byte data and the encrypted offset sub-address into the data register and the address register in real time, writes the characters carried by the received protection identifier into the protection register in a preset standard write order, and records the actual write order;

[0044] The protection identification verification module is specifically used for:

[0045] The logic controller of the CPLD detects the setting status of the protection register in real time. When the protection register is set, a primary check is performed on the actual writing order based on the preset standard writing order, and then a secondary check is performed on the protection identifier written into the protection register through the protection identifier pre-stored locally, and then the I2C main controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

[0046] Furthermore, the first byte data writing module is specifically used for:

[0047] The I2C master controller circularly shifts each character of the encrypted byte data to the left by 3 bits to obtain first intermediate data, divides the first intermediate data at a ratio of 6:2 and swaps the order to obtain first binary data, converts the first binary data into plain text to obtain byte data, and completes the decryption of the encrypted byte data; circularly shifts each character of the encrypted offset sub-address to the right by 2 bits to obtain second intermediate data, divides the second intermediate data at a ratio of 5:3 and swaps the order to obtain second binary data, converts the second binary data into plain text to obtain an offset sub-address, and completes the decryption of the encrypted offset sub-address;

[0048] The I2C master controller writes one byte of byte data into the EEPROM in real time based on the offset sub-address.

[0049] Further, the second byte data writing module is specifically used for:

[0050] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data are written, and sends a write completion notification to the logic controller through the I2C slave controller;

[0051] The logic controller clears the protection register based on the received write-end notification, reads the configuration information written by the EEPROM through the I2C main controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU;

[0052] The CPU performs integrity check on the configuration information writing based on the received CRC8 check value to obtain a check result, generates a write log based on the check result, write time, configuration information, offset address, and CPLD serial number, and stores and backs up the write log.

[0053] The advantages of the present invention are:

[0054] 1. The CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte data in the configuration information based on the offset address; then the CPU encrypts each byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively, and sends a preset protection identifier, the first encrypted byte data, and the corresponding encrypted offset sub-address to the I2C slave controller of the CPLD; then the I2C slave controller writes the protection identifier, the encrypted byte data, and the encrypted offset sub-address into the protection register, the data register, and the address register respectively; after the logic controller of the CPLD verifies the protection identifier written into the protection register, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively, and the I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address; then the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the next The byte data is written until all the byte data is written and the protection register is cleared; when the CPLD is powered on or the control register is set, the logic controller automatically sends a continuous read command to the I2C master controller, and the I2C master controller loads each byte data stored in the EEPROM into the configuration register based on the continuous read command to complete the power-on automatic loading of the configuration information; that is, the CPLD is connected to the CPU and the EEPROM respectively through the I2C bus, and the CPU interacts with the CPLD through the register group set by the CPLD to write the configuration information into the EEPROM, and the configuration information stored in the EEPROM is automatically loaded into the configuration register when the CPLD is powered on or the control register is set. Compared with the traditional method, there is no need to control a large number of firmware versions, nor to occupy a large number of IO pins. The configuration information can be written and updated only through the register group, and in the process of writing the configuration information, the encryption of the byte data and the offset sub-address, the verification of the protection identifier, and the security measures of the integrity verification are combined, which ultimately greatly improves the convenience, flexibility and security of the CPLD configuration information loading.

[0055] 2. Convert each byte data into first binary data through the CPU, divide each first binary data in a ratio of 2:6 and swap the order to obtain first intermediate data, and shift each character of each first intermediate data rightward by 3 bits to obtain encrypted byte data; convert each offset sub-address into second binary data, divide each second binary data in a ratio of 3:5 and swap the order to obtain second intermediate data, and shift each character of each second intermediate data leftward by 2 bits to obtain encrypted offset sub-address; that is, encrypt the byte data and offset sub-address through the preset data transformation rule, if the corresponding data transformation rule is not known, the encrypted byte data and encrypted offset sub-address cannot be cracked, and the byte data and offset sub-address adopt different data transformation rules to further increase the difficulty of cracking, and at least 6 security measures (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance) are adopted before and after, which greatly improves the security of transmission and storage of byte data and offset sub-address, and thus greatly improves the security of CPLD configuration information loading.

[0056] 3. By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, the actual writing order is verified based on the standard writing order, and then the protection identifier written into the protection register is verified by the protection identifier stored locally in advance. Only when both verifications pass, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively; that is, before reading the encrypted byte data and the encrypted offset sub-address, not only the protection register needs to store the correct protection identifier, but the protection identifier needs to be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order, otherwise the verification fails. Two security measures are taken before and after (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being illegally read, thereby further improving the security of CPLD configuration information loading.

[0057] 4. After writing byte data through the I2C master controller, write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the file number until all byte data are written, and sends a write end notification to the logic controller through the I2C slave controller; the logic controller clears the protection register based on the write end notification, reads the configuration information written by the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity check on the configuration information written based on the CRC8 check value; that is, during the configuration information writing process, the CPU and CPLD interact with each other in real time through write completion feedback and write end notification to monitor the writing progress. When all writing is completed, the protection register is cleared in time to avoid illegal writing. The CRC8 check value is used to check whether the configuration information written to the EEPROM is complete, thereby greatly improving the reliability of CPLD configuration information writing.

[0058] 5. Generate a write log including verification results, write time, configuration information, offset address, and CPLD serial number, and store and back up the write log to facilitate later tracing.

[0059] 6. The security of CPLD configuration information loading is greatly improved through encryption of byte data and offset sub-address (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance), verification of protection identifier (value of protection identifier, writing order of protection identifier), integrity verification (CRC8 check value of configuration information), timely clearing of protection registers, and isolation of CPU and EEPROM through CPLD.

[0060] 7. When the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time through the voltage sensor, and the power supply voltage is dynamically adjusted through the voltage regulator to be within the preset voltage range, thereby avoiding the failure of configuration information loading caused by unstable power supply voltage, thereby greatly improving the reliability of CPLD configuration information loading. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0062] Figure 1 The invention discloses a flow chart of a method for powering on and loading CPLD configuration information based on dynamic voltage regulation.

[0063] Figure 2 The invention discloses a structural schematic diagram of a CPLD configuration information power-on loading system based on dynamic voltage regulation.

[0064] Figure 3It is a hardware architecture diagram of the present invention. DETAILED DESCRIPTION

[0065] The technical solution in the embodiment of the present application has the following general idea: the CPLD is connected to the CPU and the EEPROM respectively through the I2C bus, and the CPU interacts with the CPLD through the register group (control register, protection register, data register, address register, configuration register) set by the CPLD to write the configuration information into the EEPROM, and the configuration information stored in the EEPROM is automatically loaded into the configuration register when the CPLD is powered on or the control register is set, and the power supply voltage is dynamically adjusted to be within a preset voltage range. Compared with the traditional method, there is no need to control a large number of firmware versions, nor to occupy a large number of IO pins. The configuration information can be written and updated only through the register group. In the process of writing the configuration information, the encryption of byte data and offset sub-address, the verification of protection identifiers, and the security measures of integrity verification are combined, and the failure of configuration information loading caused by the instability of the power supply voltage is avoided, so as to improve the convenience, flexibility, security and reliability of CPLD configuration information loading.

[0066] Please refer to Figures 1 to 3 As shown, a preferred embodiment of a method for powering on and loading CPLD configuration information based on dynamic voltage regulation of the present invention comprises the following steps:

[0067] Step S1, the CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte data in the configuration information based on the offset address;

[0068] Step S2, the CPU encrypts each of the byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively;

[0069] Step S3, the CPU sends a preset protection identifier, the first encrypted byte data, and an encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus;

[0070] Step S4, the I2C slave controller writes the received protection identifier, encrypted byte data and encrypted offset sub-address into the protection register, data register and address register respectively;

[0071] Step S5, after the logic controller of the CPLD verifies the protection identifier written into the protection register, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively;

[0072] Step S6, the I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain corresponding byte data and the offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address;

[0073] Step S7, the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until the writing of all the byte data is completed and the protection register is cleared;

[0074] Step S8, when the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time by the voltage sensor, the power supply voltage is dynamically adjusted by the voltage regulator to make the power supply voltage within a preset voltage range, the logic controller automatically sends a continuous read command to the I2C master controller, and the I2C master controller loads each byte of data stored in the EEPROM into the configuration register based on the received continuous read command to complete the automatic loading of the configuration information at power-on.

[0075] The CPLD is provided with a logic controller, an I2C slave controller, an I2C master controller and a register group; the register group is provided with a control register, a protection register, a data register, an address register and a configuration register; the logic controller is connected to the I2C slave controller, the I2C master controller and the register group respectively; one end of the I2C slave controller is connected to the CPU through the I2C bus, and the other end is connected to the register group; one end of the I2C master controller is connected to the EEPROM through the I2C bus, and the other end is connected to the register group;

[0076] The logic controller is used to control the work of the CPLD, and automatically sends a continuous read command to the I2C master controller based on a preset script when the CPLD is powered on or the control register is set; the I2C slave controller is used to communicate with the CPU, adopts a communication format standard similar to the EEPROM 24C02A, and supports 256-byte random read, byte write and other operations; the I2C master controller is used to write single-byte data to the EEPROM and read multi-byte data (configuration information) from the EEPROM; the control register is used to trigger the loading of configuration information; the protection register is used to start the writing of configuration information; the data register is used to store encrypted byte data; the address register is used to store the encrypted offset sub-address; the configuration register is used to store the configuration information loaded by the CPLD from the EEPROM; the register group occupies 256 bytes of space.

[0077] The step S2 is specifically as follows:

[0078] The CPU converts each of the byte data into first binary data, divides each of the first binary data in a ratio of 2:6 and swaps the order of the first and second binary data to obtain first intermediate data, and cyclically shifts each character of each of the first intermediate data to the right by 3 bits to obtain encrypted byte data;

[0079] The CPU converts each of the offset sub-addresses into second binary data, divides each of the second binary data in a ratio of 3:5 and swaps the order to obtain second intermediate data, and circularly shifts each character of each of the second intermediate data to the left by 2 bits to obtain an encrypted offset sub-address.

[0080] Each byte data is converted into first binary data by a CPU, each first binary data is divided at a ratio of 2:6 and the front-to-back order is exchanged to obtain first intermediate data, each character of each first intermediate data is circularly shifted to the right by 3 bits to obtain encrypted byte data; each offset sub-address is converted into second binary data, each second binary data is divided at a ratio of 3:5 and the front-to-back order is exchanged to obtain second intermediate data, each character of each second intermediate data is circularly shifted to the left by 2 bits to obtain encrypted offset sub-address; that is, the byte data and the offset sub-address are encrypted by a preset data transformation rule, if the corresponding data transformation rule is not known, the encrypted byte data and the encrypted offset sub-address cannot be cracked, and the byte data and the offset sub-address adopt different data transformation rules to further increase the difficulty of cracking, and at least 6 security measures (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance) are adopted before and after, which greatly improves the security of transmission and storage of byte data and offset sub-address, and thus greatly improves the security of CPLD configuration information loading.

[0081] The step S4 is specifically as follows:

[0082] Based on the write instruction sent by the CPU, the I2C slave controller writes the received encrypted byte data and the encrypted offset sub-address into the data register and the address register in real time, writes the characters carried by the received protection identifier into the protection register in a preset standard write order, and records the actual write order;

[0083] The step S5 is specifically as follows:

[0084] The logic controller of the CPLD detects the setting status of the protection register in real time. When the protection register is set, a primary check is performed on the actual writing order based on the preset standard writing order, and then a secondary check is performed on the protection identifier written into the protection register through the protection identifier pre-stored locally, and then the I2C main controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

[0085] By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, the actual writing order is verified based on the standard writing order, and then the protection identifier written into the protection register is verified by the protection identifier stored locally in advance. Only when both verifications pass, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively; that is, before reading the encrypted byte data and the encrypted offset sub-address, not only the protection register needs to store the correct protection identifier, but the protection identifier needs to be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order, otherwise the verification fails. Two security measures are taken before and after (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being illegally read, thereby further improving the security of CPLD configuration information loading.

[0086] The step S6 is specifically as follows:

[0087] The I2C master controller circularly shifts each character of the encrypted byte data to the left by 3 bits to obtain first intermediate data, divides the first intermediate data at a ratio of 6:2 and swaps the order to obtain first binary data, converts the first binary data into plain text to obtain byte data, and completes the decryption of the encrypted byte data; circularly shifts each character of the encrypted offset sub-address to the right by 2 bits to obtain second intermediate data, divides the second intermediate data at a ratio of 5:3 and swaps the order to obtain second binary data, converts the second binary data into plain text to obtain an offset sub-address, and completes the decryption of the encrypted offset sub-address;

[0088] The I2C master controller writes one byte of byte data into the EEPROM in real time based on the offset sub-address.

[0089] The step S7 is specifically as follows:

[0090] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data are written, and sends a write completion notification to the logic controller through the I2C slave controller;

[0091] The logic controller clears the protection register based on the received write end notification, prohibits the write operation, reads the configuration information written by the EEPROM through the I2C main controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU;

[0092] After writing byte data through the I2C master controller, write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the file number until all the byte data are written, and sends a write end notification to the logic controller through the I2C slave controller; the logic controller clears the protection register based on the write end notification, reads the configuration information written by the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity verification of the configuration information written based on the CRC8 check value; that is, during the configuration information writing process, the CPU and CPLD interact with each other in real time through write completion feedback and write end notification to monitor the writing progress, clear the protection register in time when all writing is completed to avoid illegal writing, and verify whether the configuration information written to the EEPROM is complete through the CRC8 check value, thereby greatly improving the reliability of CPLD configuration information writing.

[0093] The CPU performs integrity check on the configuration information writing based on the received CRC8 check value to obtain a check result, generates a write log based on the check result, write time, configuration information, offset address, and CPLD serial number, and stores and backs up the write log.

[0094] By generating a write log including verification results, write time, configuration information, offset address, and CPLD serial number, and storing and backing up the write log, it is easy to trace the source later.

[0095] The security of CPLD configuration information loading is greatly improved through encryption of byte data and offset sub-addresses (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance), verification of protection identifiers (values ​​of protection identifiers, writing order of protection identifiers), integrity verification (CRC8 verification value of configuration information), timely clearing of protection registers, and isolation of CPU and EEPROM through CPLD.

[0096] A preferred embodiment of a CPLD configuration information power-on loading system based on dynamic voltage regulation of the present invention includes the following modules:

[0097] A configuration information preprocessing module is used for the CPU to obtain the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and to generate the offset sub-address of each byte data in the configuration information based on the offset address;

[0098] An encryption module, used for the CPU to encrypt each of the byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively;

[0099] The data sending module is used for the CPU to send a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus;

[0100] A data storage module, used for the I2C slave controller to write the received protection identifier, encrypted byte data and encrypted offset sub-address into a protection register, a data register and an address register respectively;

[0101] A protection identification verification module, which is used for the logic controller of the CPLD to verify the protection identification written into the protection register, and then control the I2C main controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively;

[0102] A first byte data writing module is used for the I2C master controller to decrypt the encrypted byte data and the encrypted offset sub-address, obtain the corresponding byte data and the offset sub-address, and write the byte data into the EEPROM based on the offset sub-address;

[0103] A second byte data writing module is used for the logic controller to forward the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte data until the writing of all the byte data is completed and the protection register is cleared;

[0104] The configuration information power-on loading module is used to monitor the power supply voltage in real time through the voltage sensor when the CPLD is powered on or the control register is set, and dynamically adjust the power supply voltage through the voltage regulator to make the power supply voltage within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C main controller, and the I2C main controller loads each byte of data stored in the EEPROM into the configuration register based on the received continuous read command to complete the automatic power-on loading of the configuration information.

[0105] The CPLD is provided with a logic controller, an I2C slave controller, an I2C master controller and a register group; the register group is provided with a control register, a protection register, a data register, an address register and a configuration register; the logic controller is connected to the I2C slave controller, the I2C master controller and the register group respectively; one end of the I2C slave controller is connected to the CPU through the I2C bus, and the other end is connected to the register group; one end of the I2C master controller is connected to the EEPROM through the I2C bus, and the other end is connected to the register group;

[0106] The logic controller is used to control the work of the CPLD, and automatically sends a continuous read command to the I2C master controller based on a preset script when the CPLD is powered on or the control register is set; the I2C slave controller is used to communicate with the CPU, adopts a communication format standard similar to the EEPROM 24C02A, and supports 256-byte random read, byte write and other operations; the I2C master controller is used to write single-byte data to the EEPROM and read multi-byte data (configuration information) from the EEPROM; the control register is used to trigger the loading of configuration information; the protection register is used to start the writing of configuration information; the data register is used to store encrypted byte data; the address register is used to store the encrypted offset sub-address; the configuration register is used to store the configuration information loaded by the CPLD from the EEPROM; the register group occupies 256 bytes of space.

[0107] The encryption module is specifically used for:

[0108] The CPU converts each of the byte data into first binary data, divides each of the first binary data in a ratio of 2:6 and swaps the order of the first and second binary data to obtain first intermediate data, and cyclically shifts each character of each of the first intermediate data to the right by 3 bits to obtain encrypted byte data;

[0109] The CPU converts each of the offset sub-addresses into second binary data, divides each of the second binary data in a ratio of 3:5 and swaps the order to obtain second intermediate data, and circularly shifts each character of each of the second intermediate data to the left by 2 bits to obtain an encrypted offset sub-address.

[0110] Each byte data is converted into first binary data by a CPU, each first binary data is divided at a ratio of 2:6 and the front-to-back order is exchanged to obtain first intermediate data, each character of each first intermediate data is circularly shifted to the right by 3 bits to obtain encrypted byte data; each offset sub-address is converted into second binary data, each second binary data is divided at a ratio of 3:5 and the front-to-back order is exchanged to obtain second intermediate data, each character of each second intermediate data is circularly shifted to the left by 2 bits to obtain encrypted offset sub-address; that is, the byte data and the offset sub-address are encrypted by a preset data transformation rule, if the corresponding data transformation rule is not known, the encrypted byte data and the encrypted offset sub-address cannot be cracked, and the byte data and the offset sub-address adopt different data transformation rules to further increase the difficulty of cracking, and at least 6 security measures (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance) are adopted before and after, which greatly improves the security of transmission and storage of byte data and offset sub-address, and thus greatly improves the security of CPLD configuration information loading.

[0111] The data storage module is specifically used for:

[0112] Based on the write instruction sent by the CPU, the I2C slave controller writes the received encrypted byte data and the encrypted offset sub-address into the data register and the address register in real time, writes the characters carried by the received protection identifier into the protection register in a preset standard write order, and records the actual write order;

[0113] The protection identification verification module is specifically used for:

[0114] The logic controller of the CPLD detects the setting status of the protection register in real time. When the protection register is set, a primary check is performed on the actual writing order based on the preset standard writing order, and then a secondary check is performed on the protection identifier written into the protection register through the protection identifier pre-stored locally, and then the I2C main controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

[0115] By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, the actual writing order is verified based on the standard writing order, and then the protection identifier written into the protection register is verified by the protection identifier stored locally in advance. Only when both verifications pass, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively; that is, before reading the encrypted byte data and the encrypted offset sub-address, not only the protection register needs to store the correct protection identifier, but the protection identifier needs to be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order, otherwise the verification fails. Two security measures are taken before and after (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being illegally read, thereby further improving the security of CPLD configuration information loading.

[0116] The first byte data writing module is specifically used for:

[0117] The I2C master controller circularly shifts each character of the encrypted byte data to the left by 3 bits to obtain first intermediate data, divides the first intermediate data at a ratio of 6:2 and swaps the order to obtain first binary data, converts the first binary data into plain text to obtain byte data, and completes the decryption of the encrypted byte data; circularly shifts each character of the encrypted offset sub-address to the right by 2 bits to obtain second intermediate data, divides the second intermediate data at a ratio of 5:3 and swaps the order to obtain second binary data, converts the second binary data into plain text to obtain an offset sub-address, and completes the decryption of the encrypted offset sub-address;

[0118] The I2C master controller writes one byte of byte data into the EEPROM in real time based on the offset sub-address.

[0119] The second byte data writing module is specifically used for:

[0120] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data are written, and sends a write completion notification to the logic controller through the I2C slave controller;

[0121] The logic controller clears the protection register based on the received write end notification, prohibits the write operation, reads the configuration information written by the EEPROM through the I2C main controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU;

[0122] After writing byte data through the I2C master controller, write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the file number until all the byte data are written, and sends a write end notification to the logic controller through the I2C slave controller; the logic controller clears the protection register based on the write end notification, reads the configuration information written by the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity verification of the configuration information written based on the CRC8 check value; that is, during the configuration information writing process, the CPU and CPLD interact with each other in real time through write completion feedback and write end notification to monitor the writing progress, clear the protection register in time when all writing is completed to avoid illegal writing, and verify whether the configuration information written to the EEPROM is complete through the CRC8 check value, thereby greatly improving the reliability of CPLD configuration information writing.

[0123] The CPU performs integrity check on the configuration information writing based on the received CRC8 check value to obtain a check result, generates a write log based on the check result, write time, configuration information, offset address, and CPLD serial number, and stores and backs up the write log.

[0124] By generating a write log including verification results, write time, configuration information, offset address, and CPLD serial number, and storing and backing up the write log, it is easy to trace the source later.

[0125] The security of CPLD configuration information loading is greatly improved through encryption of byte data and offset sub-addresses (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance), verification of protection identifiers (values ​​of protection identifiers, writing order of protection identifiers), integrity verification (CRC8 verification value of configuration information), timely clearing of protection registers, and isolation of CPU and EEPROM through CPLD.

[0126] In summary, the advantages of the present invention are:

[0127] 1. The CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte data in the configuration information based on the offset address; then the CPU encrypts each byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively, and sends a preset protection identifier, the first encrypted byte data, and the corresponding encrypted offset sub-address to the I2C slave controller of the CPLD; then the I2C slave controller writes the protection identifier, the encrypted byte data, and the encrypted offset sub-address into the protection register, the data register, and the address register respectively; after the logic controller of the CPLD verifies the protection identifier written into the protection register, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively, and the I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address; then the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the next The byte data is written until all the byte data is written and the protection register is cleared; when the CPLD is powered on or the control register is set, the logic controller automatically sends a continuous read command to the I2C master controller, and the I2C master controller loads each byte data stored in the EEPROM into the configuration register based on the continuous read command to complete the power-on automatic loading of the configuration information; that is, the CPLD is connected to the CPU and the EEPROM respectively through the I2C bus, and the CPU interacts with the CPLD through the register group set by the CPLD to write the configuration information into the EEPROM, and the configuration information stored in the EEPROM is automatically loaded into the configuration register when the CPLD is powered on or the control register is set. Compared with the traditional method, there is no need to control a large number of firmware versions, nor to occupy a large number of IO pins. The configuration information can be written and updated only through the register group, and in the process of writing the configuration information, the encryption of the byte data and the offset sub-address, the verification of the protection identifier, and the security measures of the integrity verification are combined, which ultimately greatly improves the convenience, flexibility and security of the CPLD configuration information loading.

[0128] 2. Convert each byte data into first binary data through the CPU, divide each first binary data in a ratio of 2:6 and swap the order to obtain first intermediate data, and shift each character of each first intermediate data rightward by 3 bits to obtain encrypted byte data; convert each offset sub-address into second binary data, divide each second binary data in a ratio of 3:5 and swap the order to obtain second intermediate data, and shift each character of each second intermediate data leftward by 2 bits to obtain encrypted offset sub-address; that is, encrypt the byte data and offset sub-address through the preset data transformation rule, if the corresponding data transformation rule is not known, the encrypted byte data and encrypted offset sub-address cannot be cracked, and the byte data and offset sub-address adopt different data transformation rules to further increase the difficulty of cracking, and at least 6 security measures (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance) are adopted before and after, which greatly improves the security of transmission and storage of byte data and offset sub-address, and thus greatly improves the security of CPLD configuration information loading.

[0129] 3. By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, the actual writing order is verified based on the standard writing order, and then the protection identifier written into the protection register is verified by the protection identifier stored locally in advance. Only when both verifications pass, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively; that is, before reading the encrypted byte data and the encrypted offset sub-address, not only the protection register needs to store the correct protection identifier, but the protection identifier needs to be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order, otherwise the verification fails. Two security measures are taken before and after (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being illegally read, thereby further improving the security of CPLD configuration information loading.

[0130] 4. After writing byte data through the I2C master controller, write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the file number until all byte data are written, and sends a write end notification to the logic controller through the I2C slave controller; the logic controller clears the protection register based on the write end notification, reads the configuration information written by the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity check on the configuration information written based on the CRC8 check value; that is, during the configuration information writing process, the CPU and CPLD interact with each other in real time through write completion feedback and write end notification to monitor the writing progress. When all writing is completed, the protection register is cleared in time to avoid illegal writing. The CRC8 check value is used to check whether the configuration information written to the EEPROM is complete, thereby greatly improving the reliability of CPLD configuration information writing.

[0131] 5. Generate a write log including verification results, write time, configuration information, offset address, and CPLD serial number, and store and back up the write log to facilitate later tracing.

[0132] 6. The security of CPLD configuration information loading is greatly improved through encryption of byte data and offset sub-address (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance), verification of protection identifier (value of protection identifier, writing order of protection identifier), integrity verification (CRC8 check value of configuration information), timely clearing of protection registers, and isolation of CPU and EEPROM through CPLD.

[0133] 7. When the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time through the voltage sensor, and the power supply voltage is dynamically adjusted through the voltage regulator to be within the preset voltage range, thereby avoiding the failure of configuration information loading caused by unstable power supply voltage, thereby greatly improving the reliability of CPLD configuration information loading.

[0134] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for powering on and loading CPLD configuration information based on dynamic voltage regulation, characterized in that: The steps include: Step S1, the CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte data in the configuration information based on the offset address; Step S2, the CPU encrypts each of the byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively; Step S3, the CPU sends a preset protection identifier, the first encrypted byte data, and an encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus; Step S4, the I2C slave controller writes the received protection identifier, encrypted byte data and encrypted offset sub-address into the protection register, data register and address register respectively; Step S5, after the logic controller of the CPLD verifies the protection identifier written into the protection register, the I2C master controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively; Step S6, the I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain corresponding byte data and the offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address; Step S7, the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until the writing of all the byte data is completed and the protection register is cleared; Step S8, when the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time by the voltage sensor, the power supply voltage is dynamically adjusted by the voltage regulator to make the power supply voltage within a preset voltage range, the logic controller automatically sends a continuous read command to the I2C main controller, and the I2C main controller loads each byte of data stored in the EEPROM into the configuration register based on the received continuous read command to complete the automatic loading of the configuration information at power-on; The step S2 is specifically as follows: The CPU converts each of the byte data into first binary data, divides each of the first binary data in a ratio of 2:6 and swaps the order of the first and second binary data to obtain first intermediate data, and cyclically shifts each character of each of the first intermediate data to the right by 3 bits to obtain encrypted byte data; The CPU converts each of the offset sub-addresses into second binary data, divides each of the second binary data in a ratio of 3:5 and swaps the order of the second binary data to obtain second intermediate data, and circularly shifts each character of each of the second intermediate data to the left by 2 bits to obtain an encrypted offset sub-address; The step S7 is specifically as follows: After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data are written, and sends a write completion notification to the logic controller through the I2C slave controller; The logic controller clears the protection register based on the received write-end notification, reads the configuration information written by the EEPROM through the I2C main controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU; The CPU performs integrity check on the configuration information writing based on the received CRC8 check value to obtain a check result, generates a write log based on the check result, write time, configuration information, offset address, and CPLD serial number, and stores and backs up the write log.

2. A method for powering on a CPLD configuration information based on dynamic voltage regulation as claimed in claim 1, characterized in that: The step S4 is specifically as follows: Based on the write instruction sent by the CPU, the I2C slave controller writes the received encrypted byte data and the encrypted offset sub-address into the data register and the address register in real time, writes the characters carried by the received protection identifier into the protection register in a preset standard write order, and records the actual write order; The step S5 is specifically as follows: The logic controller of the CPLD detects the setting status of the protection register in real time. When the protection register is set, a primary check is performed on the actual writing order based on the preset standard writing order, and then a secondary check is performed on the protection identifier written into the protection register through the protection identifier pre-stored locally, and then the I2C main controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

3. A method for powering on and loading CPLD configuration information based on dynamic voltage regulation as claimed in claim 1, characterized in that: The step S6 is specifically as follows: The I2C master controller circularly shifts each character of the encrypted byte data to the left by 3 bits to obtain first intermediate data, divides the first intermediate data at a ratio of 6:2 and swaps the order to obtain first binary data, converts the first binary data into plain text to obtain byte data, and completes the decryption of the encrypted byte data; circularly shifts each character of the encrypted offset sub-address to the right by 2 bits to obtain second intermediate data, divides the second intermediate data at a ratio of 5:3 and swaps the order to obtain second binary data, converts the second binary data into plain text to obtain an offset sub-address, and completes the decryption of the encrypted offset sub-address; The I2C master controller writes one byte of byte data into the EEPROM in real time based on the offset sub-address.

4. A CPLD configuration information power-on loading system based on dynamic voltage regulation, characterized in that: Includes the following modules: A configuration information preprocessing module is used for the CPU to obtain the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and to generate the offset sub-address of each byte data in the configuration information based on the offset address; An encryption module, used for the CPU to encrypt each of the byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address respectively; The data sending module is used for the CPU to send a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus; A data storage module, used for the I2C slave controller to write the received protection identifier, encrypted byte data and encrypted offset sub-address into a protection register, a data register and an address register respectively; A protection identification verification module, which is used for the logic controller of the CPLD to verify the protection identification written into the protection register, and then control the I2C main controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively; A first byte data writing module is used for the I2C master controller to decrypt the encrypted byte data and the encrypted offset sub-address, obtain the corresponding byte data and the offset sub-address, and write the byte data into the EEPROM based on the offset sub-address; A second byte data writing module is used for the logic controller to forward the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte data until the writing of all the byte data is completed and the protection register is cleared; A configuration information power-on loading module is used to monitor the power supply voltage in real time through a voltage sensor when the CPLD is powered on or the control register is set, and dynamically adjust the power supply voltage through a voltage regulator to make the power supply voltage within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C main controller, and the I2C main controller loads each byte of data stored in the EEPROM into the configuration register based on the received continuous read command to complete the automatic power-on loading of the configuration information; The encryption module is specifically used for: The CPU converts each of the byte data into first binary data, divides each of the first binary data in a ratio of 2:6 and swaps the order of the first and second binary data to obtain first intermediate data, and cyclically shifts each character of each of the first intermediate data to the right by 3 bits to obtain encrypted byte data; The CPU converts each of the offset sub-addresses into second binary data, divides each of the second binary data in a ratio of 3:5 and swaps the order of the second binary data to obtain second intermediate data, and circularly shifts each character of each of the second intermediate data to the left by 2 bits to obtain an encrypted offset sub-address; The second byte data writing module is specifically used for: After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data are written, and sends a write completion notification to the logic controller through the I2C slave controller; The logic controller clears the protection register based on the received write-end notification, reads the configuration information written by the EEPROM through the I2C main controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU; The CPU performs integrity check on the configuration information writing based on the received CRC8 check value to obtain a check result, generates a write log based on the check result, write time, configuration information, offset address, and CPLD serial number, and stores and backs up the write log.

5. A CPLD configuration information power-on loading system based on dynamic voltage regulation as claimed in claim 4, characterized in that: The data storage module is specifically used for: Based on the write instruction sent by the CPU, the I2C slave controller writes the received encrypted byte data and the encrypted offset sub-address into the data register and the address register in real time, writes the characters carried by the received protection identifier into the protection register in a preset standard write order, and records the actual write order; The protection identification verification module is specifically used for: The logic controller of the CPLD detects the setting status of the protection register in real time. When the protection register is set, a primary check is performed on the actual writing order based on the preset standard writing order, and then a secondary check is performed on the protection identifier written into the protection register through the protection identifier pre-stored locally, and then the I2C main controller is controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

6. A CPLD configuration information power-on loading system based on dynamic voltage regulation as claimed in claim 4, characterized in that: The first byte data writing module is specifically used for: The I2C master controller circularly shifts each character of the encrypted byte data to the left by 3 bits to obtain first intermediate data, divides the first intermediate data at a ratio of 6:2 and swaps the order to obtain first binary data, converts the first binary data into plain text to obtain byte data, and completes the decryption of the encrypted byte data; circularly shifts each character of the encrypted offset sub-address to the right by 2 bits to obtain second intermediate data, divides the second intermediate data at a ratio of 5:3 and swaps the order to obtain second binary data, converts the second binary data into plain text to obtain an offset sub-address, and completes the decryption of the encrypted offset sub-address; The I2C master controller writes one byte of byte data into the EEPROM in real time based on the offset sub-address.

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