Halton sequence optimization method and system based on RISC-V vector extension

Abstract

The application relates to a Halton sequence optimization method, system and application based on a RISC-V vector extension, and comprises the following steps: 1) identifying the mathematical characteristics of Halton sequence generation; generating a Halton sequence; after the continuous index values are divided into blocks and grouped, the parallel grouping calculation method is used to realize the simultaneous processing of multiple index values in combination with a vectorization operation; 2) using RISC-V vector instructions for vectorization optimization; in the Halton sequence generation process, the grouped index values are processed in parallel by using RISC-V vector extension instructions; 3) encapsulating into a dynamic link library; and 4) integrating and calling the Hadoop framework. The application significantly reduces the number of loop iterations and greatly improves the efficiency of Halton sequence generation. The application avoids the resource waste in traditional serial calculation, reduces the branch jump and condition judgment overhead, and improves the utilization rate of hardware calculation resources.

Description

Technical Field

[0001] This invention relates to the fields of low-difference sequence generation and high-performance computing, and in particular to a Halton sequence optimization method, system, and application based on RISC-V vector extension. Background Technology

[0002] Halton sequences are low-dispersion sequences widely used in Monte Carlo simulations, financial modeling, and computer graphics. Traditional Halton sequence generation algorithms generate sequences one by one, and their computational efficiency is limited by changes in the sequence index, which may require different computational steps for each index. As the data size increases, this one-by-one computation method performs poorly, especially in large-scale parallel computing environments such as Hadoop.

[0003] Hadoop, as a distributed computing framework, is designed to handle large-scale datasets. However, traditional Halton sequence generation algorithms struggle to fully leverage their parallel computing advantages in this environment because their generation process is inherently serial.

[0004] In existing technologies, the synergy between hardware acceleration algorithms and distributed computing frameworks is limited. For example, even when some hardware optimization techniques are introduced into distributed computing tasks, the lack of suitable dynamic library encapsulation and framework interfaces (such as JNI) makes it difficult to transparently and efficiently integrate optimization algorithms seamlessly into distributed frameworks. Furthermore, most existing hardware optimization methods lack adaptability to mainstream distributed systems, further reducing their practical application value.

[0005] RISC-V vector extensions provide vector processing instructions, making batch operations on data efficient. By identifying the consistency of loop counts in the calculation of consecutive base numbers during Halton sequence generation, vectorized processing can be performed using RISC-V vector instructions, thereby improving the computational efficiency of sequence generation. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a method for optimizing the traditional Halton sequence generation algorithm using RISC-V vector extension instructions. Furthermore, the optimized Halton generation method is applied to the Hadoop distributed computing framework to improve the computational performance of large-scale distributed tasks (such as random number sampling, numerical simulation, and Monte Carlo simulation). This invention combines hardware and software co-optimization with a distributed parallel computing architecture, making it widely applicable to high-performance computing, artificial intelligence, data science, and engineering simulation.

[0007] This invention optimizes the traditional Halton sequence generation algorithm by utilizing RISC-V vector extension instructions, solving problems such as the serial computation bottleneck, insufficient hardware acceleration capabilities, and poor adaptability to distributed computing frameworks in existing Halton sequence generation technologies. This invention provides a Halton sequence optimization method and system based on RISC-V vector extensions, and through dynamic library encapsulation and seamless integration with the Hadoop framework, it significantly improves computational efficiency in distributed computing tasks.

[0008] Terminology Explanation:

[0009] The instructions `vle64_v_f64m4`, `vle64_v_f64m4`, `vfmul_vf_f64m4`, and `vfadd_vv_f64m4` are all instruction functions in RISC-V Vector 1.0 (RVV1.0). They are intrinsic functions of RVV1.0 and can be incorporated into C / C++ programming.<riscv_vector.h> The header file is then called.

[0010] In the instruction `vle64_v_f64m4`, "vle" stands for "vector load element"; "64" indicates that the data to be operated on is 64 bits wide; "v" indicates a vector operation; "f64" indicates a double-precision floating-point number; and "m4" indicates that LMUL=4 is set, meaning that four consecutive vector registers are used as a group, and each group is treated as a single logical vector register. Therefore, this instruction means: load a 64-bit double-precision floating-point number from memory into a vector register.

[0011] The instruction `vfmul_vf_f64m4` means: "vf" stands for vector-float operation; "mul" stands for multiplication; "vf" stands for vector-float scalar; "f64" indicates a double-precision floating-point number; and "m4" has the same meaning. This instruction multiplies each element in the vector register by a scalar floating-point number.

[0012] The instruction `vfadd_vv_f64m4` adds corresponding elements from two vector registers. "vf" stands for vector-float operation; "add" for addition; "vv" for vector-vector; "f64" for double-precision floating-point; and "m4" for the same meaning.

[0013] The Java Native Interface (JNI) is part of the Java platform and serves as an interface for Java code to interact with native code written in other programming languages ​​(such as C / C++). It's a framework provided by the Java Virtual Machine (JVM), enabling Java applications to call native methods and vice versa. It acts as a bridge for interoperability between the Java ecosystem and native code. The specific steps are: first, declare a native method in the Java program; then, compile the program to generate the corresponding JNI / C++ header file; next, implement the corresponding function in the header file using C / C++; finally, compile the C / C++ file into a dynamic library, allowing Java to call the C / C++ implemented function. The reason for using JNI is that since Java does not support direct use of RVV features, writing the relevant RVV calculation code in C / C++ and calling it from the Java program optimizes the Java program.

[0014] The technical solution of this invention is as follows:

[0015] A Halton sequence optimization method based on RISC-V vector extension includes:

[0016] 1) Identify the mathematical properties of Halton sequence generation

[0017] Generate a Halton sequence; after grouping consecutive index values ​​into blocks, use a parallelized grouping calculation method combined with vectorized operations to process multiple index values ​​simultaneously;

[0018] 2) Vectorization optimization using RISC-V vector instructions

[0019] During Halton sequence generation, RISC-V vector extension instructions are used to process the grouped index values ​​in parallel, specifically including:

[0020] Data loading: Load the grouped index values ​​into the vector register;

[0021] Vectorized computation: Parallel multiplication is performed on the index values ​​to complete the carry processing of the Halton values;

[0022] Accumulation generation: The calculation results of multiple index values ​​are accumulated to generate Halton sequence values;

[0023] 3) Encapsulate as a dynamic link library

[0024] The optimized Halton sequence generation algorithm, which is step 1) and 2), is encapsulated into a dynamic link library.

[0025] 4) Integration and invocation with the Hadoop framework

[0026] The optimized Halton sequence generation algorithm is integrated into the Hadoop MapReduce framework via the JNI interface and used as a random number generation source or low-difference sequence generator in the Hadoop distributed computing environment.

[0027] Preferably, for a Halton sequence H with a base of 2, an index starting at index, and a sequence length of length, ... base (i), Halton sequence H base (i) The generating formula is equation (i):

[0028]

[0029] Wherein: H base (i) represents the i-th value of the Halton sequence with base b; base is the chosen prime base; d k (i) is the k-th digit of the integer i expanded according to the base b; i is the input index value; n is the number of digits of the integer i in the base b.

[0030] Preferably, a parallelized grouping computation method, combined with vectorized operations, enables the simultaneous processing of multiple index values; including:

[0031] 1) For index values ​​from index to index + length - 1, group the integers into blocks based on base, with each block having a length of base. Design different loading and parallel processing strategies depending on whether the index and base are aligned, as follows:

[0032] When the index is an integer multiple of the base, the entire group is loaded directly into the vector register;

[0033] When the index is not an integer multiple of base, the first r = base - (index % base) data are calculated separately, and the subsequent data are processed in parallel.

[0034] 2) For the remaining data to be processed, if the size of the remaining data is not less than base, the entire set of vector registers will be used for parallel processing; otherwise, the remaining data will be calculated separately.

[0035] Preferably, vectorization optimization is performed using RISC-V vector instructions, including:

[0036] The vle64_v_f64m4 instruction in the RISC-V vector extension instruction set is used to load the index value group into the vector register;

[0037] The vfmul_vf_f64m4 instruction is used to perform vectorized multiplication on the index value to complete the carry processing.

[0038] The calculation results of multiple index values ​​are accumulated using the vfadd_vv_f64m4 command to generate multiple Halton sequence values.

[0039] Preferably, it is encapsulated as a dynamic link library, including:

[0040] An optimized Halton sequence generation algorithm was written in C++; the optimized Halton sequence generation algorithm was compiled into a dynamic link library; and the dynamic library was encapsulated through a Java Native Interface so that it could be called by Java programs.

[0041] A computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of a Halton sequence optimization method based on RISC-V vector extension.

[0042] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a Halton sequence optimization method based on RISC-V vector extension.

[0043] A Halton sequence optimization system based on RISC-V vector extension includes:

[0044] Input module: Provides the parameters required for generating the Halton sequence, including: starting index, generated length, and Halton sequence cardinality.

[0045] Halton optimization algorithm module: It realizes efficient parallel generation of Halton sequences through hardware acceleration technology based on RISC-V vector instructions;

[0046] Dynamic library encapsulation module: encapsulates the optimized Halton sequence generation algorithm into a dynamic library, providing a standard interface for invocation; JNI interface module: exposes the dynamic library functionality to the distributed computing framework through Java Native Interface technology;

[0047] In the Hadoop MapReduce framework, the optimized Halton sequence generation algorithm is used for task decomposition and result integration in distributed computing.

[0048] Results output module: Based on the computation task, output the low-discrepancy sequence or the results of Monte Carlo simulation.

[0049] The aforementioned applications of the Halton sequence optimization method based on RISC-V vector extension include its use in distributed computing tasks such as Monte Carlo simulation, numerical integration, and random sampling.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. Significantly improved generation efficiency. The Halton sequence generation algorithm is optimized by using RISC-V vector extension instructions, enabling simultaneous processing of multiple index values, significantly reducing the number of loop iterations, and greatly improving the efficiency of Halton sequence generation.

[0052] 2. Improved hardware resource utilization. This invention fully utilizes the hardware parallel computing capabilities of the RISC-V vector extension instruction set, avoiding resource waste in traditional serial computing, while reducing branch jumps and conditional judgment overhead, thus improving the utilization rate of hardware computing resources.

[0053] 3. Adaptable to distributed computing frameworks. The optimized Halton sequence generation algorithm is encapsulated in a dynamic library and integrated with the Hadoop framework, enabling seamless application in distributed computing tasks. This significantly improves computing efficiency in distributed environments while reducing communication overhead between task nodes.

[0054] 4. Wide range of practical applications. This invention is applicable to various distributed computing tasks such as Monte Carlo simulation, numerical integration, and random sampling. It exhibits significant performance advantages, especially in scenarios requiring the generation of large-scale, low-discrepancy point sequences, thus broadening the application scope of Halton sequences in the field of high-performance computing. Attached Figure Description

[0055] Figure 1 This is a block diagram of the Halton sequence optimization system based on RISC-V vector extension of the present invention;

[0056] Figure 2 This is a schematic diagram of the Halton vectorization optimization algorithm of the present invention;

[0057] Figure 3 This is a schematic diagram illustrating the performance improvement effect of the present invention; Detailed Implementation

[0058] The present invention will be further defined below with reference to the accompanying drawings and embodiments, but is not limited thereto.

[0059] Example 1

[0060] To better implement the technical solution of this invention, the following will specifically describe the Halton sequence optimization method based on RISC-V vector extension and its application in a distributed computing framework. This invention designs an algorithm for efficient generation of low-difference points by combining the mathematical properties of Halton sequences and RISC-V vector extension technology, and implements dynamic library encapsulation for easy application in a distributed computing framework. Specific implementations of this invention include: vectorized optimization design of Halton sequences, data processing strategies in vector registers, dynamic library encapsulation, integration into a distributed computing framework, and expansion for practical distributed application tasks. 1. Vectorized Optimization Design of Halton Sequences

[0061] This invention aims to solve the serial performance bottleneck of the traditional Halton sequence point-by-point generation method, and designs an efficient parallel computing scheme by combining RISC-V vector extension technology.

[0062] A Halton sequence optimization method based on RISC-V vector extension includes:

[0063] 1) Identify the mathematical properties of Halton sequence generation

[0064] The mathematical characteristics of Halton sequence generation were analyzed, revealing that the index values ​​have the same number of carry-overs within a consecutive base range during the generation process. This characteristic was used to transform the traditional serial algorithm of point-by-point calculation into a parallelizable group calculation method; Halton sequence was generated; after grouping consecutive index values ​​into blocks, the parallelized group calculation method, combined with vectorization operations, enabled the simultaneous processing of multiple index values.

[0065] 2) Vectorization optimization using RISC-V vector instructions

[0066] During Halton sequence generation, RISC-V vector extension instructions are used to process the grouped index values ​​in parallel, specifically including:

[0067] Data loading: via VLE <sew>_v_f <vsew> m <lmul>The instruction loads the grouped index values ​​into the vector register, ensuring that multiple index values ​​can be processed simultaneously.

[0068] Vectorized computation: using vfmul_vf_f <vsew> m <lmul>The instruction performs parallel multiplication on the index value to complete the carry processing of the Halton value;

[0069] Accumulation generation: via vfadd_vv_f <vsew> m <lmul>The instruction sums the calculation results of multiple index values ​​to generate a Halton sequence value;

[0070] The vectorization operations described above significantly reduce the number of iterations in traditional algorithms, thereby improving the efficiency of Halton sequence generation.

[0071] 3) Encapsulate as a dynamic link library

[0072] The optimized Halton sequence generation algorithm, derived from steps 1) and 2), is encapsulated into a dynamic link library (.so file) for integration into the Hadoop distributed computing framework via the Java Native Interface (JNI). This dynamic library encapsulation allows the method to be adapted to other distributed computing frameworks, improving its versatility and ease of use.

[0073] Steps 1) and 2) outline the idea behind optimizing the Halton sequence generation algorithm. The "optimized Halton sequence generation algorithm" here refers to the optimized algorithm implemented based on the ideas in steps 1) and 2). Specifically, it can be described as follows: Based on the identified mathematical characteristics, the data is first aligned by index values, grouped, and then the grouped data is processed using vectorized operations such as "data loading," "vectorized calculation," and "cumulative generation." Taking advantage of the dynamically adjustable vector operation length (VL) characteristic of RVV, the data is processed in parallel, thus optimizing the serial algorithm with vectorization.

[0074] 4) Integration and invocation with the Hadoop framework

[0075] The optimized Halton sequence generation algorithm is integrated into the Hadoop MapReduce framework via the JNI interface, and used as a random number generator or low-dispersion sequence generator in the Hadoop distributed computing environment. By calling this optimized algorithm in MapReduce tasks, the efficiency of Halton sequence generation in distributed computing tasks is significantly improved, and the waiting time and communication overhead between task nodes are reduced.

[0076] Example 2

[0077] The Halton sequence optimization method based on RISC-V vector extension described in Example 1 differs in that:

[0078] Mathematical models based on Halton sequences are used for Halton sequences H with a base, starting index value as index, and sequence length of length. base (i), Halton sequence H base (i) The generating formula is equation (i):

[0079]

[0080] Wherein: H base (i) represents the i-th value of the Halton sequence with base b; base is the chosen prime base (e.g., 2, 3, 5, etc.); d k (i) is the k-th digit of the integer i expanded according to the base b; i is the input index value; n is the number of digits of the integer i in the base b.

[0081] During the Halton sequence generation process, consecutive index values ​​are divided into blocks according to computational capabilities, and multiple index values ​​are calculated simultaneously in each block. By leveraging the instruction parallelism capabilities and vector register capacity supported by RISC-V vector extensions, the dependency of point-by-point computation is eliminated, thus achieving parallelization optimization.

[0082] For calculating index values ​​in a Halton sequence, this invention designs a method that combines vector registers for block processing, and uses a parallelized grouping calculation method combined with vectorized operations to achieve simultaneous processing of multiple index values; including:

[0083] 1) For index values ​​from index to index + length - 1, group the integers into blocks based on base, with each block having a length of base. Design different loading and parallel processing strategies depending on whether the index and base are aligned, as follows:

[0084] When the index is an integer multiple of the base, the batch of data is aligned and can be directly loaded into the vector register without separate processing.

[0085] When the index is not an integer multiple of the base, the first r = base - (index % base) data are calculated separately (called padding), and the subsequent data are processed in parallel.

[0086] 2) For the remaining data to be processed, if the size of the remaining data is not less than base, the entire set of vector registers will be used for parallel processing; otherwise, the remaining data will be calculated separately.

[0087] Based on the above logical design, such as Figure 2 As shown, the vectorized calculation process of this invention is as follows:

[0088] a. Input parameters; including: sequence starting index, total generated length, and prime number base of the Halton sequence (supports multiple dimensions);

[0089] b. Initialize the current processing position and the remaining data length. The remaining length is set to length.

[0090] c. Group data according to the alignment of index and base:

[0091] If the index is divisible by the base, no padding is needed, and the data can proceed directly to normal grouping.

[0092] Otherwise, calculate separately for the data with the current starting segment length r = base - (index % base), and update the index and remaining length;

[0093] d. For each remaining data segment:

[0094] If the current remaining length is greater than or equal to base, then directly load a set of index values ​​of length base into the vector register and use RISC-V vector instructions for parallel processing;

[0095] If the remaining length is less than the base, then scalar calculations are performed on that portion of the data separately.

[0096] Through the design of the above process, this invention effectively utilizes the vectorization characteristics of RISC-V to achieve parallel operation of the entire set of data, while solving the boundary problem caused by the initial offset.

[0097] Vectorization optimization using RISC-V vector instructions includes:

[0098] The vle64_v_f64m4 instruction in the RISC-V vector extension instruction set is used to load the index value group into the vector register;

[0099] The vfmul_vf_f64m4 instruction is used to perform vectorized multiplication on the index value to complete the carry processing.

[0100] The calculation results of multiple index values ​​are accumulated using the vfadd_vv_f64m4 command to generate multiple Halton sequence values.

[0101] To achieve the above parallel optimization scheme, this invention designs an efficient hardware affinity algorithm based on the support of RISC-V vector extension instructions. Specifically, it includes the following steps:

[0102] 2.1 Data Loading and Initialization

[0103] Determine the index length for each operation based on the vector register capacity:

[0104] 1) Configure the length of the vector register to support multi-index parallel computation;

[0105] 2) After grouping the index segments by base, load them into the register in batches. Each operation uses a fixed set of consecutive index values ​​(including data after unalignment processing).

[0106] 2.2 Parallel Computing

[0107] To leverage the weighted, hierarchical accumulation characteristics of Halton sequences, batch computation is performed using RISC-V vector registers to accomplish the following tasks:

[0108] Each index group is decomposed into high-order and low-order weights expanded in base 2;

[0109] The multiplication and accumulation of each place value is completed synchronously through vector operations (solving the problem of calculating the place value coefficients).

[0110] Vector operations are fully parallelized, reducing the loop time for bit-by-bit processing.

[0111] 2.3 Boundary Processing

[0112] After batch parallel processing is completed, scalar computation is performed on the remaining index segments that are less than a set (less than the base). Since single-point computation and vector computation share the same formula and have the same processing flow, there is no need to design complex logic separately.

[0113] Encapsulated as a dynamic link library, including:

[0114] An optimized Halton sequence generation algorithm was written in C++; the optimized Halton sequence generation algorithm was compiled into a dynamic link library; and the dynamic library was encapsulated through the Java Native Interface (JNI) so that it could be called by Java programs.

[0115] To enable cross-platform and cross-language calls to the optimized Halton sequence generation algorithm and facilitate its integration in distributed computing frameworks, this invention encapsulates the algorithm as a dynamic link library (such as a .so file) and implements an external interface through Java Native Interface (JNI), ensuring efficient call to the algorithm's functions and flexible expansion.

[0116] The dynamic link library encapsulation process of this invention includes the following steps:

[0117] 1) Encapsulation of the core algorithm

[0118] The Halton sequence generation algorithm was developed using C++, and the computational logic optimized with RISC-V vector instructions was encapsulated into a general-purpose function interface. The core function interface is as follows:

[0119] void generate_halton_sequence(int start_idx,intlength,int base[],double result[]);

[0120] Parameter description:

[0121] start_idx: The starting index value for generating the sequence;

[0122] length: The length of the generated sequence;

[0123] base[]: A radix array used to support the generation of multidimensional Halton sequences;

[0124] result[]: Output array used to store the generated Halton sequence results.

[0125] This interface supports the generation of multi-dimensional Halton sequences and fully utilizes the parallel computing capabilities of RISC-V vector instructions to ensure efficiency and accuracy.

[0126] 2) Compilation and generation of dynamic libraries

[0127] C++ code is compiled into a dynamic link library (generating a .so file on Linux and a .dll file on Windows) to enable cross-platform dynamic loading and calling. For example, the dynamic library file generated on Linux is named libhalton.so.

[0128] During the compilation process, we ensure that the dynamic library is compatible with mainstream hardware architectures (such as RISC-V and x86) and operating systems (such as Linux, Windows and macOS), and optimize for the hardware instruction set characteristics of different platforms.

[0129] 3) Testing and verification of dynamic libraries

[0130] After encapsulation, the functionality, performance, and stability of the dynamic library are thoroughly tested to ensure that it can correctly generate Halton sequences and maintain efficiency and reliability during invocation.

[0131] To support integration with distributed computing frameworks (such as Hadoop and Spark), this invention performs a secondary encapsulation of the dynamic link library using Java Native Interface (JNI), providing a calling interface for Java applications. The specific design is as follows:

[0132] 1) Java Interface Definition

[0133] Provides a Java native method interface, allowing Java programs to call core functions in dynamic libraries. The method signature is as follows:

[0134] public native double[]generateHaltonSequence(int startIdx,intlength,int[]base);

[0135] Parameter description:

[0136] startIdx: The starting index value for generating the sequence;

[0137] length: The length of the generated sequence;

[0138] base: a radix array that supports multi-dimensional Halton sequence generation;

[0139] The return value is an array of the generated Halton sequence results.

[0140] 2) Dynamic library loading and initialization

[0141] In Java programs, dynamic libraries are loaded using `System.loadLibrary("halton")`. This method automatically loads the corresponding dynamic library file based on the hardware architecture.

[0142] Once loaded, the core algorithm in the dynamic library can be directly called through the Java interface to generate the Halton sequence.

[0143] 3) Cross-platform compatibility

[0144] Through JNI encapsulation, the dynamic library supports running in various distributed frameworks and platforms, adapts to mainstream operating systems and hardware architectures, and ensures the universality and scalability of the algorithm.

[0145] This invention integrates an optimized Halton sequence generation algorithm into a distributed computing framework (such as Hadoop MapReduce) to support large-scale, low-dispersion parallel generation and distributed computing tasks. Through the combination of dynamic libraries and JNI interfaces, this invention can efficiently generate Halton sequences in a distributed environment and significantly improve the performance of computing tasks. Integration and application within the distributed computing framework include:

[0146] 4.1 Calls during the Map phase

[0147] 1) Task allocation and Halton sequence generation

[0148] During the Map phase of a MapReduce task, each Map task independently calls the Halton sequence generation algorithm in the dynamic library to generate the required low-discrepancy point sequence.

[0149] Through the JNI interface, the Map task can directly call the generate_halton_sequence method of the dynamic library to generate a Halton sequence of a specified length.

[0150] The Halton point sequence generated by each Map task can be used as input data for subsequent calculations, such as sample points in Monte Carlo simulations or sampling points in numerical integration.

[0151] 2) Advantages of parallelization

[0152] Because the Halton sequence generation algorithm is vectorized and optimized, it can fully utilize the parallel computing capabilities of the underlying hardware, thus significantly improving the efficiency of the Map task when generating large-scale low-discrepancy points.

[0153] Each Map task generates a point sequence independently, avoiding communication overhead between nodes and further improving the parallel efficiency of distributed tasks.

[0154] 4.2 Aggregation of Results in the Reduce Phase

[0155] During the Reduce phase, the Halton sequences generated by the Map tasks will be submitted to the Reduce tasks for integration of global results.

[0156] Experimental Results and Applicable Scenarios

[0157] 5.1 Experimental Environment and Test Plan

[0158] 1) Experimental Environment

[0159] Test platform: RISC-V hardware platform, combined with the Hadoop MapReduce distributed computing framework, running on XXX (operating system, specific configuration).

[0160] Experimental scenario: π value calculation task in Monte Carlo simulation. This is a classic example program for Hadoop MapReduce computation.

[0161] 2) Test Plan Description

[0162] Test task: In Monte Carlo simulation, generate a point sequence using random sampling, and then optimize it using a low-discrepancy Halton sequence to reduce randomness error and improve computational efficiency.

[0163] Comparison method: The unoptimized Halton sequence generation algorithm (the original algorithm, hereinafter referred to as T) is compared. original The RISC-V vectorization optimization algorithm (optimization algorithm, hereinafter referred to as T) proposed in this invention is similar to the algorithm itself. optimized Compare them.

[0164] Evaluation metrics: Performance improvement metrics based on the time consumed in task computation.

[0165] in:

[0166] T original : The runtime required to complete the task using the original, unoptimized algorithm;

[0167] T optimized The running time required to complete the task using the method of this invention;

[0168] η: Percentage of performance improvement, used to quantify the optimization effect.

[0169] 5.2 Experimental Results

[0170] 1) Quantitative data on performance improvement

[0171] This invention was applied in a Monte Carlo simulation task, specifically a MapReduce distributed program for calculating the value of π, and was experimentally tested under the same hardware platform and framework settings.

[0172] Experimental results are as follows Figure 3 As shown, the Halton sequence generation method optimized based on this invention achieves a significant performance improvement, with a performance enhancement of 89.32%. That is:

[0173]

[0174] The optimized algorithm significantly reduces the computation time in the Halton sequence generation process and improves the overall efficiency of the MapReduce task, especially in the general-purpose Monte Carlo simulation model.

[0175] 2) Comparative Analysis

[0176] The original method has its shortcomings: the traditional point-by-point generation of Halton sequences is severely dependent on circularity and cannot fully utilize the parallel performance of hardware, making the generation process a bottleneck in distributed simulation computing.

[0177] In this invention, vectorized operations are implemented by fully utilizing the vector registers provided by RISC-V hardware, which greatly reduces the time complexity of point sequence generation; block and alignment optimization is achieved by blocking index values ​​and aligning vector registers, which improves the concurrency of data loading and computation operations; and dynamic library integration is achieved by easily integrating the optimized Halton generation algorithm into the MapReduce framework through dynamic library encapsulation, resulting in a smoother task flow.

[0178] 5.3 Application Scenario Analysis

[0179] 1) Applicable Scenarios

[0180] The optimized Halton sequence generation method of this invention has wide applicability and can be applied to various practical scenarios in large-scale distributed computing tasks, such as:

[0181] Monte Carlo simulation: By generating low-discrepancy points through Halton sequences, it can efficiently complete complex system simulation tasks, such as option pricing in finance and system behavior simulation in physical sciences.

[0182] Numerical integration and sampling: In high-dimensional integration problems, low-discrepancy points are used to reduce computational errors and improve the accuracy of integral estimation;

[0183] Machine Learning and Model Training: Low-discrepancy points generated by Halton sequences can be used for tasks such as data augmentation and hyperparameter search to improve training results;

[0184] Other distributed stochastic computations include point sample generation in statistical simulations and data visualization.

[0185] 2) Extensibility Analysis

[0186] The cardinality array and point sequence dimension of the Halton sequence can be flexibly adjusted for different tasks, making the method of this invention adaptable to various distributed computing needs.

[0187] The underlying algorithm optimizations upon which this invention relies (such as vectorization implementation and dynamic library encapsulation) have strong versatility and can be integrated into mainstream distributed frameworks (such as Hadoop, Spark, Flink, etc.), adapting to more practical scenarios.

[0188] 5.4 Summary of Optimization Results

[0189] Experimental results show that this invention significantly improves performance in classic distributed computing tasks (such as Monte Carlo simulation of π value calculation), achieving a performance improvement of up to 89.32%. Furthermore, by introducing RISC-V vectorization technology, this invention effectively overcomes the performance bottleneck of the original point-by-point generation algorithm, demonstrating high efficiency, adaptability, and ease of use in large-scale distributed computing tasks. Its optimization methods and technical implementation have significant practical implications for improving the performance of distributed computing tasks.

[0190] 6. Error Handling and Optimization

[0191] To ensure the stability and robustness of this invention in various operating environments, a comprehensive error handling mechanism is designed and combined with performance optimization strategies to achieve efficient and reliable Halton sequence generation.

[0192] 6.1 Parameter Verification Mechanism

[0193] During the input phase, the parameters are thoroughly checked to ensure that the input index values ​​are non-negative integers, the sequence length is within a reasonable range, and all values ​​in the radix array are valid prime numbers. If the parameters do not meet the requirements, an error message is immediately returned and the calculation is terminated to prevent error propagation.

[0194] A maximum limit is set for the length of the generated sequence to prevent excessive computational tasks from causing memory shortages or performance degradation.

[0195] 6.2 Memory Management and Resource Release

[0196] During Halton sequence generation, dynamically allocated memory space is released immediately after use to avoid resource leaks.

[0197] For the allocation and use of vector registers, ensure that cleanup is performed after the calculation is completed to release hardware resources.

[0198] In the event of an anomaly or error interruption, a resource reclamation mechanism is designed to ensure that all allocated resources can be safely released.

[0199] 6.3 Runtime Error Detection and Handling

[0200] When executing vectorized instructions, the availability of hardware vector units is monitored in real time. If a vector unit is unavailable or an execution error occurs, the invention automatically degrades to scalar computation mode to ensure the task can continue to complete.

[0201] During task execution, an error logging mechanism is set up to record the time, cause, and context of errors in detail for subsequent analysis and optimization.

[0202] 6.4 Performance Optimization Measures

[0203] When processing large-scale data, a block-based computing strategy is adopted, which dynamically adjusts the size of data blocks according to the hardware cache size, reducing memory access latency and improving cache hit rate.

[0204] To take advantage of the characteristics of RISC-V vector instructions, the execution order of the instruction pipeline has been optimized, reducing dependencies between instructions and improving the utilization of hardware computing units.

[0205] For computationally repetitive tasks, a result caching mechanism is used to avoid redundant calculations and further improve performance.

[0206] 7. Security Design

[0207] This invention fully considers data security, concurrency security, and the reliability of the operating environment during its design and implementation, ensuring that the algorithm can run safely in various scenarios.

[0208] 7.1 Data Security

[0209] During data processing, a strict boundary check mechanism is designed to ensure that out-of-bounds access does not occur when accessing arrays or buffers, thus preventing potential security vulnerabilities.

[0210] A verification mechanism was designed for both input and output data to ensure data integrity and correctness. For example, after generating the Halton sequence, the results can be randomly sampled and verified to ensure that the generated point sequence conforms to the expected mathematical properties.

[0211] 7.2 Concurrency Security

[0212] In multithreaded or distributed environments, thread-safe resource access control mechanisms are employed to ensure that no conflicts occur when multiple threads or nodes access shared resources simultaneously. For example, when reading or writing shared data, locking mechanisms or atomic operations are used to ensure data consistency.

[0213] For the management of global state, a synchronization mechanism for initialization and destruction was designed to ensure that no competition for resource initialization or release occurs in a multi-threaded environment.

[0214] 7.3 Reliability of the operating environment

[0215] In a distributed computing environment, nodes may be interrupted due to hardware failures or network problems. This invention designs a fault recovery mechanism that allows tasks to restart after an interruption and continue execution from the point of interruption, avoiding redundant computation.

[0216] For potential hardware anomalies (such as vector unit failures), a degradation strategy was designed to automatically switch to compatibility mode to ensure task continuity.

[0217] 8. Compatibility Design

[0218] To ensure that this invention can run normally on different hardware platforms and distributed computing frameworks, multi-level compatibility support has been designed.

[0219] 8.1 Hardware Compatibility

[0220] This invention supports different versions of the RISC-V architecture, including processors with vector extension instruction sets and general-purpose processors without vector extension. When vector extension is detected as not being supported by the hardware, the algorithm automatically switches to scalar computation mode, ensuring compatibility on low-end hardware.

[0221] To adapt to different hardware characteristics, this invention designs a hardware detection mechanism that automatically detects the instruction set characteristics supported by the processor at runtime and selects the optimal execution path based on hardware capabilities. For example, on hardware that supports vector extensions, vectorization algorithms are used preferentially, while on hardware that does not support them, scalar algorithms are used.

[0222] 8.2 Backward Compatibility

[0223] This invention fully considers backward compatibility during its design process, ensuring normal operation during future hardware or software upgrades. For example, in a new version of the RISC-V architecture, if the instruction set changes, this invention can quickly adapt to the new architecture by updating the hardware detection module and instruction mapping table.

[0224] For version upgrades of distributed frameworks, this invention provides an extensible adaptation interface, allowing users to quickly adapt to new versions of the framework without modifying the core algorithm.

[0225] Example 3

[0226] A computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the Halton sequence optimization method based on RISC-V vector extension as described in Embodiment 1 or 2.

[0227] Example 4

[0228] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the Halton sequence optimization method based on RISC-V vector extension as described in Embodiment 1 or 2.

[0229] Example 5

[0230] A Halton sequence optimization system based on RISC-V vector extension, such as Figure 1 As shown, it includes:

[0231] Input module: Provides the parameters required for generating the Halton sequence, including: starting index, generated length, and Halton sequence cardinality.

[0232] Halton optimization algorithm module: This is the core module of the invention, which realizes efficient parallel generation of Halton sequences through hardware acceleration technology based on RISC-V vector instructions;

[0233] Dynamic library encapsulation module: Encapsulates the optimized Halton sequence generation algorithm into a dynamic library, providing a standard interface for calling;

[0234] JNI interface module: Exposes dynamic library functionality to distributed computing frameworks (such as Hadoop) through Java Native Interface technology;

[0235] The Hadoop MapReduce framework: In distributed computing, the optimized Halton sequence generation algorithm is used for task decomposition (Map phase) and result integration (Reduce phase);

[0236] Results output module: Based on the computational task, outputs low-dispersion point sequences or Monte Carlo simulation results. For example, estimation of the value of π.

[0237] By working together, the efficiency bottleneck of Halton sequence generation in distributed computing scenarios is solved.

[0238] The aforementioned applications of the Halton sequence optimization method based on RISC-V vector extension include its use in distributed computing tasks such as Monte Carlo simulation, numerical integration (e.g., high-dimensional integral calculation), and random sampling (e.g., data augmentation tasks in machine learning). In Monte Carlo simulation (e.g., π value calculation, financial risk assessment), the performance improvement effect of this invention was verified through multi-node MapReduce task calls, significantly shortening task completion time and improving the overall performance of the distributed computing environment.

[0239] The above-mentioned Halton sequence optimization method based on RISC-V vector extension is applied in the Hadoop framework as follows: calling the optimized Halton sequence generation algorithm in Hadoop's MapReduce task; generating large-scale low-discrepancy point sequences in the Map phase as input for Monte Carlo simulation or numerical integration; and aggregating the calculation results in the Reduce phase to improve the overall performance of distributed computing tasks.< / lmul> < / vsew> < / lmul> < / vsew> < / lmul> < / vsew> < / sew>

Claims

1. A Halton sequence optimization method based on RISC-V vector extension, characterized in that, The method comprises the following steps: 1) identifying the mathematical characteristics of Halton sequence generation generating Halton sequence; after grouping the continuous index values, the parallel grouping calculation method is used to realize the simultaneous processing of multiple index values by combining vectorization operation; 2) vector optimization using RISC-V vector instructions In the process of generating Halton sequence, the grouped index values are processed in parallel using RISC-V vector extension instructions, which includes the following steps: Data loading: load the grouped index values into the vector register; Vectorized calculation: perform parallel multiplication operation on the index values to complete the carry processing of Halton values; Accumulation generation: accumulate the calculation results of multiple index values to generate Halton sequence values; 3) packaging as a dynamic link library The optimized Halton sequence generation algorithm in steps 1) and 2) is packaged as a dynamic link library; 4) integration and calling with Hadoop framework The optimized Halton sequence generation algorithm is integrated into the MapReduce framework of Hadoop through JNI interface and used as a random number generation source or low-discrepancy sequence generator in the Hadoop distributed computing environment; Through the parallel grouping calculation method, the simultaneous processing of multiple index values is realized by combining vectorization operation, which includes the following steps: 1) For index to index+length-1, group the integers by base block by block, and design different loading and parallel processing strategies for the alignment of index and base, as follows: When index is an integer multiple of base, load the whole group into the vector register directly; When index is not an integer multiple of base, the first r=base-(index%base) data is calculated separately, and the subsequent data is processed in parallel; 2) For the remaining data to be processed, if the size of the remaining data is not less than base, use the whole group of vector registers for parallel processing; otherwise, calculate the remaining data separately.

2. The Halton sequence optimization method based on RISC-V vector extension according to claim 1, characterized in that, For a Halton sequence H with base base, index starting at index, and length length base (i) Halton sequence H base (i) the generating formula is formula (i): where: H bsse (i) denotes the i-th value of the Halton sequence in base b; base is a selected prime base; d k (i) is the k-th digit of the integer i when expanded in base b; i is the input index value; n is the number of digits of the integer i in base b.

3. The Halton sequence optimization method based on RISC-V vector extension according to claim 1, characterized in that, Vector optimization using RISC-V vector instructions includes the following steps: Load the index value group into the vector register using the vle64_v_f64m4 instruction in the RISC-V vector extension instruction set; Use the vfmul_vf_f64m4 instruction to perform vectorized multiplication calculation on the index values to complete the carry processing; Generate multiple Halton sequence values by accumulating the calculation results of multiple index values using the vfadd_vv_f64m4 instruction.

4. The Halton sequence optimization method based on RISC-V vector extension according to claim 1, wherein, Packaging as a dynamic link library includes the following steps: Use C++ language to write the optimized Halton sequence generation algorithm; compile the optimized Halton sequence generation algorithm into a dynamic link library; encapsulate the dynamic library through Java Native Interface interface so that it can be called by Java program. 5.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-4 when the computer program is executed by the processor. The processor executes the computer program to realize the steps of the RISC-V vector extension based Halton sequence optimization method according to any one of claims 1-4.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the Halton sequence optimization method based on the RISC-V vector extension according to any one of claims 1-4.

7. A Halton sequence optimization system based on RISC-V vector extension, characterized in that, Comprise: An input module: provides parameters required for Halton sequence generation, including: starting index index, generation length length, and Halton sequence base base; Halton optimization algorithm module: through the hardware acceleration technology based on RISC-V vector instruction, realize the efficient parallel generation of Halton sequence; Dynamic library packaging module: encapsulate the optimized Halton sequence generation algorithm into a dynamic library, and provide a standard interface that can be called; JNI interface module: through Java Native Interface technology, expose the dynamic library function to the distributed computing framework; Hadoop MapReduce framework: in distributed computing, the optimized Halton sequence generation algorithm is used for task decomposition and result integration; Result output module: according to the calculation task, output low difference point sequence or Monte Carlo simulation result; Through the hardware acceleration technology based on RISC-V vector instruction, realize the efficient parallel generation of Halton sequence; including: 1) Identify the mathematical properties of Halton sequence generation Generate Halton sequence; After grouping the continuous index values, the parallel grouping calculation method is used to realize the simultaneous processing of multiple index values combined with vector operation; 2) Use RISC-V vector instruction for vector optimization In the process of generating Halton sequence, use RISC-V vector extension instruction to process the grouped index values in parallel, including: Data loading: load the grouped index values into the vector register; Vectorized calculation: perform parallel multiplication operation on the index values to complete the carry processing of Halton value; Accumulative generation: accumulate the calculation results of multiple index values to generate Halton sequence value; Through the parallel grouping calculation method, combined with the vector operation, realize the simultaneous processing of multiple index values; including: 1) For index to index+length-1 index values, group the integers by base block by block, each group length is base, and different loading and parallel processing strategies are designed according to whether index and base are aligned, as follows: When index is an integer multiple of base, load the whole group into the vector register directly; When index is not an integer multiple of base, the first r=base-(index%base) data is calculated separately, and the subsequent data is processed in parallel; 2) For the remaining data to be processed, if the size of the remaining data is not less than base, use the whole group of vector registers to process in parallel; otherwise, calculate the remaining data separately.

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