FLASH extended space read-write access method based on domestic Feiteng E2000Q processor

Abstract

The embodiment of the invention relates to the technical field of communication, in particular to a FLASH extended space read-write access method based on a domestic Feiteng E2000Q processor, which comprises the following steps of: in the aspect of hardware, respectively hanging a plurality of FLASH chips in different chip selection spaces of a QSPI (Query Serial Peripheral Interface) controller of the domestic Feiteng E2000Q processor, providing clock signals for each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through the FPGA, and a standard library is formed; in the aspect of software, when FLASH erasing, reading or programming operation needs to be carried out, selection of different FLASH chips is achieved in the mode that FLASH chip selection parameters are transmitted to a chip selection register of the QSPI controller, and read-write access operation is achieved in the mode that FLASH addresses are transmitted to an address register of the QSPI controller. Read-write operation of the high-order data and the low-order data in the same address space is achieved in a data splicing and analyzing mode. According to the method, the flexibility of the domestic Feiteng E2000Q processor in the aspects of application program solidification and FLASH address space allocation is well improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular to a FLASH extended space read and write access method based on a domestic Feiteng E2000Q processor. Background Art

[0002] With the increasing complexity and technological level of aviation airborne electronic equipment, the integration of electronic modules is getting higher and higher. The number of application software deployed on a CPU (Central Processing Unit) module is increasing. As the application software processing tasks increase, the software scale is also increasing, and the demand for FLASH address space is also increasing.

[0003] The current domestically produced Feiteng E2000Q processor only supports 256MB of FLASH address space. In actual application, there is a possibility that the storage requirements of application software may not be met, and the technical protocols of some products require the FLASH address space to be no less than 512MB. Therefore, the current domestically produced Feiteng E2000Q processor has a serious lack of FLASH storage capacity, and has poor flexibility in application solidification and FLASH address space allocation. Summary of the invention

[0004] In view of this, the embodiment of the present application proposes a FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor, which can realize read and write access to the FLASH extended address space, improve the available storage capacity of FLASH, solve the problem of insufficient FLASH storage capacity of the domestic Feiteng E2000Q processor, and improve the flexibility of the domestic Feiteng E2000Q processor in application solidification and FLASH address space allocation.

[0005] In the first aspect, an embodiment of the present application proposes a method for reading and writing access to a FLASH extension space based on a domestic Feiteng E2000Q processor, comprising the following steps: in terms of hardware, a plurality of FLASH chips are respectively mounted in different chip select spaces of a QSPI controller of a domestic Feiteng E2000Q processor, a clock signal is provided to each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through an FPGA, and a standard library is formed; in terms of software, when FLASH erasing, reading, or programming operations are required, selection of different FLASH chips is achieved by passing FLASH chip select parameters to a chip select register of the QSPI controller, read and write access operations are achieved by passing FLASH addresses to an address register of the QSPI controller, and read and write operations of high-order data and low-order data in the same address space are achieved by data splicing and parsing.

[0006] In some optional embodiments, the access interface of the FLASH expansion space of the domestic Feiteng E2000Q processor is standardized and packaged, including an erase interface, a read interface, and a programming interface.

[0007] In some optional embodiments, the erase interface is implemented by the following steps: obtaining the base address and length of the FLASH erase; calculating the first address of the block area where the FLASH address is located, the number of erased blocks and the chip select space to which it belongs; setting the FLASH chip select instruction and the FLASH write enable instruction in the command register; setting the FLASH chip select instruction and the FLASH erase instruction in the command register, and setting the base address of this FLASH erase in the address register; executing and completing the current FLASH erase operation; determining whether all FLASH erase operations have been completed. If not all FLASH erase operations have been completed, switching the address to the base address of the next FLASH erase until all FLASH erase operations are completed in the cycle.

[0008] In some optional embodiments, the read interface is implemented by the following steps: obtaining the base address and length of the FLASH read; calculating the chip select space to which the FLASH address belongs; setting the FLASH chip select instruction and the FLASH read instruction in the command register, and setting the base address of this FLASH read in the address register; reading 8 bytes of data length each time, and concatenating the high 32-bit data and the low 32-bit data; determining whether all FLASH read operations have been completed. If not, the base address of the FLASH read is offset backward by 8 bytes until all FLASH read operations are completed in the cycle.

[0009] In some optional embodiments, the programming interface is implemented through the following steps: obtaining the base address and length of FLASH programming; calculating the chip select space to which the FLASH address belongs; completing the FLASH erase operation; setting the FLASH chip select instruction and the FLASH write enable instruction in the command register, and setting the base address of this FLASH programming in the address register; splitting the 64-bit data into high 32-bit data and low 32-bit data, and writing 8 bytes of data length each time; determining whether all FLASH programming operations have been completed. If not, the base address of the FLASH programming is offset backward by 8 bytes until all FLASH programming operations are completed in the cycle.

[0010] The embodiment of the present application proposes a method for reading and writing access to the FLASH extension space based on the domestic Feiteng E2000Q processor, which starts from both hardware and software aspects to realize the read and write access function of the FLASH extension space of the domestic Feiteng E2000Q processor. In terms of hardware, multiple FLASH chips are respectively mounted in different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor, a clock signal is provided to each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through the FPGA, and a standard library is formed. In terms of software, when FLASH erasing, reading, or programming operations are required, the selection of different FLASH chips is realized by passing the FLASH chip select parameters to the chip select register of the QSPI controller, the read and write access operation is realized by passing the FLASH address to the address register of the QSPI controller, and the read and write operations of the high-order data and the low-order data in the same address space are realized by data splicing and parsing. It effectively improves the flexibility of the domestically produced Feiteng E2000Q processor in terms of application solidification and FLASH address space allocation. At the same time, through standardized and universal design, this function can be applied to the FLASH expansion space function implementation of other Feiteng series processors, and has strong universality.

[0011] In a second aspect, an embodiment of the present application proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements a FLASH extended space read and write access method based on a domestically produced Feiteng E2000Q processor as described in the first aspect above.

[0012] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 It is a flowchart of a FLASH extension space read and write access method based on a domestic Feiteng E2000Q processor provided in an embodiment of the present application;

[0015] Figure 2It is a schematic diagram of a hardware circuit design in a FLASH extended space read and write access method based on a domestic Feiteng E2000Q processor provided in an embodiment of the present application;

[0016] Figure 3 is a flowchart of an implementation of an erase interface provided in one embodiment of the present application;

[0017] Figure 4 is a flowchart of an implementation of a read interface provided in an embodiment of the present application;

[0018] Figure 5 It is an implementation flow chart of the programming interface provided in one embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the various embodiments of the present application, many technical details are proposed in order to make the reader better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is only for the convenience of description, and the specific implementation mode of the present application should not constitute any limitation. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0020] An embodiment of the present application proposes a FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor. The implementation details of the FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor proposed in this embodiment are specifically described below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for the implementation of this solution.

[0021] The specific process of the FLASH expansion space read and write access method based on the domestic Feiteng E2000Q processor proposed in this embodiment can be as follows: Figure 1 As shown, including:

[0022] Step 101, in terms of hardware, multiple FLASH chips are respectively mounted in different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor, a clock signal is provided to each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through the FPGA, and a standard library is formed.

[0023] In the specific implementation, the improvement of the read and write access of the FLASH extension space of the domestic Feiteng E2000Q processor consists of hardware improvements and software improvements. In terms of hardware, the QSPI controller of the domestic Feiteng E2000Q processor contains multiple chip select spaces, so multiple FLASH chips can be respectively mounted in different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor. Such a design meets the design requirements of the processor manual. In this circuit design, a clock signal is provided to each FLASH chip through the QSPI controller, and a reset signal is sent to each FLASH chip through the FPGA, and a standard library (circuit multiplexing module library) is formed for multiplexing in the design of other products.

[0024] In an example, Figure 2 As shown, two FLASH chips (FLASH1 and FLASH2) are respectively mounted in two different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor, FLASH1 is mounted in the CS0 chip select space of the QSPI controller, and FLASH2 is mounted in the CS1 chip select space of the QSPI controller. The clock signal NOR_QSPI_CLK is provided to each FLASH chip through the QSPI controller, and the reset signal FLASH_RESET_N is sent to each FLASH chip through the FPGA. The system power-on reset signal CPU_POR_N can also be sent to the domestic Feiteng E2000Q processor through the FPGA.

[0025] Step 102, in terms of software, when FLASH erasing, reading, or programming operations are required, different FLASH chips are selected by passing FLASH chip select parameters to the chip select register of the QSPI controller, read and write access operations are achieved by passing the FLASH address to the address register of the QSPI controller, and read and write operations on high-order data and low-order data in the same address space are achieved by data splicing and parsing.

[0026] In the specific implementation, in terms of software, when FLASH erasing, reading, or programming operations are required, the selection of different FLASH chips can be achieved by passing the FLASH chip select parameters to the chip select register of the QSPI controller, and the read and write access operations can be achieved by passing the FLASH address to the address register of the QSPI controller. The read and write operations of the high and low data in the same address space can be achieved through data splicing and parsing.

[0027] In an example, Figure 2As shown, two FLASH chips (FLASH1 and FLASH2) are respectively mounted in two different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor. FLASH1 is mounted in the CS0 chip select space of the QSPI controller, and FLASH2 is mounted in the CS1 chip select space of the QSPI controller. The chip select function can be realized by passing the FLASH chip select parameters to the chip select register of the QSPI controller. That is to say, if the FLASH chip select is set to point to CS0, FLASH1 can be erased, read, or programmed. If the FLASH chip select is set to point to CS1, FLASH2 can be erased, read, or programmed. Among them, NOR_QSPI_CS0 means setting the FLASH chip select to point to CS0, and NOR_QSPI_CS1 means setting the FLASH chip select to point to CS1.

[0028] It is worth noting that the programming operation can also be called a write operation.

[0029] In one example, the access interface of the FLASH expansion space of the domestic Feiteng E2000Q processor needs to be standardized and packaged, and after packaging, it will provide an erase interface, a read interface, and a programming interface. Standardized packaging of hardware circuit design and standardized packaging of software read and write access interfaces can form software and hardware design specifications.

[0030] In one example, the erasure interface is implemented by the following steps: Figure 3 As shown: first obtain the base address and length of the FLASH erase, then calculate the first address of the block area where the FLASH address is located, the number of erased blocks (64Kb bytes per block) and the chip select space to which it belongs, then set the FLASH chip select instruction and FLASH write enable instruction in the command register, set the FLASH chip select instruction and FLASH erase instruction in the command register, and set the base address of this FLASH erase in the address register. The FLASH chip select instruction selects the FLASH chip to be operated, and the base address of this FLASH erase can accurately find the location to be erased. At this point, the current FLASH erase operation can be executed and completed. After the current FLASH erase operation is completed, it is necessary to determine whether all FLASH erase operations have been completed. If all FLASH erase operations have not been completed, the address needs to be switched to the base address of the next FLASH erase, and the next FLASH erase operation is performed until the cycle completes all FLASH erase operations.

[0031] In one example, the read interface is implemented by the following steps: Figure 4As shown: First, the base address and length of the FLASH read must be obtained, and then the chip select space to which the FLASH address belongs must be calculated. Then, the FLASH chip select instruction and the FLASH read instruction are set in the command register, and the base address of this FLASH read is set in the address register. The FLASH chip select instruction selects the FLASH chip to be operated, and the base address of this FLASH read can accurately find the location to be read. At this point, the current FLASH read operation can be executed and completed, and the 8-byte data length is read each time, and the high 32-bit data and the low 32-bit data are spliced. After the current FLASH read operation is completed, it is necessary to determine whether all FLASH read operations have been completed. If not, the base address of the FLASH read is offset backward by 8 bytes, and the next FLASH read operation is performed until all FLASH read operations are completed in the cycle.

[0032] In one example, the programming interface is implemented by the following steps: Figure 5 As shown: First, you need to obtain the base address and length of FLASH programming, then calculate the chip select space to which the FLASH address belongs, and complete the FLASH erase operation, that is, erase first and then program. The erase process is not repeated here. After that, set the FLASH chip select instruction and FLASH write enable instruction in the command register, and set the base address of this FLASH programming in the address register. The FLASH chip select instruction selects the FLASH chip to be operated. The base address of this FLASH programming can accurately find the programming location. At this point, the current FLASH programming operation can be executed and completed, that is, the 64-bit data is split into high 32-bit data and low 32-bit data, and 8 bytes of data length are written each time. After the current FLASH programming operation is completed, it is necessary to determine whether all FLASH programming operations have been completed. If not, the base address of FLASH programming is offset backward by 8 bytes to facilitate the next FLASH programming operation until all FLASH programming operations are completed in a cycle.

[0033] This embodiment realizes the read and write access function of the FLASH expansion space of the domestic Feiteng E2000Q processor from the two aspects of hardware and software. In terms of hardware, multiple FLASH chips are respectively mounted in different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor, a clock signal is provided to each FLASH chip through the QSPI controller, a reset signal is sent to each FLASH chip through the FPGA, and a standard library is formed. In terms of software, when FLASH erasing, reading, or programming operations are required, the selection of different FLASH chips is realized by passing the FLASH chip select parameters to the chip select register of the QSPI controller, the read and write access operation is realized by passing the FLASH address to the address register of the QSPI controller, and the read and write operations of the high-order data and the low-order data in the same address space are realized by data splicing and parsing. It effectively improves the flexibility of the domestically produced Feiteng E2000Q processor in terms of application solidification and FLASH address space allocation. At the same time, through standardized and universal design, this function can be applied to the FLASH extension space function implementation of other Feiteng series processors, and even transplanted to the FLASH extension space function implementation of processors of other brands and specifications, with strong universality.

[0034] The step division of the above methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0035] Another embodiment of the present application proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement a FLASH extended space read and write access method based on a domestically produced Feiteng E2000Q processor as described in the above method embodiments.

[0036] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, ROM (Read-Only Memory), RAM (Random Access Memory), disk or optical disk and other media that can store program codes.

[0037] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A method for reading and writing FLASH extension space based on the domestic Feiteng E2000Q processor, characterized in that: include: In terms of hardware, multiple FLASH chips are respectively mounted in different chip select spaces of the QSPI controller of the domestic Feiteng E2000Q processor, and clock signals are provided to each FLASH chip through the QSPI controller, and reset signals are sent to each FLASH chip through the FPGA to form a standard library; In terms of software, when FLASH erasing, reading, or programming operations are required, the selection of different FLASH chips is achieved by passing the FLASH chip select parameters to the chip select register of the QSPI controller, and the read and write access operations are achieved by passing the FLASH address to the address register of the QSPI controller. The read and write operations of high and low order data in the same address space are achieved through data splicing and parsing.

2. According to claim 1, a FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor is characterized in that: The access interface of the FLASH expansion space of the domestically produced Feiteng E2000Q processor is standardized and packaged, including the erase interface, read interface and programming interface.

3. According to claim 2, the method for reading and writing FLASH extension space based on the domestic Feiteng E2000Q processor is characterized in that: The erasure interface is implemented by the following steps: Get the base address and length of FLASH erase; Calculate the first address of the block area where the FLASH address is located, the number of erased blocks and the chip select space to which it belongs; Set the FLASH chip select instruction and FLASH write enable instruction in the command register; Set the FLASH chip select instruction and FLASH erase instruction in the command register, and set the base address of this FLASH erase in the address register; Execute and complete the current FLASH erase operation; It is determined whether all FLASH erase operations have been completed. If not, the address is switched to the base address of the next FLASH erase until all FLASH erase operations are completed in a cycle.

4. According to claim 2, a FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor is characterized in that: The read interface is implemented by the following steps: Get the base address and length of FLASH read; Calculate the chip select space to which the FLASH address belongs; Set the FLASH chip select instruction and FLASH read instruction in the command register, and set the base address of this FLASH read in the address register; Each time, 8 bytes of data length is read, and the high 32-bit data and the low 32-bit data are concatenated; It is determined whether all FLASH read operations have been completed. If not, the base address of the FLASH read is shifted backward by 8 bytes until all FLASH read operations are completed in a loop.

5. According to claim 2, a FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor is characterized in that: The programming interface is implemented by the following steps: Get the base address and length of FLASH programming; Calculate the chip select space to which the FLASH address belongs; Complete the FLASH erase operation; Set the FLASH chip select instruction and FLASH write enable instruction in the command register, and set the base address of this FLASH programming in the address register; Split 64-bit data into high 32-bit data and low 32-bit data, and write 8 bytes of data each time; It is determined whether all FLASH programming operations have been completed. If not, the base address of the FLASH programming is shifted backward by 8 bytes until all FLASH programming operations are completed in a loop.

6. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the processor, a FLASH extended space read and write access method based on the domestic Feiteng E2000Q processor as described in any one of claims 1 to 5 is implemented.

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