Neural network training method and system for automatic circuit generation

Abstract

The invention relates to the technical field of electronic design automation, and discloses a neural network training method and system for automatic circuit generation, and the method comprises the steps: carrying out the preprocessing of initial circuit design data, obtaining target circuit design data, recognizing the module type of each circuit function module in the target circuit design data, and carrying out the recognition of the module type of each circuit function module; marking circuit function modules by using the module types, identifying module features corresponding to the circuit function modules, training the initial convolutional neural network by using the module features corresponding to the circuit function modules of the same module type, and obtaining a target convolutional neural network corresponding to each module type, and training the initial graph neural network according to the associated information to obtain a target graph neural network. The circuit design efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology, and in particular to a neural network training method and system for automatic circuit generation. Background Art

[0002] As the complexity of electronic systems continues to increase, there is an urgent need for more efficient circuit design methods. Artificial intelligence (AI) technology has great potential in analyzing circuit data and mining circuit design patterns, but AI has not yet been fully utilized to achieve automated circuit generation.

[0003] Currently, circuit design mainly relies on engineers to manually input design codes or construct circuit design logic through a graphical interface. This process requires engineers to have a deep understanding of the hardware architecture of FPGA (field programmable gate array) and HDL (hardware description language), and it often takes a lot of time to debug and optimize when designing complex circuits, resulting in a long design cycle and low efficiency. Summary of the invention

[0004] The present invention provides a neural network training method and system for automatic circuit generation, the main purpose of which is to improve the efficiency of circuit design.

[0005] To achieve the above object, the present invention provides a neural network training method for automatic circuit generation, comprising: Acquiring initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; Preprocessing the initial circuit design data to obtain target circuit design data; Identifying a module type of each circuit function module in the target circuit design data, and marking the circuit function module with the module type; Identify module features corresponding to the circuit function module, wherein the module features include: logic structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; The pre-built initial convolutional neural network is trained using the module features corresponding to the circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, wherein the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The pre-constructed initial graph neural network is trained according to the association information to obtain a target graph neural network, thereby completing the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

[0006] Optionally, preprocessing the initial circuit design data to obtain target circuit design data includes: Performing data integrity detection on the initial circuit design data to obtain complete detection circuit data; Performing logic verification on the complete detection circuit data to obtain logic verification circuit data; Identifying abnormal data in the logic verification circuit data, removing the abnormal data, and obtaining normal circuit data; Identifying logic gate data and module connection data in the normal circuit data, and performing standard processing on the logic gate data and module connection data to obtain connection standard circuit data; Identifying performance parameters in the connection standard circuit data, and standardizing the performance parameters to obtain performance standard circuit data; The connection standard circuit data and the performance standard circuit data are subjected to feature fusion and weighting processing to obtain target circuit design data.

[0007] Optionally, the method of training a pre-built initial convolutional neural network using module features corresponding to circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type includes: Summarizing module features corresponding to circuit function modules of the same module type, identifying data complexity of the summarized module features, and adjusting the size of the convolution kernel in the initial convolutional neural network according to the data complexity to obtain an original convolutional neural network; Using a preset hybrid pooling method to perform data dimensionality reduction on the aggregated module features to obtain a reduced-dimensional module feature set; The original convolutional neural network is trained using the dimension reduction module feature set to obtain a target convolutional neural network corresponding to the module type.

[0008] Optionally, the using the dimension reduction module feature set to train the original convolutional neural network to obtain a target convolutional neural network corresponding to the module type includes: Extracting dimension reduction module features in the dimension reduction module feature set in sequence, inputting the dimension reduction module features into the original convolutional neural network, and outputting a circuit structure; Using a pre-built EDA tool to identify performance indicators corresponding to the circuit structure, wherein the performance indicators include: timing performance, power consumption performance, and resource utilization; Calculating a multi-objective loss function value based on a preset target performance indicator and a performance indicator corresponding to the circuit structure, and adjusting parameters of the original convolutional neural network using a pre-built gradient descent algorithm according to the multi-objective loss function value to obtain an iterative convolutional neural network; Inputting the pre-constructed verification set into the iterative convolutional neural network, and outputting the circuit structure after the iteration; Using a pre-built EDA tool to identify performance indicators corresponding to the iterated circuit structure; Determining whether the performance index corresponding to the iterated circuit structure meets the preset verification standard; If the verification standard is not met, the performance indicator based on the preset target performance indicator and the circuit structure is returned to calculate the multi-objective loss function value, and the parameters of the original convolutional neural network are adjusted using a pre-built gradient descent algorithm according to the multi-objective loss function value to obtain the step of iterative convolutional neural network; If the verification criteria are met, the target convolutional neural network is obtained.

[0009] Optionally, the training of the pre-constructed initial graph neural network according to the association information to obtain a target graph neural network includes: Standardizing the associated information to obtain standardized module data; The initial graph neural network is trained according to the standardized module data to obtain a target graph neural network.

[0010] Optionally, the standardized module data includes connection relationships of circuit function modules, communication protocol types, module characteristics, data flow directions and timing relationships; Before training the pre-constructed initial graph neural network according to the association information, the method further includes: Using the communication protocol type and module characteristics as node characteristics of the circuit function module; Taking the data flow direction and time sequence relationship as edge features; The circuit function modules are used as nodes, and an initial graph neural network is constructed according to the nodes, node features and edge features.

[0011] Optionally, the training of the initial graph neural network according to the standardized module data to obtain a target graph neural network includes: Iteratively training the initial graph neural network using the power consumption characteristics, delay time, and resource utilization characteristics to obtain an iterative graph neural network; Identifying model performance of the iterative graph neural network using a pre-built EDA tool; Determining whether the model performance meets the preset performance standard; If the model performance does not meet the performance standard, returning to the above step of iteratively training the initial graph neural network using the power consumption characteristics, delay time, and resource utilization characteristics; If the model performance meets the performance criteria, the target graph neural network is obtained.

[0012] Optionally, the identifying the model performance of the iterative graph neural network using a pre-built EDA tool includes: The EDA tool is used to identify the model performance of the iterative graph neural network based on preset functional indicators, timing indicators, power consumption indicators and resource usage indicators.

[0013] To achieve the above object, the present invention also provides a neural network training system for automatic circuit generation, comprising: A circuit marking module is used to obtain initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; preprocess the initial circuit design data to obtain target circuit design data; identify the module type of each circuit function module in the target circuit design data, and mark the circuit function module using the module type; A module feature identification module, used to identify module features corresponding to the circuit function module, wherein the module features include: logical structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; An initial convolutional neural network training module is used to train a pre-built initial convolutional neural network using module features corresponding to circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, wherein the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The initial graph neural network training module is used to train the pre-constructed initial graph neural network according to the association information to obtain the target graph neural network, and complete the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

[0014] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising: A memory storing at least one instruction; and a processor executing the instruction stored in the memory to implement the neural network training method for automatic circuit generation as described above.

[0015] In order to solve the above problems, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned neural network training method for automatic circuit generation.

[0016] The present invention is to solve the problem described in the background technology. The present invention first obtains initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules. Since the initial circuit design data may contain non-standard data, it is necessary to pre-process the initial circuit design data to obtain target circuit design data. Since different circuit function modules have different module types, and the initial convolutional neural network is trained based on the module type, it is necessary to identify the module type of each circuit function module in the target circuit design data, and then use the module type to mark the circuit function module. At this time, the target circuit design data can be identified. The module features corresponding to the circuit function modules are obtained, wherein the module features include: logical structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features. The module features corresponding to the circuit function modules of the same module type are then used to train the pre-constructed initial convolutional neural network to obtain the target convolutional neural network corresponding to each module type. The target convolutional neural network is used to generate the circuit corresponding to the circuit function module according to user needs. Finally, the pre-constructed initial graph neural network is trained according to the association information to obtain the target graph neural network, and the neural network training for automatic circuit generation is completed. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit. Therefore, the present invention can improve the efficiency of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a flow chart of a neural network training method for automatic circuit generation provided by an embodiment of the present invention; Figure 2 A functional module diagram of a neural network training system for automatic circuit generation provided by one embodiment of the present invention; Figure 3 A schematic diagram of the structure of an electronic device for implementing the neural network training method for automatic circuit generation provided by one embodiment of the present invention.

[0018] Description of reference numerals: 1. Electronic device; 10. Processor; 11. Memory; 12. Bus; 100. Neural network training system for automatic circuit generation; 101. Circuit annotation module; 102. Module feature recognition module; 103. Initial convolutional neural network training module; 104. Initial graph neural network training module.

[0019] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0021] The embodiment of the present application provides a neural network training method for automatic circuit generation. The execution subject of the neural network training method for automatic circuit generation includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the neural network training method for automatic circuit generation can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0022] Reference Figure 1 FIG. 1 is a flow chart of a neural network training method for automatic circuit generation provided by an embodiment of the present invention. In this embodiment, the neural network training method for automatic circuit generation includes: S1. Acquire initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules.

[0023] It can be explained that the initial circuit design data includes a large amount of FPGA circuit design data, including different types of circuit functional modules (for example: arithmetic logic unit, storage unit, communication interface, etc.) and their corresponding performance parameters, related information (for example: design constraints, etc.).

[0024] S2. Preprocess the initial circuit design data to obtain target circuit design data.

[0025] In an embodiment of the present invention, the preprocessing of the initial circuit design data to obtain target circuit design data includes: Performing data integrity detection on the initial circuit design data to obtain complete detection circuit data; Performing logic verification on the complete detection circuit data to obtain logic verification circuit data; Identifying abnormal data in the logic verification circuit data, removing the abnormal data, and obtaining normal circuit data; Identifying logic gate data and module connection data in the normal circuit data, and performing standard processing on the logic gate data and module connection data to obtain connection standard circuit data; Identifying performance parameters in the connection standard circuit data, and standardizing the performance parameters to obtain performance standard circuit data; The connection standard circuit data and the performance standard circuit data are subjected to feature fusion and weighting processing to obtain target circuit design data.

[0026] Furthermore, the data integrity check refers to checking whether the initial circuit design data meets the preset data standards, for example: checking whether the initial circuit design data meets the preset format standards (that is, whether the initial circuit design data is a Verilog, JSON, CSV, XML format file), verifying the connection relationship between circuit function modules (ensuring that the output and input bit widths are consistent), checking whether the circuit function is reasonable, whether the state number of the control module matches the logic description, whether the protocol settings of the communication module meet the standards, and checking whether the performance parameters (clock frequency, delay time, power consumption parameters, etc.) are within a reasonable range.

[0027] Explainably, the logic verification refers to verifying whether the circuit logic of the complete detection circuit data is qualified, for example: whether the signal flows in the expected direction from the source module to the target module, whether the timing relationship of the circuit function module is qualified (ensuring that there will be no competition or delay exceeding the design indicators during data transmission), and whether the input and output of the circuit function module meet the design constraints.

[0028] It should be understood that the abnormal data refers to the data of the circuit module function description of the circuit function module that is inconsistent with the actual operation and the design data of the same module that is repeatedly recorded. The standardization process refers to the Min-Max standardization of logic gate data, module connection data, etc., and scaling the characteristic values ​​to [0, 1] to ensure that the comparison between different circuit function modules is consistent. The performance parameters can be: clock frequency, power consumption, delay time, etc. In the process of standardizing the performance parameters, each performance parameter needs to be converted into a form with a mean of 0 and a standard deviation of 1 to avoid deviations in the initial convolutional neural network training process due to large dimensional differences in different performance parameters. Finally, the connection standard circuit data and the performance standard circuit data are subjected to feature fusion and weighted processing, and multi-modal features are combined to obtain the target circuit design data.

[0029] S3. Identify the module type of each circuit function module in the target circuit design data, and use the module type to label the circuit function module.

[0030] Furthermore, the module type can be a calculation type (for example: arithmetic logic unit, multiplier, etc.), a storage type (for example: register, RAM, ROM, etc.), a communication type (for example: UART, SPI, Ethernet interface, etc.), a control type (for example: state machine, controller, etc.) and other special function types (for example: encryption module, digital signal processing module, etc.).

[0031] S4. Identify module features corresponding to the circuit function module, wherein the module features include: logical structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features.

[0032] It is understandable that the logical structure features include: the type, quantity and connection mode of the logic gates inside the logic. For example, a computing circuit function module may contain a specific number of AND gates, OR gates and XOR gates, and their connection forms a logical structure that implements a specific computing function. The input and output features include: the number of input and output ports of the circuit function module, the data bit width, the signal type (such as digital signal, analog signal) and the logical relationship between the input and output ports. For example, the input of a communication interface module may be data in a specific protocol format, and the output is data that conforms to another protocol format. The data bit width and logical relationship of its input and output ports are important features of the module. The performance features include the running speed of the circuit function module (measured in clock cycles), etc. These performance features reflect the performance of the circuit function module in actual operation, which is crucial for classification and subsequent design generation. The resource utilization features include the type and quantity of resources occupied in the FPGA chip, including: logic units (LUTs), triggers, wiring resources, etc. Different types of circuit function modules have obvious differences in resource utilization. For example, storage modules may occupy more storage resources, while computing modules mainly consume logic resources.

[0033] S5. Use the module features corresponding to the circuit function modules of the same module type to train the pre-constructed initial convolutional neural network to obtain the target convolutional neural network corresponding to each module type, and the target convolutional neural network is used to generate the circuit corresponding to the circuit function module according to user needs.

[0034] In an embodiment of the present invention, the module features corresponding to the circuit function modules of the same module type are used to train the pre-constructed initial convolutional neural network to obtain the target convolutional neural network corresponding to each module type, including: Summarizing module features corresponding to circuit function modules of the same module type, identifying data complexity of the summarized module features, and adjusting the size of the convolution kernel in the initial convolutional neural network according to the data complexity to obtain an original convolutional neural network; Using a preset hybrid pooling method to perform data dimensionality reduction on the aggregated module features to obtain a reduced-dimensional module feature set; The original convolutional neural network is trained using the dimension reduction module feature set to obtain a target convolutional neural network corresponding to the module type.

[0035] Furthermore, the data complexity refers to the connection complexity of the FPGA module, the hybrid pooling method refers to the method of combining maximum pooling with average pooling, and the dimension reduction module feature set refers to the set of dimension reduction module features of each circuit function module.

[0036] In an embodiment of the present invention, the method of training the original convolutional neural network using the dimension reduction module feature set to obtain a target convolutional neural network corresponding to the module type includes: Extracting dimension reduction module features in the dimension reduction module feature set in sequence, inputting the dimension reduction module features into the original convolutional neural network, and outputting a circuit structure; Using a pre-built EDA tool to identify performance indicators corresponding to the circuit structure, wherein the performance indicators include: timing performance, power consumption performance, and resource utilization; Calculating a multi-objective loss function value based on a preset target performance indicator and a performance indicator corresponding to the circuit structure, and adjusting parameters of the original convolutional neural network using a pre-built gradient descent algorithm according to the multi-objective loss function value to obtain an iterative convolutional neural network; Inputting the pre-constructed verification set into the iterative convolutional neural network, and outputting the circuit structure after the iteration; Using a pre-built EDA tool to identify performance indicators corresponding to the iterated circuit structure; Determining whether the performance index corresponding to the iterated circuit structure meets the preset verification standard; If the verification standard is not met, the performance indicator based on the preset target performance indicator and the circuit structure is returned to calculate the multi-objective loss function value, and the parameters of the original convolutional neural network are adjusted using a pre-built gradient descent algorithm according to the multi-objective loss function value to obtain the step of iterative convolutional neural network; If the verification criteria are met, the target convolutional neural network is obtained.

[0037] Furthermore, the circuit structure refers to the circuit structure predicted by the original convolutional neural network based on the dimension reduction module characteristics. The circuit structure is represented in the form of a hardware description language or a logical topology diagram, including the connection relationship between circuit functional modules, resource allocation and timing information, etc. The performance indicators of the circuit structure can be identified using the EDA tool. The multi-objective loss function value includes: the deviation between the clock constraint in the dimension reduction module characteristics and the circuit structure, the deviation between the power consumption in the dimension reduction module characteristics and the power consumption performance of the circuit structure, the deviation between the resource utilization in the dimension reduction module characteristics and the resource utilization of the performance indicators, etc.

[0038] It is understandable that when adjusting parameters, the gradient descent algorithm and the multi-objective loss function value can be used to adjust the convolution kernel weights, bias terms, etc. of the original convolutional neural network, and dynamically adjust the hyperparameters to accelerate the convergence process of the original convolutional neural network.

[0039] Furthermore, after obtaining the iterative convolutional neural network, its performance needs to be verified. If during the verification process, the performance of the iterative convolutional neural network does not meet the verification criteria, gradient optimization is continued to further adjust the parameters of the iterative convolutional neural network.

[0040] S6. Train the pre-constructed initial graph neural network according to the association information to obtain a target graph neural network, and complete the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

[0041] Interpretable, an initial graph neural network (GNN) is used to take circuit functional modules as nodes and the connection relationships between circuit functional modules (e.g., communication lines, data dependencies, etc.) as edges. The nodes of the initial graph neural network update the module features of the circuit functional modules, and the edges update the connection relationships between the circuit functional modules.

[0042] Furthermore, the association information is used as the input of the initial graph neural network, and the optimal circuit splicing method of the circuit functional module is learned through the minimum loss function. In the process of training the initial graph neural network, the model parameters of the initial graph neural network can be adjusted using the relevant verification set to improve the generalization ability of the initial graph neural network for splicing in different circuit design scenarios.

[0043] In an embodiment of the present invention, the pre-constructed initial graph neural network is trained according to the association information to obtain a target graph neural network, including: Standardizing the associated information to obtain standardized module data; The initial graph neural network is trained according to the standardized module data to obtain a target graph neural network.

[0044] It can be understood that the standardized module data refers to standardized FPGA circuit design data.

[0045] In the embodiment of the present invention, the standardized module data includes the connection relationship of the circuit function modules, the communication protocol type, the module characteristics, the data flow direction and the timing relationship; Before training the pre-constructed initial graph neural network according to the association information, the method further includes: Using the communication protocol type and module characteristics as node characteristics of the circuit function module; Taking the data flow direction and time sequence relationship as edge features; The circuit function modules are used as nodes, and an initial graph neural network is constructed according to the nodes, node features and edge features.

[0046] Furthermore, the connection relationship refers to a global topological relationship diagram between circuit functional modules, which is used to describe the connection mode and dependency relationship of circuit functional modules. The communication protocol type refers to a data transmission protocol, such as UART, SPI or a custom protocol. The data flow direction refers to the data flow path between circuit functional modules, including input-output relationship and multi-module cascade relationship. The timing relationship refers to the timing dependency between circuit functional modules, such as the clock synchronization mechanism for cross-module data transmission.

[0047] Understandably, it is necessary to convert the communication protocol type and data flow direction into a unified representation, quantify the timing relationship, and unify it into standardized numerical data.

[0048] In the embodiment of the present invention, the initial graph neural network is trained according to the standardized module data to obtain a target graph neural network, including: Iteratively training the initial graph neural network using the power consumption characteristics, delay time, and resource utilization characteristics to obtain an iterative graph neural network; Identifying model performance of the iterative graph neural network using a pre-built EDA tool; Determining whether the model performance meets the preset performance standard; If the model performance does not meet the performance standard, returning to the above step of iteratively training the initial graph neural network using the power consumption characteristics, delay time, and resource utilization characteristics; If the model performance meets the performance criteria, the target graph neural network is obtained.

[0049] It is understandable that the power consumption characteristics, delay time, and resource utilization characteristics are used as optimization consideration dimensions to iteratively train the initial graph neural network model.

[0050] In an embodiment of the present invention, the identifying the model performance of the iterative graph neural network using a pre-built EDA tool includes: The EDA tool is used to identify the model performance of the iterative graph neural network based on preset functional indicators, timing indicators, power consumption indicators and resource usage indicators.

[0051] In an embodiment of the present invention, in the process of training the initial graph neural network, firstly, splicing-related information such as the communication protocol type and timing relationship of the circuit functional module is extracted from the standardized module data, and then, a splicing model based on the initial graph neural network (GNN) is constructed to learn the optimal connection method and behavioral characteristics between the circuit functional modules. After completing the training of the initial graph neural network, the iterative graph neural network is verified and optimized in combination with EDA tools to ensure that the circuit design after splicing achieves the best results in terms of function, timing, power consumption characteristics and resource utilization characteristics, and finally a splicing model adapted to specific design scenarios is generated.

[0052] The present invention is to solve the problem described in the background technology. The present invention first obtains initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules. Since the initial circuit design data may contain non-standard data, it is necessary to pre-process the initial circuit design data to obtain target circuit design data. Since different circuit function modules have different module types, and the initial convolutional neural network is trained based on the module type, it is necessary to identify the module type of each circuit function module in the target circuit design data, and then use the module type to mark the circuit function module. At this time, the target circuit design data can be identified. The module features corresponding to the circuit function modules are obtained, wherein the module features include: logical structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features. The module features corresponding to the circuit function modules of the same module type are then used to train the pre-constructed initial convolutional neural network to obtain the target convolutional neural network corresponding to each module type. The target convolutional neural network is used to generate the circuit corresponding to the circuit function module according to user needs. Finally, the pre-constructed initial graph neural network is trained according to the association information to obtain the target graph neural network, and the neural network training for automatic circuit generation is completed. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit. Therefore, the present invention can improve the efficiency of circuit design.

[0053] like Figure 2 , which is a functional module diagram of a neural network training system for automatic circuit generation provided by one embodiment of the present invention.

[0054] The neural network training system 100 for automatic circuit generation of the present invention can be installed in an electronic device. According to the functions implemented, the neural network training system 100 for automatic circuit generation can include a circuit labeling module 101, a module feature recognition module 102, an initial convolutional neural network training module 103 and an initial graph neural network training module 104. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0055] The circuit labeling module 101 is used to obtain initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; preprocess the initial circuit design data to obtain target circuit design data; identify the module type of each circuit function module in the target circuit design data, and label the circuit function module using the module type; The module feature identification module 102 is used to identify the module features corresponding to the circuit function module, wherein the module features include: logical structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; The initial convolutional neural network training module 103 is used to train the pre-built initial convolutional neural network using the module features corresponding to the circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, and the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The initial graph neural network training module 104 is used to train the pre-constructed initial graph neural network according to the association information to obtain the target graph neural network, and complete the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

[0056] In detail, each module in the neural network training system 100 for automatic circuit generation in the embodiment of the present invention is used in the same manner as described above. Figure 1 The technical means are the same as the neural network training method for automated circuit generation described in, and can produce the same technical effects, so they will not be repeated here.

[0057] like Figure 3 , which is a schematic diagram of the structure of an electronic device for implementing a neural network training method for automatic circuit generation provided by an embodiment of the present invention.

[0058] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a neural network training method program for automated circuit generation.

[0059] The memory 11 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1. Further, the memory 11 also includes an internal storage unit of the electronic device 1 and an external storage device. The memory 11 can not only be used to store application software and various types of data installed in the electronic device 1, such as the code of the neural network training method program for automatic circuit generation, but also can be used to temporarily store data that has been output or is to be output.

[0060] The processor 10 may be composed of an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules (such as neural network training method programs for automatic circuit generation, etc.) stored in the memory 11, and calls data stored in the memory 11 to execute various functions of the electronic device 1 and process data.

[0061] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize connection and communication between the memory 11 and at least one processor 10, etc.

[0062] Figure 3 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0063] For example, although not shown, the electronic device 1 may also include a power source (such as a battery) for supplying power to various components. Preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that the power management device can realize functions such as charging management, discharging management, and power consumption management. The power source may also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0064] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0065] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0066] The neural network training method program for automatic circuit generation stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve: Acquiring initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; Preprocessing the initial circuit design data to obtain target circuit design data; Identifying a module type of each circuit function module in the target circuit design data, and marking the circuit function module with the module type; Identify module features corresponding to the circuit function module, wherein the module features include: logic structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; The pre-built initial convolutional neural network is trained using the module features corresponding to the circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, wherein the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The pre-constructed initial graph neural network is trained according to the association information to obtain a target graph neural network, thereby completing the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

[0067] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 3 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0068] Furthermore, if the module / unit integrated in the electronic device 1 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0069] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement: Acquiring initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; Preprocessing the initial circuit design data to obtain target circuit design data; Identifying a module type of each circuit function module in the target circuit design data, and marking the circuit function module with the module type; Identify module features corresponding to the circuit function module, wherein the module features include: logic structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; The pre-built initial convolutional neural network is trained using the module features corresponding to the circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, wherein the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The pre-constructed initial graph neural network is trained according to the association information to obtain a target graph neural network, thereby completing the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

[0070] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and actual implementation may have other division methods.

[0071] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0072] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0073] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A neural network training method for automated circuit generation, characterized in that: The method comprises: Acquiring initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; Preprocessing the initial circuit design data to obtain target circuit design data; Identifying a module type of each circuit function module in the target circuit design data, and marking the circuit function module with the module type; Identify module features corresponding to the circuit function module, wherein the module features include: logic structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; The pre-built initial convolutional neural network is trained using the module features corresponding to the circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, wherein the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The pre-constructed initial graph neural network is trained according to the association information to obtain a target graph neural network, thereby completing the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

2. The neural network training method for automatic circuit generation according to claim 1, characterized in that: The preprocessing of the initial circuit design data to obtain target circuit design data includes: Performing data integrity detection on the initial circuit design data to obtain complete detection circuit data; Performing logic verification on the complete detection circuit data to obtain logic verification circuit data; Identifying abnormal data in the logic verification circuit data, removing the abnormal data, and obtaining normal circuit data; Identifying logic gate data and module connection data in the normal circuit data, and performing standard processing on the logic gate data and module connection data to obtain connection standard circuit data; Identifying performance parameters in the connection standard circuit data, and standardizing the performance parameters to obtain performance standard circuit data; The connection standard circuit data and the performance standard circuit data are subjected to feature fusion and weighting processing to obtain target circuit design data.

3. The neural network training method for automatic circuit generation according to claim 1, characterized in that: The pre-built initial convolutional neural network is trained using the module features corresponding to the circuit function modules of the same module type to obtain the target convolutional neural network corresponding to each module type, including: Summarizing module features corresponding to circuit function modules of the same module type, identifying data complexity of the summarized module features, and adjusting the size of the convolution kernel in the initial convolutional neural network according to the data complexity to obtain an original convolutional neural network; Performing data dimensionality reduction on the aggregated module features using a preset hybrid pooling method to obtain a reduced-dimensional module feature set; The original convolutional neural network is trained using the dimension reduction module feature set to obtain a target convolutional neural network corresponding to the module type.

4. The neural network training method for automatic circuit generation according to claim 3, characterized in that: The method of training the original convolutional neural network using the dimension reduction module feature set to obtain a target convolutional neural network corresponding to the module type includes: Extracting dimension reduction module features in the dimension reduction module feature set in sequence, inputting the dimension reduction module features into the original convolutional neural network, and outputting a circuit structure; Using a pre-built EDA tool to identify performance indicators corresponding to the circuit structure, wherein the performance indicators include: timing performance, power consumption performance, and resource utilization; Calculating a multi-objective loss function value based on a preset target performance indicator and a performance indicator corresponding to the circuit structure, and adjusting parameters of the original convolutional neural network using a pre-built gradient descent algorithm according to the multi-objective loss function value to obtain an iterative convolutional neural network; Inputting the pre-constructed verification set into the iterative convolutional neural network, and outputting the circuit structure after the iteration; Using a pre-built EDA tool to identify performance indicators corresponding to the iterated circuit structure; Determining whether the performance index corresponding to the iterated circuit structure meets the preset verification standard; If the verification standard is not met, the performance indicator based on the preset target performance indicator and the circuit structure is returned to calculate the multi-objective loss function value, and the parameters of the original convolutional neural network are adjusted using a pre-built gradient descent algorithm according to the multi-objective loss function value to obtain the step of iterative convolutional neural network; If the verification criteria are met, the target convolutional neural network is obtained.

5. The neural network training method for automatic circuit generation according to claim 1, characterized in that: The step of training the pre-built initial graph neural network according to the association information to obtain a target graph neural network includes: Standardizing the associated information to obtain standardized module data; The initial graph neural network is trained according to the standardized module data to obtain a target graph neural network.

6. The neural network training method for automatic circuit generation according to claim 5, characterized in that: The standardized module data includes the connection relationship of the circuit function modules, the communication protocol type, the module characteristics, the data flow direction and the timing relationship; Before training the pre-constructed initial graph neural network according to the association information, the method further includes: Using the communication protocol type and module characteristics as node characteristics of the circuit function module; Taking the data flow direction and time sequence relationship as edge features; The circuit function modules are used as nodes, and an initial graph neural network is constructed according to the nodes, node features and edge features.

7. The neural network training method for automatic circuit generation according to claim 6, characterized in that: The step of training the initial graph neural network according to the standardized module data to obtain a target graph neural network includes: Iteratively training the initial graph neural network using the power consumption characteristics, delay time, and resource utilization characteristics to obtain an iterative graph neural network; Identifying model performance of the iterative graph neural network using a pre-built EDA tool; Determining whether the model performance meets the preset performance standard; If the model performance does not meet the performance standard, return to the above step of iteratively training the initial graph neural network using the power consumption characteristics, delay time, and resource utilization characteristics; If the model performance meets the performance criteria, the target graph neural network is obtained.

8. The neural network training method for automatic circuit generation according to claim 7, characterized in that: The using of a pre-built EDA tool to identify the model performance of the iterative graph neural network includes: The EDA tool is used to identify the model performance of the iterative graph neural network based on preset functional indicators, timing indicators, power consumption indicators and resource usage indicators.

9. A neural network training system for automated circuit generation, characterized in that: The system comprises: A circuit marking module is used to obtain initial circuit design data, wherein the initial circuit design data includes: a circuit function module set and performance parameters corresponding to the circuit function modules, and association information between associated circuit function modules; preprocess the initial circuit design data to obtain target circuit design data; identify the module type of each circuit function module in the target circuit design data, and mark the circuit function module using the module type; A module feature identification module, used to identify module features corresponding to the circuit function module, wherein the module features include: logical structure features, input and output features, performance features, power consumption features, delay time, and resource utilization features; An initial convolutional neural network training module is used to train a pre-built initial convolutional neural network using module features corresponding to circuit function modules of the same module type to obtain a target convolutional neural network corresponding to each module type, wherein the target convolutional neural network is used to generate a circuit corresponding to the circuit function module according to user requirements; The initial graph neural network training module is used to train the pre-constructed initial graph neural network according to the association information to obtain the target graph neural network, and complete the neural network training for automatic circuit generation. The target graph neural network is used to splice the circuits corresponding to the multiple circuit function modules to generate a complete circuit.

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