Pixel circuit, display panel, and display device

Abstract

The present invention discloses a pixel circuit, a display panel and a display device, which belong to the field of display technology. The pixel circuit includes: a driving module; a threshold compensation module, which is arranged in a first branch connected between the control end and the second end of the driving module, and the threshold compensation module is used to turn on or off according to a first scanning signal; a first initialization module, which is arranged in a second branch connected to the control end of the driving module, and the first initialization module is used to turn on or off according to the second scanning signal; a frequency control module, which is respectively connected to the first branch and the second branch, and receives a frequency control signal and a first scanning signal; the frequency control module is used to control the on and off of the first branch according to the frequency control signal and the first scanning signal, and to control the on and off of the second branch according to the frequency control signal, so as to control the refresh frequency of the pixel circuit. The embodiment of the present invention can realize pixel-level refresh frequency control, so that the display panel supports flexible partitioned frequency display function.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have become mainstream in consumer electronics, including mobile phones, televisions, laptops, and desktop computers, due to their advantages of high image quality, power efficiency, thinness, and wide application range. However, display panels in related technologies cannot achieve flexible, zone-based, or frequency-based display. Summary of the Invention

[0003] The present invention provides a pixel circuit, a display panel and a display device to realize pixel-level refresh frequency control, so that the display panel supports a flexible partitioned frequency display function.

[0004] In a first aspect, an embodiment of the present invention provides a pixel circuit, including:

[0005] Driver module;

[0006] a threshold compensation module, provided in a first branch connected between the control terminal and the second terminal of the driving module, the threshold compensation module being configured to be turned on or off according to a first scanning signal;

[0007] A first initialization module is provided in the second branch connected to the control end of the driving module, and the first initialization module is used to turn on or off according to the second scanning signal;

[0008] A frequency control module is connected to the first branch and the second branch respectively, and receives a frequency control signal and the first scanning signal; the frequency control module is used to control the on and off of the first branch according to the frequency control signal and the first scanning signal, and to control the on and off of the second branch according to the frequency control signal, so as to control the refresh frequency of the pixel circuit.

[0009] Optionally, the frequency control module includes:

[0010] A first switch unit is connected in series with the threshold compensation module in the first branch; the first switch unit is used to be turned on or off according to the voltage of its control terminal;

[0011] a second switch unit, connected in series with the first initialization module in the second branch, and a control end of the second switch unit receiving the frequency control signal; the second switch unit is configured to be turned on or off according to the frequency control signal;

[0012] a voltage control unit connected to the control end of the first switch unit and receiving the frequency control signal and the first scanning signal; the voltage control unit is used to control whether the frequency control signal is transmitted to the control end of the first switch unit according to the first scanning signal;

[0013] Preferably, one end of the second branch is connected to the control end of the driving module, and the other end of the second branch is connected to the initialization signal;

[0014] Preferably, the on-voltage of the first switch unit is the same as the on-voltage of the second switch unit; when the first scanning signal is the cut-off voltage of the threshold compensation module, the voltage control unit is controlled to transmit the frequency control signal to the control end of the first switch unit.

[0015] Optionally, in any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase that occur successively; in the first initialization phase, the second scanning signal is a turn-on voltage of the first initialization module; in the data writing phase, the first scanning signal is a turn-on voltage of the threshold compensation module;

[0016] In a display frame in which the pixel circuit performs data refresh, a period in which the frequency control signal maintains the on-voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase;

[0017] In a display frame in which the pixel circuit performs data retention, a period in which the frequency control signal maintains the cut-off voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase;

[0018] Preferably, in a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains the on-voltage of the second switch unit at least during a period from the start of the first initialization phase to the start of the data writing phase;

[0019] In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the second switch unit at least during a period from the start of the first initialization phase to the start of the data writing phase.

[0020] Optionally, the first switch unit includes: a first transistor connected in series with the threshold compensation module in the first branch, and a gate of the first transistor is connected to a control terminal of the first switch unit;

[0021] The second switch unit includes: a second transistor connected in series with the first initialization module in the second branch, and a gate of the second transistor is connected to the frequency control signal;

[0022] The voltage control unit includes: a third transistor, a gate of the third transistor is connected to the first scanning signal, a first electrode of the third transistor is connected to the frequency control signal, and a second electrode of the third transistor is connected to the control end of the first switch unit;

[0023] Preferably, the voltage control unit further includes: a first capacitor, a first end of the first capacitor is connected to the control end of the first switch unit, and a second end of the first capacitor is connected to a fixed voltage signal;

[0024] Preferably, the threshold compensation module includes: a fourth transistor connected in series with the first switch unit in the first branch, and a gate of the fourth transistor is connected to the first scanning signal;

[0025] The first initialization module includes: a fifth transistor connected in series with the second switch unit in the second branch, and a gate of the fifth transistor is connected to the second scanning signal;

[0026] Preferably, the first transistor and the second transistor have the same channel type, and the third transistor and the fourth transistor have different channel types;

[0027] Preferably, the channel types of the first transistor, the second transistor, the fourth transistor and the fifth transistor are all the same;

[0028] Preferably, the first transistor, the second transistor, the fourth transistor and the fifth transistor are all N-type transistors, and the third transistor is a P-type transistor.

[0029] Optionally, the driving module includes: a driving transistor, a gate of the driving transistor is connected to the control terminal of the driving module, a first electrode of the driving transistor is connected to the first terminal of the driving module, and a second electrode of the driving transistor is connected to the second terminal of the driving module;

[0030] Preferably, the pixel circuit further includes:

[0031] The data writing module includes a sixth transistor; the gate of the sixth transistor is connected to the third scanning signal, the first electrode of the sixth transistor is connected to the data signal, and the second electrode of the sixth transistor is connected to the first end of the driving module;

[0032] a light-emitting control module, comprising a seventh transistor and an eighth transistor; the gates of the seventh transistor and the eighth transistor are both connected to a light-emitting control signal, a first electrode of the seventh transistor is connected to a first power supply signal, a second electrode of the seventh transistor is connected to a first terminal of the driver module, a first electrode of the eighth transistor is connected to a second terminal of the driver module, a second electrode of the eighth transistor is connected to an anode of a light-emitting device, and a cathode of the light-emitting device is connected to a second power supply signal;

[0033] The second initialization module includes a ninth transistor; a gate of the ninth transistor is connected to the fourth scanning signal, a first electrode of the ninth transistor is connected to the initialization signal, and a second electrode of the ninth transistor is connected to the anode of the light-emitting device;

[0034] The storage module includes a storage capacitor; a first end of the storage capacitor is connected to the first power signal, and a second end of the storage capacitor is connected to the control end of the driving module;

[0035] Preferably, the frequency control module includes a first capacitor, and a second end of the first capacitor is connected to a fixed voltage signal; wherein the initialization signal, the first power signal or the second power signal is multiplexed into the fixed voltage signal.

[0036] In a second aspect, an embodiment of the present invention provides a display panel, comprising: a pixel circuit provided by any embodiment of the present invention;

[0037] Preferably, the frequency control module includes a first switch unit, a second switch unit and a voltage control unit; the display panel includes a plurality of pixel circuits arranged in an array; at least two pixel circuits in the same row share the same voltage control unit;

[0038] Preferably, the display panel includes a plurality of pixel units, each of the pixel units includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit share the same voltage control unit;

[0039] Preferably, the display panel further comprises: at least one frequency control signal line, at least one column of pixel circuits is connected to the same frequency control signal line, and the frequency control signal line is used to provide the frequency control signal to the connected pixel circuits;

[0040] Preferably, at least two pixel circuits in the same row are connected to the same frequency control signal line;

[0041] Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines;

[0042] Preferably, the display panel further comprises: a plurality of data lines connected to each column of pixel circuits in a one-to-one correspondence; the data lines and the frequency control signal lines extend in the same direction.

[0043] In a third aspect, an embodiment of the present invention provides a display device, including:

[0044] A display panel includes a plurality of pixel circuits and at least one frequency control signal line; the pixel circuits include: a driving module, a threshold compensation module, a first initialization module, and a frequency control module; the threshold compensation module is disposed in a first branch connected between a control terminal and a second terminal of the driving module; the first initialization module is disposed in a second branch connected to the control terminal of the driving module; the frequency control module is connected to the frequency control signal line corresponding to the pixel circuit, and is configured to control the on / off state of the first branch and the second branch according to a frequency control signal transmitted by the connected frequency control signal line, thereby controlling the refresh frequency of the pixel circuit;

[0045] A driving component is connected to each of the frequency control signal lines and is used to control the voltage of the frequency control signal transmitted by each of the frequency control signal lines according to the partition frequency information.

[0046] Optionally, the drive assembly includes:

[0047] A timing controller, configured to analyze the partition frequency information and generate a display control signal;

[0048] A driver chip connected to the timing controller;

[0049] The number of level conversion circuits is the same as the number of frequency control signal lines, and each level conversion circuit is connected to each frequency control signal line in a one-to-one correspondence; each level conversion circuit receives a first level signal and a second level signal, and is connected to the driver chip; the driver chip is used to control each level conversion circuit to output the first level signal or the second level signal according to the display control signal;

[0050] Preferably, the display panel includes a plurality of pixel circuits arranged in an array; the display panel further includes: a gate driving circuit connected to the timing controller and each pixel circuit respectively; the timing controller is further configured to control the output of the gate driving circuit so that each row of pixel circuits enters a scanning phase row by row;

[0051] The driver chip is used to control the voltage of the frequency control signal received by each pixel circuit in a row according to the display control signal during the scanning phase of each row of pixel circuits;

[0052] Preferably, the display panel includes a plurality of frequency control signal lines, one of which is connected to at least one column of pixel circuits; the display control signal includes a refresh control signal for each row of pixel circuits, and the timing controller serially outputs the refresh control signal for each row of pixel circuits to the driver chip; during a scanning phase of any row of pixel circuits, the driver chip controls each level conversion circuit to transmit a frequency control signal in parallel to each frequency control signal line according to the refresh control signal for the pixel circuit in that row;

[0053] Preferably, the display panel further comprises: a plurality of data lines connected to each column of pixel circuits in a one-to-one correspondence; the driving chip is also connected to each of the data lines; and the timing controller is further used to control the driving chip to transmit a corresponding data signal to each of the data lines;

[0054] Preferably, the data line and the frequency control signal line extend in the same direction;

[0055] Preferably, at least two pixel circuits in the same row are connected to the same frequency control signal line;

[0056] Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines;

[0057] Preferably, the display device further comprises: a host connected to the driving component and configured to provide the partition frequency information;

[0058] Preferably, the partition frequency information includes: the number, position and refresh frequency of each display partition in the display area of ​​the display panel;

[0059] Preferably, the display panel includes a lower frame area and a display area which are sequentially away from the driving chip, the level conversion circuit is arranged in the lower frame area, and the pixel circuit is arranged in the display area;

[0060] Alternatively, the level conversion circuit is integrated into the driver chip;

[0061] Alternatively, the level conversion circuit is arranged in a circuit board for carrying the timing controller.

[0062] Optionally, the pixel circuit is the pixel circuit provided by any embodiment in the first aspect.

[0063] Optionally, the frequency control module includes:

[0064] a third switch unit, connected in series with the threshold compensation module in the first branch, and a control terminal of the third switch unit is connected to the frequency control signal;

[0065] a fourth switch unit, connected in series with the first initialization module in the second branch, and a control end of the second switch unit is connected to the frequency control signal;

[0066] Preferably, the turn-on voltage of the third switch unit is the same as the turn-on voltage of the fourth switch unit;

[0067] Preferably, in any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase that occur successively; in the first initialization phase, the first initialization module is turned on; in the data writing phase, the threshold compensation module is turned on;

[0068] In a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit at least in the first initialization phase and the data writing phase;

[0069] In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit at least in the first initialization phase and the data writing phase;

[0070] Preferably, in a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains the on-voltage of the third switch unit in the scanning phase;

[0071] In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit in the scanning phase;

[0072] Preferably, the third switch unit includes: a tenth transistor connected in series with the threshold compensation module in the first branch, and a gate of the tenth transistor is connected to the frequency control signal;

[0073] The fourth switch unit includes: an eleventh transistor connected in series with the first initialization module in the second branch, and a gate of the eleventh transistor is connected to the frequency control signal;

[0074] Preferably, the tenth transistor and the eleventh transistor have the same channel type.

[0075] In the pixel circuit provided by an embodiment of the present invention, a frequency control module is provided to control the on / off switching of the first branch and the second branch. During a hold frame, the frequency control module controls the disconnection of the first branch and the second branch, allowing the threshold compensation module and the first initialization module to be turned on. Thus, the first scan signal and the second scan signal can maintain the same waveforms during the hold frame as during the display frame. Therefore, in this embodiment of the present invention, there is no need to redesign the gate drive circuit for providing the scan signals. Furthermore, by providing the frequency control module, pixel-level refresh frequency adjustment can be achieved, allowing the partition positions of display partitions with different refresh frequencies in the display panel to be arbitrarily adjusted as needed, enabling the display panel to support flexible partitioned and frequency-scaling display capabilities.

[0076] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0078] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0079] Figure 2 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0080] Figure 3 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0081] Figure 4 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0082] Figure 5 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0083] Figure 6 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0084] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0085] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0086] Figure 9 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0087] Figure 10 This is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0088] Figure 11 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0089] Figure 12 This is a schematic diagram of a display partition structure of a display panel provided by an embodiment of the present invention;

[0090] Figure 13 This is a schematic diagram of the refresh state of each display frame of a display panel in a display cycle provided by an embodiment of the present invention;

[0091] Figure 14 This is a schematic diagram of a driving timing sequence of a display panel provided by an embodiment of the present invention;

[0092] Figure 15 is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0093] Figure 16 This is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0094] Figure 17 This is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0095] Figure 18 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0096] Figure 19 is a structural diagram of another display panel provided by an embodiment of the present invention;

[0097] Figure 20 This is a schematic structural diagram of a voltage control unit shared by two pixel circuits provided by an embodiment of the present invention;

[0098] Figure 21is a schematic structural diagram of a display device provided by an embodiment of the present invention;

[0099] Figure 22 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0100] Figure 23 is a schematic structural diagram of another display device provided by an embodiment of the present invention;

[0101] Figure 24 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0102] Figure 25 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0103] Figure 26 This is a schematic diagram of control signals of a display panel in different time periods in a frame provided by an embodiment of the present invention;

[0104] Figure 27 This is a schematic diagram of control signals of another display panel in different time periods in a frame provided by an embodiment of the present invention;

[0105] Figure 28 This is another schematic diagram of control signals of a display panel in different time periods in a frame provided by an embodiment of the present invention;

[0106] Figure 29 1 is a timing diagram of a frequency control signal provided by an embodiment of the present invention;

[0107] Figure 30 This is a structural diagram of another pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0108] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0109] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0110] As pointed out in the background art, the display panel in the related art cannot achieve flexible partitioned frequency display, mainly for the following reasons: in the display panel, pixels are arranged in an array, and the display screen usually adopts a row-by-row scanning refresh method. In the related art, in order to realize the display of multiple display areas of the display panel at different refresh frequencies, the gate drive circuit (GIP) is usually improved, specifically: the signals transmitted row by row between each GIP are transmitted normally and are not controlled by the partition signal; but a control switch is added to the output stage of each row of GIP, and the control switch is controlled by the partition signal, thereby controlling the frequency of the gate drive signal of each row to achieve partitioned multi-frequency. Since the pixels in the same row of the display panel are controlled by the same gate drive signal, the above scheme can only achieve frequency division display by row partition, and cannot achieve column partition or other more flexible partitioned frequency division display.

[0111] To solve the above problem, an embodiment of the present invention provides a pixel circuit. Figure 1 Schematic diagram of a pixel circuit according to an embodiment of the present invention. Figure 1 The pixel circuit includes: a driving module 10, a threshold compensation module 20, a first initialization module 30 and a frequency control module 40.

[0112] The threshold compensation module 20 is disposed in the first branch connected between the control terminal G and the second terminal D of the driving module 10, and the control terminal of the threshold compensation module 20 is connected to the first scanning signal S1; the threshold compensation module 20 is used to turn on or off according to the first scanning signal S1. The first initialization module 30 is disposed in the second branch connected to the control terminal G of the driving module 10, and the control terminal of the first initialization module 30 is connected to the second scanning signal S2; the first initialization module 30 is used to turn on or off according to the second scanning signal S2. The frequency control module 40 is connected to the first branch and the second branch respectively, and is connected to the frequency control signal CCL and the first scanning signal S1; the frequency control module 40 is used to control the on and off of the first branch according to the frequency control signal CCL and the first scanning signal S1, and to control the on and off of the second branch according to the frequency control signal CCL, so as to control the refresh frequency of the pixel circuit.

[0113] Exemplarily, the driver module 10 generates a driving current based on the voltage at its control terminal G to drive the light-emitting device OLED to emit light. The control terminal G of the driver module 10 is connected to two branches. The first branch is connected between the control terminal G and the second terminal D of the driver module 10. When the first branch is conductive, the control terminal G and the second terminal D of the driver module 10 are connected, forming a diode connection. This allows a voltage related to the voltage connected to the first terminal S of the driver module 10 to be transmitted to the control terminal of the driver module 10. The second branch, for example, has one end connected to the control terminal G of the driver module 10 and the other end connected to the initialization signal VREF. When the second branch is conductive, the initialization signal can be transmitted to the control terminal G of the driver module 10 to reset the control terminal G.

[0114] The scanning phase of each display frame of the pixel circuit may include a first initialization phase and a data writing phase, which occur sequentially. During the first initialization phase, the second branch may be controlled to be conductive to control whether the initialization signal VREF is transmitted to the control terminal G of the driver module 10. During the data writing phase, the first branch may be controlled to be conductive to control whether the voltage associated with the data signal Vdata is transmitted to the control terminal G of the driver module 10. In display frames where the pixel circuit performs data refresh, i.e., write frames, the second branch must be controlled to be conductive in the first initialization phase to reset the control terminal G of the driver module 10. During the data writing phase, the first branch must be controlled to be conductive to write data to the control terminal G of the driver module 10, thereby completing the data refresh. During display frames where the pixel circuit performs data retention, i.e., hold frames, the second branch must be controlled to be disconnected in the first initialization phase, and the first branch must be controlled to be disconnected in the data writing phase, so that the voltage at the control terminal G of the driver module 10 does not change during the display frame, thereby achieving data retention.

[0115] Exemplarily, the refresh frequency control principle of the pixel circuit is:

[0116] In the display frame (writing frame) in which the pixel circuit refreshes data, in the first initialization stage, the frequency control signal CCL controls the frequency control module 40 to be connected to the structure in the second branch, so that the on / off state of the second branch is controlled by the on / off state of the first initialization module 30. At this time, the second scanning signal S2 controls the first initialization module 30 to be turned on, so that the second branch can be turned on, thereby resetting the control terminal G of the driving module 10. In the data writing stage, the frequency control signal CCL cooperates with the first scanning signal S1 to control the frequency control module 40 to be connected to the structure in the first branch, so that the on / off state of the first branch is controlled by the on / off state of the threshold compensation module 20. At this time, the first scanning signal S1 controls the threshold compensation module 20 to be turned on, thereby turning on the first branch, thereby writing data to the control terminal G of the driving module 10.

[0117] In the display frame (holding frame) in which the pixel circuit holds data, in the first initialization stage, the frequency control signal CCL controls the frequency control module 40 to be connected to the structure in the second branch to be disconnected, so that the second branch is directly disconnected. At this time, regardless of whether the first initialization module 30 is turned on, the second branch remains disconnected, and the initialization signal VREF cannot be transmitted to the control terminal G of the driving module 10. Therefore, in this stage, the second scanning signal S2 can control the first initialization module 30 to be turned on; in the data writing stage, the frequency control signal CCL cooperates with the first scanning signal S1 to control the frequency control module 40 to be connected to the structure in the first branch to be disconnected, so that the first branch is directly disconnected. At this time, regardless of whether the threshold compensation module 20 is turned on, the first branch remains disconnected, and data cannot be written to the control terminal G of the driving module 10. Therefore, in this stage, the first scanning signal S1 can control the threshold compensation module 20 to be turned on.

[0118] For example, the frequency control signal CCL can directly control the on / off state of the structure connected to the second branch of the frequency control module 40. The first scan signal S1 can control whether the frequency control signal CCL is transmitted to the internal node of the frequency control module 40, thereby controlling the on / off state of the structure connected to the first branch of the frequency control module 40. When the first scan signal S1 controls the frequency control signal CCL to be transmitted to the internal node of the frequency control module 40, the voltage of the internal node is equal to the voltage of the frequency control signal CCL. When the first scan signal S1 controls the frequency control signal CCL to be unable to be transmitted to the internal node of the frequency control module 40, the voltage of the internal node is maintained and does not change with the voltage of the frequency control signal CCL. In this way, by setting the internal node of the frequency control module 40 to have a stage where the voltage does not change with the frequency control signal CCL, the refresh frequency control of the pixel circuit can be made more flexible. For example, during the data writing phase of the hold frame, the first scan signal S1 can be used to control the internal nodes of the frequency control module 40 to maintain voltage. Thus, the frequency control signal CCL can undergo voltage jumps during the data writing phase without affecting the on / off state of the structure connected to the first branch by the frequency control module 40, thereby allowing the first branch to remain disconnected. Furthermore, during the data writing phase, since the second scan signal S2 has already controlled the first initialization module 30 to shut down, the second branch is already disconnected. Even if the frequency control signal CCL undergoes a jump, causing the on / off state of the structure connected to the second branch by the frequency control module 40 to change, it will not affect the on / off state of the second branch, and the second branch will remain disconnected. Thus, compared to directly controlling the on / off state of the structure connected to the first and second branches by the frequency control signal CCL, the voltage jump of the frequency control signal CCL can be made more flexible, allowing the frequency control signal CCL to undergo voltage jumps during the data writing phase. Especially for the case where a column of pixel circuits is connected to the same frequency control signal CCL, if the pixel circuits belonging to the current row need to maintain data and the pixel circuits belonging to the next row need to refresh data, the frequency control signal CCL can be controlled to perform a voltage jump during the data writing phase of the current row, without having to wait for the data writing phase of the current row to be completed before performing a voltage jump. In this way, the scanning phases of the pixel circuits in adjacent rows can overlap in time, and the pixel circuits belonging to the next row can also achieve data refresh normally, which is beneficial to shortening the frame time.

[0119] From the above analysis, it can be seen that by controlling the on-off state of the frequency control module 40 in each branch according to the frequency control signal CCL and the first scanning signal S1, it is possible to control whether the pixel circuit performs data refresh in each display frame; by controlling the frequency of data refresh of the pixel circuit, or by controlling the number of frames maintained by the pixel circuit between two adjacent write frames, the refresh frequency of the pixel circuit can be adjusted.

[0120] In the pixel circuit provided by an embodiment of the present invention, a frequency control module 40 is provided to control the on / off switching of the first branch and the second branch. During the hold frame, the frequency control module 40 controls the first branch and the second branch to be disconnected, allowing the threshold compensation module 20 and the first initialization module 30 to be turned on. Therefore, the first scan signal S1 and the second scan signal S2 can maintain the same waveforms during the hold frame as during the display frame. Therefore, the embodiment of the present invention does not require redesigning the gate drive circuit for providing the scan signals. Furthermore, by providing the frequency control module 40, pixel-level refresh frequency adjustment can be achieved, allowing the partition positions of display partitions with different refresh frequencies in the display panel to be arbitrarily adjusted as needed, enabling the display panel to support flexible partitioned and frequency-scaling display functions.

[0121] Figure 2 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 2 On the basis of the above embodiments, optionally, the frequency control module 40 includes: a first switch unit 410 , a second switch unit 420 and a voltage control unit 430 .

[0122] The first switch unit 410 is connected in series with the threshold compensation module 20 in the first branch; the first switch unit 410 is configured to be turned on or off based on the voltage at its control terminal. The control terminal K of the first switch unit 410 is an internal node of the frequency control module 40. The second switch unit 420 is connected in series with the first initialization module 30 in the second branch, and the control terminal of the second switch unit 420 is connected to the frequency control signal CCL; the second switch unit 420 is configured to be turned on or off based on the frequency control signal CCL. The voltage control unit 430 is connected to the control terminal K of the first switch unit 410 and is connected to the frequency control signal CCL and the first scan signal S1; the voltage control unit 430 is configured to control whether the frequency control signal CCL is transmitted to the control terminal K of the first switch unit 410 based on the first scan signal S1.

[0123] Specifically, when the first switch unit 410 is turned off, the first branch is disconnected; when the first switch unit 410 is turned on, the on / off state of the first branch is controlled by the threshold compensation module 20. When the second switch unit 420 is turned off, the second branch is disconnected; when the second switch unit 420 is turned on, the on / off state of the second branch is controlled by the first initialization module 30. When the voltage control unit 430 is turned on, the voltage of the frequency control signal CCL is written to the control terminal K of the first switch unit 410; when the voltage control unit 430 is turned off, the voltage of the control terminal K of the first switch unit 410 remains the voltage written to the control terminal K before the voltage control unit 430 is turned off.

[0124] Exemplarily, the turn-on voltage of the first switch unit 410 is the same as the turn-on voltage of the second switch unit 420, for example, both are low voltages or both are high voltages. When the first scan signal S1 is the cut-off voltage of the threshold compensation module 20, the control voltage control unit 430 is turned on and transmits the frequency control signal CCL to the control terminal K of the first switch unit 410. When the first scan signal S1 is the turn-on voltage of the threshold compensation module 20, the control voltage control unit 430 is turned off, so that the voltage at the control terminal K of the first switch unit 410 is maintained.

[0125] In the following, the on-state voltages of the first switch unit 410, the second switch unit 420, the first initialization module 30 and the threshold compensation module 29 are all high voltages, and the on-state voltage of the voltage control unit 430 is low voltage. Figure 3-Figure 6 , the driving process of the pixel circuit is explained.

[0126] See also Figure 2-Figure 6 In any display frame, the scanning phase of the pixel circuit includes a first initialization phase T11 and a data writing phase T12, which occur sequentially. In the first initialization phase T11, the second scanning signal S2 is the on-state voltage of the first initialization module 30, controlling the first initialization module 30 to be turned on, so that the on-off of the second branch is controlled by the second switch unit 420. In the data writing phase T12, the first scanning signal S1 is the on-state voltage of the threshold compensation module 20, controlling the threshold compensation module 20 to be turned on, so that the on-off of the first branch is controlled by the first switch unit 410.

[0127] In the display frame (holding frame) in which the pixel circuit holds data, the period in which the frequency control signal CCL holds the cutoff voltage of the second switch unit 420 at least covers the start time of the first initialization phase T11 and the data writing phase T12. In this way, it can be ensured that in the maintenance frame, in the first initialization phase T11, the frequency control signal CCL controls the second switch unit 420 to be turned off, so that the second branch is disconnected, and the initialization signal VREF does not reset the control terminal G of the driving module 10; and before the start of the data writing phase T12, the first scanning signal S1 controls the voltage control unit 430 to be turned on, and the frequency control signal CCL having the cut-off voltage of the second switch unit 420 can be transmitted to the control terminal K of the first switch unit 410 to control the first switch unit 410 to be turned off. After the start of the data writing phase T12, the first scanning signal S1 controls the voltage control unit 430 to be turned off, and the control terminal K of the first switch unit 410 can maintain the cut-off voltage of the second switch unit 420 (which is also the cut-off voltage of the first switch unit 410), so that the first branch remains in the off state in the data writing phase T12, and no data is written to the control terminal G of the driving module 10.

[0128] Specifically, during the period between the first initialization phase T11 and the data writing phase T12, the voltage of the frequency control signal CCL can be set arbitrarily. For example, the frequency control signal CCL can be set to maintain the cut-off voltage of the second switch unit 420 at least during the period from the start of the first initialization phase T11 to the start of the data writing phase T12, so as to reduce the voltage jump of the frequency control signal CCL. For example, see Figure 3 , the frequency control signal CCL can be set to maintain the cut-off voltage of the second switch unit 420 before the start of the first initialization phase T11 until the end of the data writing phase T12, so that the voltage VK of the control terminal K of the first switch unit 410 is the same as the waveform of the frequency control signal CCL. Alternatively, see Figure 4 The frequency control signal CCL can be set to maintain the cut-off voltage of the second switch unit 420 from the beginning of the first initialization phase T11 to the beginning of the data writing phase T12, and jump to the turn-on voltage of the second switch unit 420 in the data writing phase T12. Then, the voltage VK of the control terminal K of the first switch unit 410 follows the voltage change of the frequency control signal CCL before the data writing phase T12, maintains the cut-off voltage of the second switch unit 420 in the data writing phase T12, and follows the frequency control signal CCL to change the voltage again at the end of the data writing phase T12.

[0129] In a display frame (writing frame) in which the pixel circuit performs data refresh, the period in which the frequency control signal CCL maintains the on-voltage of the second switch unit 420 at least covers the start time of the first initialization phase T11 and the data writing phase T12. In this way, it can be ensured that in the write frame, in the first initialization phase T11, the frequency control signal CCL controls the second switch unit 420 to be turned on, so that the second branch is turned on, and the initialization signal VREF resets the control terminal G of the driving module 10; and before the start of the data writing phase T12, the first scan signal S1 controls the voltage control unit 430 to be turned on, and the frequency control signal CCL having the turn-on voltage of the second switch unit 420 can be transmitted to the control terminal K of the first switch unit 410 to control the turn-on of the first switch unit 410. After the start of the data writing phase T12, the first scan signal S1 controls the voltage control unit 430 to be turned off, and the control terminal K of the first switch unit 410 can maintain the turn-on voltage of the second switch unit 420 (which is also the turn-on voltage of the first switch unit 410), so that the first branch remains in the on state in the data writing phase T12, and data is written to the control terminal G of the driving module 10.

[0130] Specifically, during the period between the first initialization phase T11 and the data writing phase T12, the voltage of the frequency control signal CCL can be set arbitrarily. For example, the frequency control signal CCL can be set to maintain the on-voltage of the second switch unit 420 at least during the period from the start of the first initialization phase T11 to the start of the data writing phase T12, so as to reduce the voltage jump of the frequency control signal CCL. For example, see Figure 5 , the frequency control signal CCL can be set to maintain the on-state voltage of the second switch unit 420 before the start of the first initialization phase T11 and until the end of the data writing phase T12. Then, the voltage VK of the control terminal K of the first switch unit 410 has the same waveform as the frequency control signal CCL. Alternatively, see Figure 6 The frequency control signal CCL can be set to maintain the on-voltage of the second switch unit 420 from the start of the first initialization phase T11 to the start of the data writing phase T12, and jump to the cut-off voltage of the second switch unit 420 in the data writing phase T12. Then, the voltage VK of the control terminal K of the first switch unit 410 follows the voltage change of the frequency control signal CCL before the data writing phase T12, maintains the on-voltage of the second switch unit 420 in the data writing phase T12, and follows the frequency control signal CCL to change the voltage again at the end of the data writing phase T12.

[0131] In the above-mentioned embodiments, the refresh frequency control process of the pixel circuit is explained. The specific structure that the pixel circuit may have is exemplified below, but it is not intended to limit the present invention.

[0132] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 7 In one embodiment, optionally, the first switch unit 410 includes: a first transistor M1, the first transistor M1 and the threshold compensation module 20 are connected in series in a first branch, and the gate of the first transistor M1 is connected to the control terminal K of the first switch unit 410. In this embodiment, the first switch unit 410 is configured to be composed of a single transistor, which makes its structure simple and easy to implement.

[0133] In one embodiment, the second switch unit 420 optionally includes a second transistor M2, which is connected in series with the first initialization module 30 in the second branch, and the gate of the second transistor M2 is connected to the frequency control signal CCL. In this embodiment, the second switch unit 420 is configured to be composed of a single transistor, which makes its structure simple and easy to implement.

[0134] In one embodiment, the voltage control unit 430 optionally includes a third transistor M3, wherein a gate of the third transistor M3 is connected to the first scan signal S1, a first electrode of the third transistor M3 is connected to the frequency control signal CCL, and a second electrode of the third transistor M3 is connected to the control terminal K of the first switch unit 410. In this embodiment, the voltage control unit 430 is formed by a single transistor, which makes its structure simple and easy to implement.

[0135] Furthermore, the voltage control unit 430 further includes a first capacitor C1, a first end of which is connected to the control terminal K of the first switch unit 410, and a second end of which is connected to the fixed voltage signal VDC. By providing the first capacitor C1, the voltage at the control terminal K of the first switch unit 410 can be maintained when the third transistor M3 is turned off, thereby improving circuit operational stability.

[0136] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention. Figure 8 Based on the above embodiments, the threshold compensation module 20 optionally includes a fourth transistor M4, which is connected in series with the first switch unit 410 in the first branch, and the gate of the fourth transistor M4 is connected to the first scan signal S1. The first initialization module 30 includes a fifth transistor M5, which is connected in series with the second switch unit 420 in the second branch, and the gate of the fifth transistor M5 is connected to the second scan signal S2.

[0137] Based on the above embodiments, optionally, the first transistor M1 and the second transistor M2 may be set to have the same channel type, so that the on-voltage of the first switch unit 410 is the same as the on-voltage of the second switch unit 420. The third transistor M3 and the fourth transistor M4 may be set to have different channel types, so that the on-voltage source of the threshold compensation module 20 and the cut-off voltage of the voltage control unit 430 are the same, so that the gates of the third transistor M3 and the fourth transistor M4 can both be connected to the first scan signal S1 and have different on and off states.

[0138] Furthermore, the channel types of the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 can be set to be the same, so that the turn-on voltages of the first switch unit 410, the second switch unit 420, the threshold compensation module 20 and the first initialization module 30 are all the same.

[0139] On the basis of the above embodiments, optionally, the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 can be set to be N-type transistors, such as IGZO-type transistors, to reduce leakage on the first branch and the second branch; accordingly, the third transistor M3 can be set to be a P-type transistor, such as an LTPS transistor.

[0140] Continue to see Figure 8 Based on the above embodiments, optionally, the driving module 10 includes: a driving transistor DTFT, a gate of the driving transistor DTFT connected to the control terminal G of the driving module 10, a first electrode of the driving transistor DTFT connected to the first terminal S of the driving module 10, and a second electrode of the driving transistor DTFT connected to the second terminal D of the driving module 10.

[0141] The pixel circuit may further include: a data writing module 50, a light emitting control module 60, a second initialization module 70, and a storage module 80. The data writing module 50 includes a sixth transistor M6; the gate of the sixth transistor M6 is connected to the third scan signal S3, the first electrode of the sixth transistor M6 is connected to the data signal Vdata, and the second electrode of the sixth transistor M6 is connected to the first terminal S of the driving module 10. The light emitting control module 60 includes a seventh transistor M7 and an eighth transistor M8; the gates of the seventh transistor M7 and the eighth transistor M8 are both connected to the light emitting control signal EM, the first electrode of the seventh transistor M7 is connected to the first power supply signal VDD, the second electrode of the seventh transistor M7 is connected to the first terminal S of the driving module 10, the first electrode of the eighth transistor M8 is connected to the second terminal D of the driving module 10, the second electrode of the eighth transistor M8 is connected to the anode of the light emitting device OLED, and the cathode of the light emitting device OLED is connected to the second power supply signal VSS. The second initialization module 70 includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to the fourth scan signal S4, the first electrode of the ninth transistor M9 is connected to the initialization signal VREF, and the second electrode of the ninth transistor M9 is connected to the anode of the light emitting device OLED. The storage module 80 includes a storage capacitor Cst; a first end of the storage capacitor Cst is connected to a first power signal VDD, and a second end of the storage capacitor Cst is connected to a control terminal G of the driving module 10. The first power signal VDD and the second power signal VSS have different voltages. For example, the first power signal VDD is a high voltage, and the second power signal VSS is a low voltage.

[0142] For example, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are all N-type transistors, such as IGZO transistors; the other transistors in the pixel circuit are all P-type transistors, such as LTPS transistors. This allows for an LTPO pixel circuit that combines the advantages of low leakage current of N-type transistors with the good stability of P-type transistors, thereby improving display quality.

[0143] Based on the above embodiments, optionally, any one of the initialization signal VREF, the first power signal VDD and the second power signal VSS can be multiplexed as a fixed voltage signal connected to the second end of the first capacitor C1 to avoid introducing additional DC voltage signals and simplify the display panel wiring.

[0144] Figure 8 The driving timing of the pixel circuit shown in the writing frame can be seen in Figure 9 , in the drive timing of the maintenance frame can be seen Figure 10 . Figure 9 and Figure 10 In the figure, L1 represents the first branch, L2 represents the second branch, the shaded filling represents the branch is disconnected, and the blank filling represents the branch is on. Figures 8-10 The driving process of the pixel circuit in each display frame includes: a scanning phase T1 and a light-emitting phase T2. The scanning phase T1, for example, includes a phase in which the light-emitting control signal EM maintains the cutoff potential of the light-emitting control module 60. In addition to the first initialization phase T11 and the data writing phase T12, the scanning phase T1 may also include a second initialization phase T13. In the second initialization phase T13, the fourth scanning signal S4 controls the second initialization module 70 to be turned on, so that the initialization signal VREF resets the anode of the light-emitting device OLED. The second initialization phase T13 can be set at any position in the scanning phase T1, for example Figure 9 and Figure 10 As shown, it is arranged between the first initialization phase T11 and the data writing phase T12, or it may also overlap at least partially in time with either the first initialization phase T11 or the data writing phase T12. It can be understood that during the data writing phase T12, the third scanning signal S3 controls the data writing module 50 to turn on, so that the data signal Vdata is transmitted to the first terminal S of the driver module 10; during the light-emitting phase T2, the light-emitting control signal EM controls the light-emitting control module 60 to turn on, so that the driver module 10 generates a driving current based on the voltage at its control terminal G, thereby driving the light-emitting device OLED to emit light.

[0145] See also Figure 9 and Figure 10 It can be seen that during the driving process of the pixel circuit, whether it is a write frame or a hold frame, the waveforms of the scanning signals and the light-emitting control signal EM are consistent and are all high-frequency signals. By controlling the voltage of the frequency control signal CCL, the on-off of the first branch and the second branch can be controlled, thereby controlling whether the pixel circuit performs data refresh in the display frame. For details, see Figure 9In the writing frame, the frequency control signal CCL can be set to maintain the conduction voltage (herein, a high voltage) of the second switch unit 420 at least in the first initialization phase T11 and around the start of the data writing phase, so as to ensure that the second branch L2 is turned on in the first initialization phase T11 and the first branch L1 is turned on in the data writing phase T12. Figure 10 In the hold frame, the frequency control signal CCL can be set to maintain the cut-off voltage (here exemplarily a low voltage) of the second switch unit 420 at least in the first initialization phase T11 and around the start of the data writing phase, so as to ensure that the second branch L2 remains turned off in the display frame and the first branch L1 also remains turned off in the display frame.

[0146] In summary, the embodiments of the present invention provide a novel pixel circuit that helps to realize multi-frequency partitioning of arbitrary regions of a display panel, and can flexibly control the refresh frequency of the pixel circuit based on the frequency control signal CCL and the first scan signal S1.

[0147] An embodiment of the present invention further provides a display panel, including the pixel circuit provided by any embodiment of the present invention, and having corresponding beneficial effects.

[0148] Figure 11 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 11 The display panel 1000 may include a plurality of pixel circuits 100, and the plurality of pixel circuits 100 may be arranged in an array in the display area AA of the display panel 1000. The display panel 1000 may further include a non-display area NAA surrounding the display area AA. In addition, a gate driving circuit 200 and gate lines extending along the row direction may also be provided in the display panel 1000; the gate driving circuit 200 is provided in the non-display area NAA, and the gate driving circuit 200 is connected to the gate lines to provide corresponding gate driving signals to the pixel circuits 100 connected to the gate lines; the gate driving signals include, for example, various scanning signals and light-emitting control signals. Figure 11 The first gate line LS1 for transmitting the first scanning signal S1 and the second gate line for transmitting the second scanning signal S2 are shown as examples, but this is not intended to limit the present invention. In practical applications, the pixel circuit 100 has Figure 8 Taking the structure shown in FIG. 1 as an example, the display panel may further include a third gate line for transmitting a third scanning signal S3, a fourth gate line for transmitting a fourth scanning signal S4, and a fifth gate line for transmitting a light emitting control signal EM. The gate driving circuit 200 may specifically include a scanning circuit for providing a scanning signal and a light emitting control circuit for providing a light emitting control signal. Specifically, the pixel circuit 100 may have Figure 8Taking the illustrated structure as an example, the gate drive circuit 200 may include: a first scanning circuit for providing a first scanning signal S1 and a second scanning signal S2; a second scanning circuit for providing a third scanning signal S3 and a fourth scanning signal S4; and a light-emission control circuit for providing a light-emission control signal EM. The first scanning circuit utilizes one set of power supply voltages, while the second scanning circuit and the light-emission control circuit utilize another set of power supply voltages. The specific structure of the gate drive circuit 200 is not limited here; it only needs to be able to provide the required gate drive signals to the pixel circuit according to the driving requirements of the pixel circuit 100.

[0149] Based on the above embodiments, the display panel 1000 may optionally further include at least one frequency control signal line LC. Each frequency control signal line LC is connected to a corresponding pixel circuit 100 to transmit a frequency control signal CCL to the pixel circuit 100. At least one column of pixel circuits 100 is connected to the same frequency control signal line LC, and the frequency control signal line LC is used to provide the frequency control signal CCL to the connected pixel circuits 100.

[0150] Furthermore, the display panel 1000 further includes a plurality of data lines LD, each data line LD being connected to each column of pixel circuits 100 in a one-to-one correspondence. The data lines LD are used to transmit data signals Vdata. For example, the data lines LD and the frequency control signal lines LC extend in the same direction, for example, in the column direction, with the row direction being perpendicular to the column direction.

[0151] In this display panel, each row of pixel circuits 100 is scanned row by row, and the frequency control signal is supplied column by column. Therefore, during the scanning phase of each row of pixel circuits 100, the frequency control signal CCL received by the pixel circuits 100 belonging to each column in a row can be set according to the display requirements to control whether each pixel circuit 100 in a row performs data refresh. Therefore, through pixel-level refresh frequency control, it is possible to achieve partitioning at any position of the display panel 1000, and each display partition can display at a different refresh frequency. It can be understood that, based on the highest pulse frequency of the gate drive signal that the gate drive circuit 200 can provide, the refresh frequency of each display partition does not exceed this base frequency; and the pixel circuit of the embodiment of the present invention achieves frequency adjustment by controlling the number of hold frames inserted between adjacent write frames, and the refresh frequency of each display partition is a frequency that can be divided by the base frequency. The refresh frequency of the pixel circuits in each display partition can be controlled separately, and each pixel circuit 100 in the same display partition refreshes data at the refresh frequency of the display partition, and there is no limit on the refresh frequency between the display partitions.

[0152] The following describes the process of displaying at different frequencies in different regions of the display panel 1000 by taking the example of each column of pixel circuits 100 being connected to a frequency control signal line LC and each frequency control signal line LC being insulated from each other. Figure 12 , taking the three-partition display panel as an example, the display area AA of the display panel includes the first display partition A1, the second display partition A2 and the third display partition A3. Assume that the refresh frequencies of the first display partition A1, the second display partition A2 and the third display partition A3 decrease in sequence. For example, with a base frequency of 120Hz, the refresh frequency of the first display partition A1 is 120Hz, the refresh frequency of the second display partition A2 is 60Hz, and the refresh frequency of the third display partition A3 is 40Hz. Then, for the pixel circuit in the first display partition A1, each display frame is a refresh frame; for the pixel circuit in the second display partition A2, one hold frame can be inserted between every two adjacent refresh frames; for the pixel circuit in the third display partition A3, two hold frames can be inserted between every two adjacent refresh frames. Specifically, see Figure 13 , six display frames (F1-F6) can be used as a display cycle, and the control process of one display cycle is used as a cycle to repeat the control of each frequency control signal CCL. It can be understood that, Figure 13 In the display, the partition is divided into Figure 12 Similarly, each number in the array represents a pixel circuit, with 0 indicating that the pixel circuit is retaining data during a display frame, and 1 indicating that the pixel circuit is refreshing data during a display frame. For any pixel circuit, during its scanning phase, if the pixel circuit needs to retain data, the frequency control signal CCL must cooperate with the first scanning signal S1, so that the frequency control module controls the second branch to be disconnected during at least the first initialization phase and the first branch to be disconnected during at least the data writing phase. If the pixel circuit needs to refresh data, the frequency control signal CCL must cooperate with the first scanning signal S1, so that the frequency control module controls the second branch to be conductive during the first initialization phase and the first branch to be conductive during the data writing phase.

[0153] The following combination Figure 14 and Figure 15 , the control process of the intersection position of different display partitions along the column direction is described. For example, along the column direction, the last row of pixel circuits in the previous display partition belongs to the nth row of pixel circuits, and the first row of pixel circuits in the next display partition belongs to the n+1th row of pixel circuits, where n is a positive integer. Figure 14 and Figure 15The figures show the first scan signal S1n of the nth row, the second scan signal S2n of the nth row, the first scan signal S1n+1 of the n+1th row, the second scan signal S2n+1 of the n+1th row, a column frequency control signal CCL, the voltage VKn of the control terminal of the first switch unit in the pixel circuit belonging to the nth row in the same column, and the voltage VKn+1 of the control terminal of the first switch unit in the pixel circuit belonging to the n+1th row in the same column. The voltage of the frequency control signal CCL can represent the on / off state of the second branch, and the voltage of the control terminal of the first switch unit can represent the on / off state of the first branch.

[0154] Then, see Figure 14 When the pixel circuits in the previous display partition need to retain data and the pixel circuits in the next display partition need to refresh data: at or after the start of the data writing phase T12n for the pixel circuits in the nth row, the frequency control signal CCL is controlled to jump from the cutoff voltage of the second switch unit to the on-voltage of the second switch unit, so that when the data writing phase T12n for the pixel circuits in the nth row begins, the voltage VKn at the control terminal of the first switch unit in the pixel circuits in the nth row that receive the frequency control signal CCL is the cutoff voltage of the second switch unit (equal to the cutoff voltage of the first switch unit), and this cutoff voltage is maintained during the data writing phase T12n for the pixel circuits in the nth row. Preferably, the frequency control signal CCL is controlled to undergo a voltage jump after the start of the data writing phase T12n for the pixel circuits in the nth row, so as to avoid abnormal driving of the pixel circuits in the nth row in a column due to voltage jump delay or other reasons when the first scanning signal S1n and the frequency control signal CCL in the nth row jump simultaneously.

[0155] Furthermore, it is necessary to control the frequency control signal CCL to jump from the cut-off voltage of the second switch unit to the turn-on voltage of the second switch unit at or before the start of the first initialization phase T11n+1 of the pixel circuits in the n+1th row, so that during the first initialization phase T11n+1 of the pixel circuits in the n+1th row, the second switch unit in the pixel circuits in the n+1th row that receives the frequency control signal CCL is turned on, thereby turning on the second branch and resetting the control terminal of the driving module. For the first branch in the pixel circuits in the n+1th row that receives the frequency control signal CCL, even if the voltage Vkn+1 at the control terminal of the first switch unit jumps to the turn-on voltage of the second switch unit (equal to the turn-on voltage of the first switch unit) during the first initialization phase T11n+1 of the pixel circuits in the n+1th row, controlling the first switch unit to turn on, since the threshold compensation module is not turned on during this phase, the first branch will not be turned on either, and the reset process of the control terminal of the driving module will not be affected.

[0156] See also Figure 15When the pixel circuit in the previous display partition needs to refresh data and the pixel circuit in the next display partition needs to retain data: it is necessary to control the frequency control signal CCL to jump from the on-voltage of the second switch unit to the off-voltage of the second switch unit at the beginning or after the data writing phase T12n of the pixel circuit in the nth row, and at the beginning or before the first initialization phase T11n+1 of the pixel circuit in the n+1th row, so that in a column of pixel circuits receiving the frequency control signal CCL, the pixel circuits belonging to the nth row refresh data normally, and the pixel circuits belonging to the n+1th row retain data normally.

[0157] In summary, in the case where the scanning phases of two adjacent rows of pixel circuits overlap, the pixel circuit and display panel structure provided by any of the above embodiments can be used to normally implement any setting of the number, position and size of partitions.

[0158] In the case where the pulse width of the conduction pulse used by the first scanning signal to control the conduction of the threshold compensation module covers multiple line times, the pixel circuit and display panel structure provided by any of the above embodiments can also be used to normally realize any number of partitions, partition positions and partition sizes. Specifically, Figure 16 and Figure 17 exemplarily shows the first scanning signal S1n of the nth row to the scanning signal S1n+4 of the n+4th row. It can be seen that the pulse width of the on-pulse (pulse with a high voltage) in each first scanning signal is relatively wide, and there is overlap between the data writing phases of adjacent rows. Figure 16 and Figure 17 The figure also shows a column of frequency control signals CCL and the on / off states of the first branches (L1n to L1n+4) in each pixel circuit in rows n to n+4 in a column of pixel circuits connected to the frequency control signal CCL. For example, along the column direction, the last row of pixel circuits in the previous display partition belongs to the n+3 row of pixel circuits, and the first row of pixel circuits in the next display partition belongs to the n+4 row of pixel circuits, where n is a positive integer. Figure 16, when the pixel circuits in the previous display partition need to maintain data and the pixel circuits in the next display partition need to refresh data: it is necessary to set the time t01 when the frequency control signal CCL jumps from the cut-off voltage of the second switch unit to the on-voltage of the second switch unit, at or after the start of the data writing phase T12n+3 of the pixel circuit in the n+3th row, and before the start of the data writing phase T12n+4 of the pixel circuit in the n+4th row, so that the control terminal voltage of the first switch unit in the pixel circuit belonging to the n+3th row maintains the cut-off voltage of the first switch unit in the data writing phase T12n+3 of the pixel circuit in the n+3th row, and the control terminal voltage of the first switch unit in the pixel circuit belonging to the n+4th row maintains the on-voltage of the first switch unit in the data writing phase T12n+4 of the pixel circuit in the n+4th row. Similarly, see Figure 17 When the pixel circuit in the previous display partition needs to refresh data and the pixel circuit in the next display partition needs to retain data: it is necessary to set the time t02 when the frequency control signal CCL jumps from the on-voltage of the second switch unit to the off-voltage of the second switch unit, at the beginning or after the data writing phase T12n+3 of the pixel circuit in the n+3th row, and before the beginning of the data writing phase T12n+4 of the pixel circuit in the n+4th row.

[0159] The above embodiments illustrate a one-to-one connection between the frequency control signal line LC and each column of pixel circuits 100, but this is not intended to limit the present invention. In other embodiments, at least two pixel circuits 100 in the same row may optionally be connected to the same frequency control signal line LC to reduce the number of frequency control signal lines LC, thereby simplifying the display panel wiring. It will be understood that the refresh frequencies of the pixel circuits in the same row connected to the same frequency control signal line LC change synchronously. In actual applications, the number and location of the pixel circuits in the same row connected to the same frequency control signal line LC can be determined by taking into account the wiring difficulty and the partition control accuracy.

[0160] On the basis of the above-mentioned embodiments, optionally, the pixel circuits 100 connected to the same frequency control signal line LC in the same row can be selected according to the pixel arrangement in the display panel 1000. Specifically, the display panel 1000 includes a plurality of pixel units, and each pixel unit includes at least two pixel circuits 100; in the same row, the pixel circuits 100 belonging to the same pixel unit can be connected to the same frequency control signal line LC, and different pixel circuits 100 belonging to different pixel units can be connected to different frequency control signal lines LC. This setting allows the refresh frequency of the same pixel unit to change synchronously, which is equivalent to realizing the frequency setting and partition setting at the pixel unit level. Since the pixel circuits 100 in the same pixel unit themselves need to display at the same refresh frequency, this setting in this embodiment is equivalent to simplifying the wiring of the display panel without affecting the partition control accuracy. For example, see Figure 18 In the case of Real RGB pixel arrangement, three pixel circuits 100 in a row may share a frequency control signal line LC; or, see Figure 19 In the case of SPR pixel arrangement, two pixel circuits 100 in a row can share a frequency control signal line LC. It can be understood that Figure 18 and Figure 19 In FIG, R represents a pixel circuit driving a red sub-pixel, G represents a pixel circuit driving a green sub-pixel, and B represents a pixel circuit driving a blue sub-pixel.

[0161] Based on the above embodiments, optionally, in the pixel circuit 100, the frequency control module includes a first switch unit, a second switch unit, and a voltage control unit. At least two pixel circuits 100 in the same row can be set to share the same voltage control unit to further simplify the panel structure. Exemplarily, the display panel includes a plurality of pixel units, each pixel unit includes at least two pixel circuits 100; in the same row, the pixel circuits 100 belonging to the same pixel unit share the same voltage control unit. Specifically, see Figure 20 Taking two pixel circuits sharing the same voltage control unit 430 as an example, the control ends of the first switch units in the pixel circuits sharing the same voltage control unit 430 are connected together and connected to the third transistor M3; and the control ends of the second switch units in the pixel circuits sharing the same voltage control unit 430 are connected to the same frequency control signal line LC.

[0162] An embodiment of the present invention further provides a display device that can implement flexible zone-by-zone and frequency-by-frequency display. Figure 21 Schematic diagram of a display device according to an embodiment of the present invention. Figure 21The display device includes: a display panel 1000 and a driving component 2000. The display panel 1000 includes a plurality of pixel circuits 100 and at least one frequency control signal line LC. Figure 22 The pixel circuit 100 includes a driving module 10, a threshold compensation module 20, a first initialization module 30, and a frequency control module 40. The threshold compensation module 20 is disposed in a first branch connected between the control terminal G and the second terminal D of the driving module 10. The first initialization module 30 is disposed in a second branch connected to the control terminal G of the driving module 10. The frequency control module 40 is connected to the frequency control signal line LC corresponding to the pixel circuit 100. The frequency control module 40 is configured to control the on / off state of the first branch and the second branch according to the frequency control signal CCL transmitted by the connected frequency control signal line LC, thereby controlling the refresh frequency of the pixel circuit 100. The driving component 2000 is connected to each frequency control signal line LC and is configured to control the voltage of the frequency control signal CCL transmitted by each frequency control signal line LC according to the partition frequency information SF.

[0163] Exemplarily, when the frequency control signal CCL is the cut-off voltage of the frequency control module 40, the frequency control module 40 controls both the first branch and the second branch to be disconnected; when the frequency control signal CCL is the on-voltage of the frequency control module 40, the frequency control module 40 controls the on-off of the first branch to be controlled by the threshold compensation module 20, and the on-off of the second branch to be controlled by the first initialization module 30.

[0164] In the display device provided by the embodiment of the present invention, a frequency control module 40 is provided to control the on / off state of the first and second branches in each pixel circuit 100 based on a frequency control signal CCL, thereby controlling the refresh frequency of each pixel circuit 100. This enables pixel-level refresh frequency adjustment, allowing the positions of display partitions with different refresh frequencies in the display panel to be adjusted as needed. Furthermore, the display panel 1000 can support flexible partitioned and frequency-controlled display functions without redesigning the gate drive circuit 200.

[0165] Figure 23 is a structural diagram of another display device provided by an embodiment of the present invention, see Figure 23Based on the above embodiments, the driver component 2000 optionally includes: a timing controller 201, a driver chip 202, and level shifting circuits 203, the same number as the frequency control signal lines LC. The timing controller 201 receives partition frequency information SF, parses the partition frequency information SF, and generates a display control signal DP. The driver chip 202 is connected to the timing controller 201 and receives and parses the display control signal DP. Each level shifting circuit 203 is connected to a frequency control signal line LC in a one-to-one correspondence. Each level shifting circuit 203 receives a first level signal VGH and a second level signal VGL, and is connected to the driver chip 202. The driver chip 202 controls each level shifting circuit 203 to output either the first level signal VGH or the second level signal VGL based on the display control signal DP. The first level signal VGH and the second level signal VGL have different second voltages, for example, the first level signal VGH has a high voltage, and the second level signal VGL has a low voltage.

[0166] Specifically, the display panel 1000 includes a plurality of pixel circuits 100 arranged in an array; the display panel 1000 also includes: a gate drive circuit 200, which is connected to a timing controller 201 and connected to each row of pixel circuits 100 through each gate line LS. The timing controller 201 is also used to control the output of the gate drive circuit 200 so that each row of pixel circuits 100 enters the scanning phase row by row. The timing controller 201 can, for example, output a gate control signal GP based on a basic frequency to control the working process of the gate drive circuit 200. The gate control signal GP may include a start signal and a clock signal required for the operation of the gate drive circuit 200. The driver chip 202 is used to control the voltage of the frequency control signal CCL received by each pixel circuit 100 in a row according to the display control signal DP during the scanning phase of each row of pixel circuits 100, so that the frequency control signal CCL changes in real time with the scanning row position.

[0167] The display panel 1000 may include multiple frequency control signal lines LC, each of which is connected to at least one column of pixel circuits 100. Accordingly, the driver component 2000 includes multiple level conversion circuits 203. The display control signal DP may include refresh control signals for each row of pixel circuits 100. The timing controller 201 serially outputs the refresh control signals for each row of pixel circuits 100 to the driver chip 202. During the scanning phase of any row of pixel circuits 100, the driver chip 202 controls each level conversion circuit 203 to transmit the frequency control signal CCL in parallel to each frequency control signal line LC based on the refresh control signal for that row of pixel circuits 100.

[0168] This embodiment is configured such that, based on the serial data transmitted from the timing controller 201, after serial-to-parallel conversion by the driver chip 202 and level conversion by the level conversion circuit 203, frequency control signals CCL are generated for all sub-pixel columns. Each frequency control signal CCL changes in real time with the scan line position. This allows the refresh rate setting of any display partition to be converted into specific pixel circuit control, dividing the display screen into high-frequency refresh areas and low-frequency refresh areas. Furthermore, this signal control method enables online setting of any row, column, or number of areas, facilitating real-time adjustment of the display partition position and frequency without power outages during the display process.

[0169] Based on the above embodiments, the display panel 1000 optionally further includes: a plurality of data lines LD, connected one-to-one to each column of pixel circuits 100; a driver chip 202 further connected to each data line LD; and a timing controller 201 further configured to control the driver chip 202 to transmit a corresponding data signal Vdata to each data line LD, thereby controlling the display panel 1000 to display an image. The data lines LD and the frequency control signal lines LC extend in the same direction, for example, in the column direction.

[0170] Based on the above embodiments, optionally, multiple pixel circuits 100 are arranged in an array in the display panel 1000, with at least two pixel circuits 100 in the same row connected to the same frequency control signal line LC, thereby reducing wiring in the display panel. For example, the display panel 1000 includes multiple pixel units, each of which includes at least two pixel circuits 100. In the same row, the pixel circuits 100 belonging to the same pixel unit are connected to the same frequency control signal line LC, while different pixel circuits 100 belonging to different pixel units are connected to different frequency control signal lines LC.

[0171] Figure 24 FIG is a structural diagram of another display device provided by an embodiment of the present invention. Figure 24 For example, the display device includes a host 3000 and a display module 4000, and the display module 4000 includes, for example, a display panel 1000 and a driving component 2000. The host 3000 is connected to the driving component 2000, and the host 3000 is used to provide partition frequency information SF. Specifically, the partition frequency information SF may include: the number, position, and refresh rate of each display partition in the display area AA of the display panel 1000. The position of the display partition can be reflected by the coordinates of each vertex, for example Figure 12The three partitions shown, the position of the first display partition A1 can be reflected by the coordinates of the pixel circuits of its four vertices in the display area AA, the position of the second display partition A2 can be reflected by the coordinates of the pixel circuits of its four vertices in the display area AA, and the positions in the display area AA except the first display partition A1 and the second display partition A2 all belong to the third display partition A3. Specifically, when the electronic product is in use, the host (or client / AP) 3000 can know the current small window situation, know whether the small window displays video, pictures, or text, and generate partition frequency information SF accordingly. The partition frequency information SF may specifically include the number of partitions, the coordinates of each partition, and the refresh frequency value of each partition. After receiving the partition frequency information SF, the timing controller 201 parses it to generate coordinate parsing data. Each binary digit represents a pixel. The number of rows and columns of the parsed data is equal to the resolution (resolution) of the display screen. The parsing results can be seen in Figure 13 The timing controller 201 temporarily stores the analysis results and outputs them serially and row by row to the driver chip 202 .

[0172] Based on the above embodiments, the display panel 1000 may optionally include a lower frame area and a display area AA that are sequentially away from the driver chip 202. The level conversion circuit 203 may be disposed in the lower frame area (eg Figure 23 As shown), in order to facilitate the wiring between the driving chip 202 and the level conversion circuit 203, as well as the level conversion circuit 203 and each frequency control signal line LC. Alternatively, the level conversion circuit 203 can also be set in the circuit board (such as FPC or PCB) used to carry the timing controller 201. Alternatively, see Figure 25 The level conversion circuit can be integrated into the driver chip 202 to avoid the level conversion circuit occupying the volume of the display module 4000.

[0173] In summary, the embodiment of the present invention can realize the multi-frequency display technology of partitioning at any position, and the partition position can be changed in real time according to the partition frequency information SF. The partitioning at any position includes two technical branches: partitioning by row and partitioning by column, both of which can be implemented using a set of solutions. To facilitate understanding of the control process of the driver chip 202 on each level conversion circuit 203, Figure 26-Figure 28 The control signal CP provided by the driving chip 202 to each level conversion circuit 203 in different time periods within a frame in various partitioning modes is provided in FIG. , which will be described below respectively. Figure 26-Figure 28 In the figure, each bit in the control signal CP represents a control signal provided by the driver chip 202 to a level conversion circuit 203, wherein 0 represents the cut-off voltage of the control level conversion circuit 203 outputting the frequency control module, and 1 represents the on-voltage of the control level conversion circuit 203 outputting the frequency control module; the thick horizontal line represents the position of the pixel circuit row currently being scanned. Figure 26In the example, the display area AA is divided into two partitions, the display area AA is divided into a first display partition A11 and a second display partition A12. In the current frame, the pixel circuit in the first display partition A11 refreshes data, and the pixel circuit in the second display partition A12 retains data. Figure 27 For example, the display area AA is divided into three partitions, and the display area AA is divided into a first display partition A21, a second display partition A22 and a third display partition A23. The first display partition A21 and the second display partition A22 are arranged along the row direction; in the current frame, the pixel circuits in the first display partition A21 and the second display partition A22 refresh data, and the pixel circuits in the third display partition A23 maintain data. Figure 28 For example, the display area AA is divided into three partitions, namely, the first display partition A31, the second display partition A32 and the third display partition A33. The first display partition A31 and the second display partition A32 are arranged along the column direction. In the current frame, the pixel circuits in the first display partition A31 and the second display partition A32 perform data refresh, and the pixel circuits in the third display partition A33 perform data retention. Figures 26-28 It can be seen that regardless of how display area AA is divided into display zones, the driver chip 201 controls the level shifter circuit 203 connected to each pixel circuit that needs to be refreshed to output the on-voltage of the frequency control module, and controls the level shifter circuit 203 connected to each pixel circuit that needs to maintain the output of the off-voltage of the frequency control module during at least a portion of the scanning phase corresponding to each row of pixel circuits. After each row of pixel circuits is scanned, the control signal CP is updated based on the display control signal DP provided by the upstream.

[0174] For the voltage variation of the frequency control signal in each display frame, please refer to Figure 28 and Figure 29 , here we select Figure 28 The first frequency control signal line LC1 on the right side of the middle provides the first frequency control signal CCL1, and Figure 28 The second frequency control signal CCL2 provided by the second frequency control signal line LC2 on the left side is shown, wherein the first frequency control signal line LC1 passes through the third display partition A33 and the second display partition A32, and the second frequency control signal line LC2 passes through the third display partition A33, the first display partition A31 and the second display partition A32. Figure 29In the first frame F11, data is refreshed across the entire screen, and both the first frequency control signal CCL1 and the second frequency control signal CCL2 maintain the on-voltage of the frequency control module (here, illustratively, a high voltage). In the second frame F12, data is refreshed in the first display partition A31 and the second display partition A32, while data is maintained in the third display partition A33. Therefore, in the second frame F12, the first frequency control signal CCL1 serves as the on-voltage of the frequency control module during the scanning phase for each row of pixel circuits in the first display partition A31 and each row of pixel circuits in the second display partition A32, and serves as the off-voltage of the frequency control module during other periods. In the second frame F12, the second frequency control signal CCL2 serves as the on-voltage of the frequency control module during the scanning phase for each row of pixel circuits in the second display partition A32, and serves as the off-voltage of the frequency control module during other periods.

[0175] In summary, in the display device provided by the embodiment of the present invention, the partition position and partition size can be completely controlled by signals and can be changed at any time during product use. If the partition position needs to be changed, there is no need to change the hardware structure, and the product does not need to be powered off. The partition information can be directly updated in the client host or timing controller to achieve the update of the partition, realizing real-time adjustable partition multi-frequency technology. Moreover, it is possible to achieve arbitrary partition position settings and arbitrary partition sizes. For example, the display device can be a car display, an industrial control display, a computer display, a TV, a PAD, etc.

[0176] In one embodiment, the pixel circuit may optionally have the structure described in any of the above embodiments, and the frequency control module 40 may include a first switch unit, a second switch unit, and a voltage control unit. Then, the on-voltage of the frequency control module 40 is equal to the off-voltage of the second switch unit.

[0177] In another embodiment, optionally, see Figure 30 The frequency control module 40 includes a third switch unit 440 and a fourth switch unit 450. The third switch unit 440 is connected in series with the threshold compensation module 20 in the first branch, and the control terminal of the third switch unit 440 is connected to the frequency control signal CCL. The fourth switch unit 450 is connected in series with the first initialization module 30 in the second branch, and the control terminal of the second switch unit 450 is connected to the frequency control signal CCL.

[0178] Specifically, the turn-on voltage of the third switch unit 440 is the same as the turn-on voltage of the fourth switch unit 450. Accordingly, the turn-on voltage of the frequency control module 40 is equal to the turn-on voltage of the third switch unit 440. In any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase, which occur sequentially. During the first initialization phase, the first initialization module 30 is turned on; during the data writing phase, the threshold compensation module 20 is turned on. In display frames where the pixel circuit is refreshing data, the frequency control signal CCL maintains the turn-on voltage of the third switch unit 440 during at least the first initialization phase and the data writing phase. In display frames where the pixel circuit is retaining data, the frequency control signal CCL maintains the turn-on voltage of the third switch unit 440 during at least the first initialization phase and the data writing phase. Furthermore, in display frames where the pixel circuit is refreshing data, the frequency control signal CCL maintains the turn-on voltage of the third switch unit 440 during the scanning phase; and in display frames where the pixel circuit is retaining data, the frequency control signal CCL maintains the turn-on voltage of the third switch unit 440 during the scanning phase.

[0179] Specifically, the third switch unit 440 includes: a tenth transistor M10, the tenth transistor M10 is connected in series with the threshold compensation module 20 in the first branch, and the gate of the tenth transistor M10 is connected to the frequency control signal CCL. The fourth switch unit 450 includes: an eleventh transistor M11, the eleventh transistor M11 is connected in series with the first initialization module 30 in the second branch, and the gate of the eleventh transistor M11 is connected to the frequency control signal CCL. Exemplarily, the tenth transistor M10 and the eleventh transistor M11 have the same channel type. For example, the tenth transistor M10 and the eleventh transistor M11 are both N-type transistors, such as IGZO transistors, to reduce leakage on the first branch and the second branch; or, the tenth transistor M10 and the eleventh transistor M11 are both P-type transistors, such as LTPS transistors, to reduce the occupied area of ​​the tenth transistor M10 and the eleventh transistor M11, which is conducive to achieving high pixel density. The structures of other modules in the pixel circuit can be referred to. Figure 8 The explanation is not repeated here.

[0180] In this embodiment, two transistors are added to each pixel circuit as control switches, a frequency control signal line is added to each sub-pixel column, and a level conversion circuit is provided outside the display area AA. Pixel-level refresh state control can be achieved under the control of the frequency control signal CCL. Even pixel circuits in the same row can be in two pixel states: data refresh and data write.

[0181] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0182] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: include: Driver module; a threshold compensation module, provided in a first branch connected between the control terminal and the second terminal of the driving module, the threshold compensation module being configured to be turned on or off according to a first scanning signal; A first initialization module is provided in the second branch connected to the control end of the driving module, and the first initialization module is used to turn on or off according to the second scanning signal; a frequency control module, connected to the first branch and the second branch, respectively, and receiving a frequency control signal and the first scanning signal; the frequency control module is used to control the on / off of the first branch according to the frequency control signal and the first scanning signal, and to control the on / off of the second branch according to the frequency control signal, so as to control the refresh frequency of the pixel circuit; The frequency control module includes: A first switch unit is connected in series with the threshold compensation module in the first branch; the first switch unit is used to be turned on or off according to the voltage of its control terminal; a second switch unit, connected in series with the first initialization module in the second branch, and a control end of the second switch unit receiving the frequency control signal; the second switch unit is configured to be turned on or off according to the frequency control signal; a voltage control unit connected to the control end of the first switch unit and receiving the frequency control signal and the first scanning signal; the voltage control unit is used to control whether the frequency control signal is transmitted to the control end of the first switch unit according to the first scanning signal; The first switch unit includes: a first transistor connected in series with the threshold compensation module in the first branch, and a gate of the first transistor is connected to a control terminal of the first switch unit; The second switch unit includes: a second transistor connected in series with the first initialization module in the second branch, and a gate of the second transistor is connected to the frequency control signal; The voltage control unit includes: a third transistor, a gate of the third transistor is connected to the first scanning signal, a first electrode of the third transistor is connected to the frequency control signal, and a second electrode of the third transistor is connected to the control end of the first switch unit.

2. The pixel circuit according to claim 1, wherein: One end of the second branch is connected to the control end of the driving module, and the other end of the second branch is connected to the initialization signal.

3. The pixel circuit according to claim 2, wherein: The on-voltage of the first switch unit is the same as the on-voltage of the second switch unit; when the first scanning signal is the cut-off voltage of the threshold compensation module, the voltage control unit is controlled to transmit the frequency control signal to the control end of the first switch unit.

4. The pixel circuit according to claim 3, wherein: In any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase that occur successively; in the first initialization phase, the second scanning signal is the turn-on voltage of the first initialization module; in the data writing phase, the first scanning signal is the turn-on voltage of the threshold compensation module; In a display frame in which the pixel circuit performs data refresh, a period in which the frequency control signal maintains the on-voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase; In a display frame in which the pixel circuit performs data retention, a period in which the frequency control signal maintains the cut-off voltage of the second switch unit at least covers the start times of the first initialization phase and the data writing phase.

5. The pixel circuit according to claim 4, wherein: In a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains the on-voltage of the second switch unit at least during a period from the start of the first initialization phase to the start of the data writing phase; In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the second switch unit at least during a period from the start of the first initialization phase to the start of the data writing phase.

6. The pixel circuit according to claim 1, wherein: The voltage control unit further includes: a first capacitor, a first end of the first capacitor is connected to the control end of the first switch unit, and a second end of the first capacitor is connected to a fixed voltage signal.

7. The pixel circuit according to claim 1, wherein: The threshold compensation module includes: a fourth transistor connected in series with the first switch unit in the first branch, and the gate of the fourth transistor is connected to the first scanning signal; The first initialization module includes: a fifth transistor connected in series with the second switch unit in the second branch, and a gate of the fifth transistor is connected to the second scanning signal.

8. The pixel circuit according to claim 7, wherein: The first transistor and the second transistor have the same channel type, and the third transistor and the fourth transistor have different channel types.

9. The pixel circuit according to claim 7, wherein: The first transistor, the second transistor, the fourth transistor, and the fifth transistor all have the same channel type.

10. The pixel circuit according to claim 9, wherein: The first transistor, the second transistor, the fourth transistor, and the fifth transistor are all N-type transistors, and the third transistor is a P-type transistor.

11. The pixel circuit according to any one of claims 1 to 10, characterized in that: The driving module includes a driving transistor, a gate of the driving transistor connected to the control terminal of the driving module, a first electrode of the driving transistor connected to the first terminal of the driving module, and a second electrode of the driving transistor connected to the second terminal of the driving module.

12. The pixel circuit according to claim 11, wherein: The pixel circuit further includes: The data writing module includes a sixth transistor; the gate of the sixth transistor is connected to the third scanning signal, the first electrode of the sixth transistor is connected to the data signal, and the second electrode of the sixth transistor is connected to the first end of the driving module; a light-emitting control module, comprising a seventh transistor and an eighth transistor; the gates of the seventh transistor and the eighth transistor are both connected to a light-emitting control signal, a first electrode of the seventh transistor is connected to a first power supply signal, a second electrode of the seventh transistor is connected to a first terminal of the driver module, a first electrode of the eighth transistor is connected to a second terminal of the driver module, a second electrode of the eighth transistor is connected to an anode of a light-emitting device, and a cathode of the light-emitting device is connected to a second power supply signal; The second initialization module includes a ninth transistor; a gate of the ninth transistor is connected to the fourth scanning signal, a first electrode of the ninth transistor is connected to the initialization signal, and a second electrode of the ninth transistor is connected to the anode of the light-emitting device; The storage module includes a storage capacitor; a first end of the storage capacitor is connected to the first power signal, and a second end of the storage capacitor is connected to the control end of the driving module.

13. The pixel circuit according to claim 12, wherein: The frequency control module includes a first capacitor, and a second end of the first capacitor is connected to a fixed voltage signal; wherein the initialization signal, the first power signal or the second power signal is multiplexed into the fixed voltage signal.

14. A display panel, characterized in that: include: The pixel circuit according to any one of claims 1 to 13.

15. The display panel according to claim 14, wherein: The frequency control module includes a first switch unit, a second switch unit and a voltage control unit; the display panel includes a plurality of pixel circuits arranged in an array; at least two pixel circuits in the same row share the same voltage control unit.

16. The display panel according to claim 15, wherein: The display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit share the same voltage control unit.

17. The display panel according to claim 14, wherein: The display panel further includes: at least one frequency control signal line, at least one column of pixel circuits is connected to the same frequency control signal line, and the frequency control signal line is used to provide the frequency control signal to the connected pixel circuits.

18. The display panel according to claim 17, wherein: At least two pixel circuits in the same row are connected to the same frequency control signal line.

19. The display panel according to claim 18, wherein: The display panel includes multiple pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines.

20. The display panel according to claim 17, wherein The display panel further includes: a plurality of data lines connected to each column of pixel circuits in a one-to-one correspondence; the data lines and the frequency control signal lines extend in the same direction.

21. A display device, characterized in that: include: The display panel according to any one of claims 14 to 20, comprising a plurality of pixel circuits and at least one frequency control signal line; the pixel circuit comprising: a driving module, a threshold compensation module, a first initialization module and a frequency control module; the threshold compensation module is arranged in a first branch connected between a control end and a second end of the driving module; the first initialization module is arranged in a second branch connected to the control end of the driving module; the frequency control module is connected to the frequency control signal line corresponding to the pixel circuit, and the frequency control module is used to control the on and off of the first branch and the second branch according to the frequency control signal transmitted by the connected frequency control signal line, so as to control the refresh frequency of the pixel circuit; A driving component is connected to each of the frequency control signal lines and is used to control the voltage of the frequency control signal transmitted by each of the frequency control signal lines according to the partition frequency information.

22. The display device according to claim 21, wherein The drive assembly includes: A timing controller, configured to analyze the partition frequency information and generate a display control signal; A driver chip connected to the timing controller; The number of level conversion circuits is the same as the number of frequency control signal lines, and each level conversion circuit is connected to each frequency control signal line in a one-to-one correspondence; each level conversion circuit is connected to a first level signal and a second level signal, and is connected to the driver chip; the driver chip is used to control each level conversion circuit to output the first level signal or the second level signal according to the display control signal.

23. The display device according to claim 22, wherein: The display panel includes a plurality of pixel circuits arranged in an array; The display panel further includes: a gate driving circuit connected to the timing controller and each pixel circuit respectively; The timing controller is further used to control the output of the gate drive circuit so that the pixel circuits in each row enter the scanning phase row by row; The driving chip is used to control the voltage of the frequency control signal received by each pixel circuit in a row according to the display control signal during the scanning phase of each row of pixel circuits.

24. The display device according to claim 23, wherein: The display panel includes multiple frequency control signal lines, one of which is connected to at least one column of pixel circuits; the display control signal includes a refresh control signal for each row of pixel circuits, and the timing controller serially outputs the refresh control signal for each row of pixel circuits to the driver chip; during the scanning phase of any row of pixel circuits, the driver chip controls each level conversion circuit to transmit the frequency control signal in parallel to each frequency control signal line according to the refresh control signal for the pixel circuit in that row.

25. The display device according to claim 22, wherein The display panel further includes: a plurality of data lines, which are connected to each column of pixel circuits in a one-to-one correspondence; the driving chip is also connected to each of the data lines; and the timing controller is further used to control the driving chip to transmit a corresponding data signal to each of the data lines.

26. The display device according to claim 25, wherein: The data line and the frequency control signal line extend in the same direction.

27. The display device according to claim 24, wherein: At least two pixel circuits in the same row are connected to the same frequency control signal line.

28. The display device according to claim 27, wherein: The display panel includes multiple pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines.

29. The display device according to claim 22, wherein: The display device further includes: a host connected to the driving component and configured to provide the partition frequency information.

30. The display device according to claim 29, wherein The partition frequency information includes: the number, position and refresh frequency of each display partition in the display area of ​​the display panel.

31. The display device according to claim 22, wherein The display panel includes a lower frame area and a display area which are sequentially away from the driving chip, the level conversion circuit is arranged in the lower frame area, and the pixel circuit is arranged in the display area; Alternatively, the level conversion circuit is integrated into the driver chip; Alternatively, the level conversion circuit is arranged in a circuit board for carrying the timing controller.

32. The display device according to claim 21, wherein The pixel circuit is the pixel circuit according to any one of claims 1 to 13.

33. The display device according to claim 21, wherein The frequency control module includes: a third switch unit, connected in series with the threshold compensation module in the first branch, and a control terminal of the third switch unit is connected to the frequency control signal; A fourth switch unit is connected in series with the first initialization module in the second branch, and a control end of the second switch unit is connected to the frequency control signal.

34. The display device according to claim 33, wherein: A turn-on voltage of the third switch unit is the same as a turn-on voltage of the fourth switch unit.

35. The display device according to claim 34, wherein: In any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase that occur successively; in the first initialization phase, the first initialization module is turned on; in the data writing phase, the threshold compensation module is turned on; In a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit at least in the first initialization phase and the data writing phase; In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit at least in the first initialization phase and the data writing phase.

36. The display device according to claim 35, characterized in that In a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit in the scanning phase; In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switching unit in the scanning phase.

37. The display device according to claim 33, wherein: The third switch unit includes: a tenth transistor connected in series with the threshold compensation module in the first branch, and a gate of the tenth transistor is connected to the frequency control signal; The fourth switch unit includes: an eleventh transistor connected in series with the first initialization module in the second branch, and a gate of the eleventh transistor is connected to the frequency control signal.

38. The display device according to claim 37, wherein: The tenth transistor and the eleventh transistor have the same channel type.

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