Double-screen full-screen display control system based on FPGA

Abstract

The invention discloses a double-screen full-screen display control system based on an FPGA (Field Programmable Gate Array), which belongs to the technical field of display control systems and comprises a video output unit, an FPGA programmable logic module I, an FPGA programmable logic module II, a flat-panel display and a television display, the video output unit is in communication connection with the first FPGA programmable logic module and the second FPGA programmable logic module. The first FPGA programmable logic module is in communication connection with the second FPGA programmable logic module, the first FPGA programmable logic module is in communication connection with the flat panel display, and the second FPGA programmable logic module is in communication connection with the television display. By means of the mode, full-screen display automatically adaptive to the displays of two types is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of display control systems, and in particular to a dual-screen full-screen display control system based on FPGA. Background Art

[0002] FPGA chip (field programmable gate array chip) is a programmable integrated circuit chip. It can change the hardware circuit structure inside the chip through software programming according to the needs of users, so as to realize different logical functions. It is like a "universal circuit board" that users can freely design and modify the circuit connection mode and function without re-manufacturing the chip.

[0003] Currently, when projecting a screen to two display devices with different display resolutions, the output display signal often cannot adapt to both display devices at the same time, so it is necessary to manually adjust one of the resolutions to achieve a full-screen display effect.

[0004] Based on this, the present invention designs a dual-screen full-screen display control system based on FPGA to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a dual-screen full-screen display control system based on FPGA.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0007] A dual-screen full-screen display control system based on FPGA, comprising a video output unit, a FPGA programmable logic module 1, a FPGA programmable logic module 2, a flat panel display and a television display;

[0008] The video output unit is communicatively connected with both the FPGA programmable logic module 1 and the FPGA programmable logic module 2;

[0009] The FPGA programmable logic module 1 is connected to the FPGA programmable logic module 2 for communication, the FPGA programmable logic module 1 is connected to the flat panel display for communication, and the FPGA programmable logic module 2 is connected to the TV display for communication;

[0010] The video output unit is used for outputting the first direction MIPI display signal and the audio signal. The video output unit sends the first direction MIPI display signal to the FPGA programmable logic module 1, and the video output unit sends the audio signal to the FPGA programmable logic module 2;

[0011] The FPGA programmable logic module 1 is used to send the first direction MIPI display signal to the FPGA programmable logic module 2 and the flat panel display;

[0012] The flat panel display is used for displaying an image of a MIPI display signal in a first direction;

[0013] The FPGA programmable logic module 2 is used to simultaneously identify the extended display identification data of the TV display by the FPGA programmable logic module 2, and process the first direction MIPI display signal into a second direction MIPI display signal through the graphic software according to the extended display identification data, the FPGA programmable logic module 2 simultaneously receives the audio signal sent by the video output unit, and converts the audio signal and the second direction MIPI display signal into an HDMI signal, and the FPGA programmable logic module 2 sends the HDMI signal to the TV display;

[0014] The television display is used for displaying images of HDMI signals.

[0015] Furthermore, the video output unit is also used to send firmware update information to FPGA programmable logic module 1 and FPGA programmable logic module 2 through an SPI serial interface.

[0016] Furthermore, the video output unit includes a video processor SOC, an audio output port, a serial bus port 1, a serial bus port 2 and a MIPI video output port;

[0017] The audio output port, serial bus port 1 and serial bus port 2 are all arranged on the video processor SOC and are all electrically connected to the video processor SOC;

[0018] The audio output port is communicatively connected to FPGA programmable logic module 2, serial bus port 1 and serial bus port 2 are communicatively connected to FPGA programmable logic module 2 and FPGA programmable logic module 1 respectively, and the MIPI video output port is communicatively connected to the video input port of FPGA programmable logic module 1.

[0019] Furthermore, the audio output port is used to output the audio signal to the FPGA programmable logic module 2;

[0020] Serial bus port 1 is used to communicate with FPGA programmable logic module 2;

[0021] Serial bus port 2 is used to communicate with FPGA programmable logic module 1;

[0022] The MIPI video output port is used to output a first direction MIPI display signal to FPGA programmable logic module one.

[0023] Furthermore, the FPGA programmable logic module 1 includes MIPI video interface 1, MIPI video interface 2, pseudo-static random access memory controller, pseudo-static random access memory 1, pseudo-static random access memory 2 and high-speed differential serial bus controller;

[0024] The MIPI video interface 1 and the MIPI video interface 2 are both communicatively connected to the pseudo-static random access memory controller, the pseudo-static random access memory controller is communicatively connected to the pseudo-static random access memory 1, the pseudo-static random access memory 2, and the high-speed differential serial bus controller, and the high-speed differential serial bus controller is communicatively connected to the FPGA programmable logic module 2.

[0025] Furthermore, the MIPI video interface 1 is used to receive a first direction MIPI display signal sent by a MIPI video output port, and the MIPI video interface 1 sends the first direction MIPI display signal to a pseudo-static random row memory controller;

[0026] The pseudo-static random access memory controller sends the first direction MIPI display signal to the pseudo-static random access memory 1 and the pseudo-static random access memory 2 for video data caching;

[0027] The pseudo-static random row memory controller sends the first direction MIPI display signal to the MIPI video interface 2, and the MIPI video interface 2 sends the flat panel display;

[0028] The pseudo-static random row memory controller sends the first direction MIPI display signal to the high-speed differential serial bus controller, and the high-speed differential serial bus controller sends it to the FPGA programmable logic module 2.

[0029] Furthermore, the FPGA programmable logic module 1 also includes a serial bus controller 1, a firmware update 1 and a firmware storage 1;

[0030] The serial bus controller 1 is communicatively connected with the serial bus port 2 and the firmware update 1, and the firmware update 1 is communicatively connected with the firmware storage 1;

[0031] The serial bus port 2 sends firmware data 1 to firmware update 1 through a serial bus controller 1, and the firmware update 1 stores the firmware data 1 in a firmware storage 1.

[0032] Furthermore, the FPGA programmable logic module 2 includes an HDMI video interface, a high-speed differential serial bus controller, a serial bus controller 2, a memory controller, a video buffer 1, a video buffer 2, an image processing unit and an image scaling unit;

[0033] The HDMI video interface is communicatively connected with the TV display, the audio output port, the second serial bus controller, and the image processing unit;

[0034] The image processing unit is communicatively connected to the memory controller and the image scaling unit, the memory controller is communicatively connected to the video buffer 1 and the video buffer 2, the high-speed differential serial bus controller is communicatively connected to the image scaling unit and the high-speed differential serial bus controller, and the serial bus controller 2 is communicatively connected to the serial bus port 1;

[0035] The HDMI video interface is used to obtain the extended display identification data from the television display, the HDMI video interface sends the extended display identification data to the image processing unit, and the image processing unit sends it to the image scaling unit;

[0036] The HDMI video interface is also used to receive the audio signal sent by the audio output port, and the HDMI video interface sends the audio signal to the image processing unit;

[0037] The extended display identification data records the maximum resolution displayed by the television display;

[0038] The high-speed differential serial bus controller is used to receive a first direction MIPI display signal sent by the high-speed differential serial bus controller, and the high-speed differential serial bus controller sends the first direction MIPI display signal to the image scaling unit;

[0039] The image scaling unit is used to swap the horizontal pixel value and the vertical pixel value according to the maximum resolution of the extended display identification data, and scale the resolution of the first direction MIPI display signal according to the swapped resolution, and send the scaled first direction MIPI display signal to the image processing unit;

[0040] The image processing unit is used to interchange the horizontal pixel value and the vertical pixel value of the scaled first direction MIPI display signal based on the graphics software and output the second direction MIPI display signal, and the image processing unit sends the HDMI signal to the HDMI video interface and the memory controller;

[0041] The image processing unit is also used to convert the audio signal and the second direction MIPI display signal into an HDMI signal based on the MIPI and HDMI conversion protocols;

[0042] The memory controller is used for writing and reading cache data of the video buffer 1 and the video buffer 2, and the memory controller sends the HDMI signal to the video buffer 1 and the video buffer 2;

[0043] The video buffer 1 and the video buffer 2 are used for caching HDMI signals.

[0044] Furthermore, the FPGA programmable logic module 2 also includes a firmware update 2 and a firmware storage 2;

[0045] The second firmware updater is communicatively connected with the second firmware storage and the second serial bus controller;

[0046] The serial bus port 1 sends the firmware data 2 to the firmware update 2 through the serial bus controller 2, and the firmware update 2 sends the firmware data 2 to the firmware storage 2 for storage.

[0047] Compared with the prior art, the present invention has the following beneficial effects: 1. Full-screen display signals of two resolutions are output respectively through FPGA programmable logic module 1 and FPGA programmable logic module 2, without the need to manually adjust the resolution.

[0048] The FPGA programmable logic module 1 directly sends the first direction MIPI display signal sent by the video output unit to the flat panel display;

[0049] 2. After the HDMI video interface identifies the maximum resolution of the TV display, the image scaling unit scales the first direction display information to a resolution after the horizontal pixel value and the vertical pixel value are swapped with the maximum resolution of the TV display, and the image processing unit swaps the horizontal pixel value and the vertical pixel value of the scaled first direction display information, thereby outputting a second direction MIPI display signal adapted to the maximum resolution of the TV display;

[0050] This enables both flat panel displays and TV displays to output images in full screen without the need for complicated manual resolution adjustments. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 The present invention is a block diagram of a dual-screen full-screen display control system based on FPGA.

[0053] The numbers in the figure represent:

[0054] 1. Video output unit 11. Video processor SOC 12. Audio output port 13. Serial bus port one 14. Serial bus port two 15. MIPI video output port 2. FPGA programmable logic module one 21. MIPI video interface one 22. MIPI video interface two 23. Pseudo-static random access memory controller 24. Pseudo-static random access memory one 25. Pseudo-static random access memory two 26. High-speed differential serial bus controller 27. Serial bus controller one 28. Firmware update one 29. Firmware storage one 3. FPGA programmable logic module two 31. HDMI video interface 32. High-speed differential serial bus controller 33. Serial bus controller two 34. Memory controller 35. Video buffer one 36. Video buffer two 37. Image processing unit 38. Image scaling unit 39. Firmware update two 310. Firmware storage two 4. Flat panel display 5. TV display DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] Embodiment 1: In some embodiments, please refer to the drawings of the specification Figure 1 , a dual-screen full-screen display control system based on FPGA, comprising a video output unit 1, an FPGA programmable logic module 1 2, an FPGA programmable logic module 2 3, a flat panel display 4 and a TV display 5;

[0057] The video output unit 1 is communicatively connected with the FPGA programmable logic module 1 2 and the FPGA programmable logic module 2 3;

[0058] FPGA programmable logic module one 2 is connected to FPGA programmable logic module two 3 for communication, FPGA programmable logic module one 2 is connected to flat panel display 4 for communication, and FPGA programmable logic module two 3 is connected to TV display 5 for communication;

[0059] The video output unit 1 is used for outputting the first direction MIPI display signal and the audio signal. The video output unit 1 sends the first direction MIPI display signal to the FPGA programmable logic module 1 2, and the video output unit 1 sends the audio signal to the FPGA programmable logic module 2 3;

[0060] FPGA programmable logic module one 2 is used to send the first direction MIPI display signal to FPGA programmable logic module two 3 and flat panel display 4;

[0061] The flat panel display 4 is used for image display of the MIPI display signal in the first direction;

[0062] The FPGA programmable logic module 2 3 is used to simultaneously identify the extended display identification data of the TV display 5, and process the first direction MIPI display signal into a second direction MIPI display signal through graphic software according to the extended display identification data. The FPGA programmable logic module 2 3 simultaneously receives the audio signal sent by the video output unit 1, and converts the audio signal and the second direction MIPI display signal into HDMI signals. The FPGA programmable logic module 2 3 sends the HDMI signal to the TV display 5;

[0063] The television display 5 is used for displaying images of HDMI signals.

[0064] The video output unit 1 is also used to send firmware update information to the FPGA programmable logic module 1 2 and the FPGA programmable logic module 2 3 through the SPI serial interface.

[0065] The video output unit 1 includes a video processor SOC 11, an audio output port 12, a serial bus port 1 13, a serial bus port 2 14 and a MIPI video output port 15;

[0066] The audio output port 12, the serial bus port 1 13, and the serial bus port 2 14 are all arranged on the video processor SOC 11 and are all electrically connected to the video processor SOC 11;

[0067] The audio output port 12 is connected to the FPGA programmable logic module 2 3 for communication, the serial bus port 1 13 and the serial bus port 2 14 are connected to the FPGA programmable logic module 2 3 and the FPGA programmable logic module 1 2 for communication respectively, and the MIPI video output port 15 is connected to the video input terminal of the FPGA programmable logic module 1 2 for communication;

[0068] The FPGA programmable logic module 1 2 includes a MIPI video interface 1 21, a MIPI video interface 2 22, a pseudo-static random access memory controller 23, a pseudo-static random access memory 1 24, a pseudo-static random access memory 2 25 and a high-speed differential serial bus controller 26;

[0069] MIPI video interface 1 21 and MIPI video interface 2 22 are both connected to the pseudo-static random access memory controller 23, the pseudo-static random access memory controller 23 is connected to the pseudo-static random access memory 1 24, the pseudo-static random access memory 2 25, and the high-speed differential serial bus controller 26, and the high-speed differential serial bus controller 26 is connected to the FPGA programmable logic module 2 3;

[0070] The MIPI video interface 1 21 is used to receive the first direction MIPI display signal sent by the MIPI video output port 15, and the MIPI video interface 1 21 sends the first direction MIPI display signal to the pseudo-static random row memory controller 23;

[0071] The pseudo-static random access memory controller 23 sends the first direction MIPI display signal to the pseudo-static random access memory 1 24 and the pseudo-static random access memory 2 25 for video data caching;

[0072] The pseudo-static random row memory controller 23 sends the first direction MIPI display signal to the MIPI video interface 2 22, and the MIPI video interface 2 22 sends the flat panel display 4;

[0073] The pseudo-static random row memory controller 23 sends the first direction MIPI display signal to the high-speed differential serial bus controller 26, and the high-speed differential serial bus controller 26 sends it to the FPGA programmable logic module 23;

[0074] The FPGA programmable logic module 2 also includes a serial bus controller 27, a firmware update 28 and a firmware storage 29;

[0075] The serial bus controller 1 27 is connected to the serial bus port 2 14 and the firmware update 1 28 for communication, and the firmware update 1 28 is connected to the firmware storage 1 29 for communication;

[0076] The serial bus port 2 14 sends the firmware data 1 to the firmware update 1 28 through the serial bus controller 1 27 , and the firmware update 1 28 stores the firmware data 1 in the firmware storage 1 29 .

[0077] The FPGA programmable logic module 2 3 includes an HDMI video interface 31, a high-speed differential serial bus controller 32, a serial bus controller 2 33, a memory controller 34, a video buffer 1 35, a video buffer 2 36, an image processing unit 37 and an image scaling unit 38;

[0078] The HDMI video interface 31 is communicatively connected with the TV display 5, the audio output port 12, the serial bus controller 2 33, and the image processing unit 37;

[0079] The image processing unit 37 is connected to the memory controller 34 and the image scaling unit 38 in communication, the memory controller 34 is connected to the video buffer 1 35 and the video buffer 2 36 in communication, the high-speed differential serial bus controller 32 is connected to the image scaling unit 38 and the high-speed differential serial bus controller 26 in communication, and the serial bus controller 2 33 is connected to the serial bus port 1 13 in communication;

[0080] The HDMI video interface 31 is used to obtain the extended display identification data EDID from the television display 5, and the HDMI video interface 31 sends the extended display identification data to the image processing unit 37, and the image processing unit 37 sends it to the image scaling unit 38;

[0081] The HDMI video interface 31 is also used to receive the audio signal sent by the audio output port 12, and the HDMI video interface 31 sends the audio signal to the image processing unit 37;

[0082] The extended display identification data records the maximum resolution displayed by the television display 5;

[0083] The high-speed differential serial bus controller 32 is used to receive the first direction MIPI display signal sent by the high-speed differential serial bus controller 26, and the high-speed differential serial bus controller 32 sends the first direction MIPI display signal to the image scaling unit 38;

[0084] The image scaling unit 38 is used to swap the horizontal pixel value and the vertical pixel value according to the maximum resolution of the extended display identification data, and scale the resolution of the first direction MIPI display signal according to the swapped resolution, and send the scaled first direction MIPI display signal to the image processing unit 37;

[0085] The image processing unit 37 is used to swap the horizontal pixel value and the vertical pixel value of the scaled first direction MIPI display signal based on the graphic software and output the second direction MIPI display signal. The image processing unit 37 sends the HDMI signal to the HDMI video interface 31 and the memory controller 34;

[0086] The image processing unit 37 is also used to convert the audio signal and the second direction MIPI display signal into an HDMI signal based on the MIPI and HDMI conversion protocols;

[0087] The memory controller 34 is used for writing and reading cache data of the video buffer 1 35 and the video buffer 2 36 . The memory controller 34 sends the HDMI signal to the video buffer 1 35 and the video buffer 2 36 .

[0088] Video buffer one 35 and video buffer two 36 are used for caching HDMI signals.

[0089] The FPGA programmable logic module 2 3 also includes a firmware update 2 39 and a firmware storage 2 310;

[0090] The firmware update 2 39 is in communication connection with the firmware storage 2 310 and the serial bus controller 2 33;

[0091] The serial bus port 13 sends the firmware data 2 to the firmware update 2 39 through the serial bus controller 2 33 , and the firmware update 2 39 sends the firmware data 2 to the firmware storage 2 310 for storage;

[0092] When the present invention is used, full-screen display signals of two resolutions are outputted respectively through FPGA programmable logic module 1 2 and FPGA programmable logic module 2 3, without the need to manually adjust the resolution.

[0093] When the present invention is used, the FPGA programmable logic module 1 2 directly sends the first direction MIPI display signal sent by the video output unit 1 to the flat panel display 4;

[0094] After the HDMI video interface 31 identifies the maximum resolution of the TV display 5, the image scaling unit 38 scales the first direction display information to a resolution after the horizontal pixel value and the vertical pixel value are swapped with the maximum resolution of the TV display 5, and the image processing unit 37 swaps the horizontal pixel value and the vertical pixel value of the scaled first direction display information, thereby outputting a second direction MIPI display signal adapted to the maximum resolution of the TV display 5;

[0095] This ensures that both the flat panel display 4 and the television display 5 can output images on full screen without the need for complicated manual adjustment of the resolution.

[0096] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-screen full-screen display control system based on FPGA, characterized by: It comprises a video output unit (1), a FPGA programmable logic module 1 (2), a FPGA programmable logic module 2 (3), a flat panel display (4) and a television display (5); The video output unit (1) is communicatively connected with the FPGA programmable logic module 1 (2) and the FPGA programmable logic module 2 (3); The FPGA programmable logic module 1 (2) is communicatively connected to the FPGA programmable logic module 2 (3), the FPGA programmable logic module 1 (2) is communicatively connected to the flat panel display (4), and the FPGA programmable logic module 2 (3) is communicatively connected to the television display (5); The video output unit (1) is used to output a first direction MIPI display signal and an audio signal. The video output unit (1) sends the first direction MIPI display signal to the FPGA programmable logic module 1 (2), and the video output unit (1) sends the audio signal to the FPGA programmable logic module 2 (3); The FPGA programmable logic module one (2) is used to send a first direction MIPI display signal to the FPGA programmable logic module two (3) and the flat panel display (4); The flat panel display (4) is used for image display of a MIPI display signal in a first direction; The FPGA programmable logic module 2 (3) is used to simultaneously identify the extended display identification data of the television display (5) by the FPGA programmable logic module 2 (3), and process the first direction MIPI display signal into a second direction MIPI display signal through graphic software according to the extended display identification data; the FPGA programmable logic module 2 (3) simultaneously receives the audio signal sent by the video output unit (1), and converts the audio signal and the second direction MIPI display signal into an HDMI signal; the FPGA programmable logic module 2 (3) sends the HDMI signal to the television display (5); The television display (5) is used for displaying images of HDMI signals.

2. The FPGA-based dual-screen full-screen display control system according to claim 1, characterized in that: The video output unit (1) is also used to send firmware update information to the FPGA programmable logic module one (2) and the FPGA programmable logic module two (3) via the SPI serial interface.

3. The FPGA-based dual-screen full-screen display control system according to claim 2 is characterized in that: The video output unit (1) comprises a video processor SOC (11), an audio output port (12), a serial bus port 1 (13), a serial bus port 2 (14) and a MIPI video output port (15); The audio output port (12), serial bus port 1 (13), and serial bus port 2 (14) are all arranged on the video processor SOC (11) and are all electrically connected to the video processor SOC (11); The audio output port (12) is connected to the FPGA programmable logic module 2 (3) for communication, the serial bus port 1 (13) and the serial bus port 2 (14) are connected to the FPGA programmable logic module 2 (3) and the FPGA programmable logic module 1 (2) for communication respectively, and the MIPI video output port (15) is connected to the video input port of the FPGA programmable logic module 1 (2) for communication.

4. The FPGA-based dual-screen full-screen display control system according to claim 3 is characterized in that: The audio output port (12) is used to output the audio signal to the FPGA programmable logic module 2 (3); Serial bus port 1 (13) is used to communicate with FPGA programmable logic module 2 (3); Serial bus port two (14) is used to communicate with FPGA programmable logic module one (2); The MIPI video output port (15) is used to output a first direction MIPI display signal to the FPGA programmable logic module 1 (2).

5. The FPGA-based dual-screen full-screen display control system according to claim 4 is characterized in that: The FPGA programmable logic module 1 (2) includes a MIPI video interface 1 (21), a MIPI video interface 2 (22), a pseudo-static random access memory controller (23), a pseudo-static random access memory 1 (24), a pseudo-static random access memory 2 (25) and a high-speed differential serial bus controller (26); The MIPI video interface 1 (21) and the MIPI video interface 2 (22) are both communicatively connected to a pseudo-static random access memory controller (23), the pseudo-static random access memory controller (23) is communicatively connected to a pseudo-static random access memory 1 (24), a pseudo-static random access memory 2 (25), and a high-speed differential serial bus controller (26), and the high-speed differential serial bus controller (26) is communicatively connected to an FPGA programmable logic module 2 (3).

6. The FPGA-based dual-screen full-screen display control system according to claim 5, characterized in that: The MIPI video interface 1 (21) is used to receive a first direction MIPI display signal sent by the MIPI video output port (15), and the MIPI video interface 1 (21) sends the first direction MIPI display signal to the pseudo-static random row memory controller (23); The pseudo-static random access memory controller (23) sends the first direction MIPI display signal to the pseudo-static random access memory 1 (24) and the pseudo-static random access memory 2 (25) for video data caching; The pseudo-static random row memory controller (23) sends the first direction MIPI display signal to the MIPI video interface 2 (22), and the MIPI video interface 2 (22) sends the flat panel display (4); The pseudo-static random row memory controller (23) sends the first direction MIPI display signal to the high-speed differential serial bus controller (26), and the high-speed differential serial bus controller (26) sends it to the FPGA programmable logic module 2 (3).

7. The FPGA-based dual-screen full-screen display control system according to claim 6, characterized in that: The FPGA programmable logic module (2) further includes a serial bus controller (27), a firmware update (28) and a firmware storage (29); The serial bus controller 1 (27) is in communication connection with the serial bus port 2 (14) and the firmware update 1 (28), and the firmware update 1 (28) is in communication connection with the firmware storage 1 (29); The serial bus port 2 (14) sends firmware data 1 to firmware update 1 (28) through serial bus controller 1 (27), and firmware update 1 (28) stores the firmware data 1 in firmware storage 1 (29).

8. The FPGA-based dual-screen full-screen display control system according to claim 7, characterized in that: The FPGA programmable logic module 2 (3) includes an HDMI video interface (31), a high-speed differential serial bus controller (32), a serial bus controller 2 (33), a memory controller (34), a video buffer 1 (35), a video buffer 2 (36), an image processing unit (37) and an image scaling unit (38); The HDMI video interface (31) is communicatively connected to the television display (5), the audio output port (12), the second serial bus controller (33), and the image processing unit (37); The image processing unit (37) is in communication connection with the memory controller (34) and the image scaling unit (38); the memory controller (34) is in communication connection with the video buffer 1 (35) and the video buffer 2 (36); the high-speed differential serial bus controller (32) is in communication connection with the image scaling unit (38) and the high-speed differential serial bus controller (26); the serial bus controller 2 (33) is in communication connection with the serial bus port 1 (13); The HDMI video interface (31) is used to obtain the extended display identification data from the television display (5), the HDMI video interface (31) sends the extended display identification data to the image processing unit (37), and the image processing unit (37) sends it to the image scaling unit (38); The HDMI video interface (31) is also used to receive an audio signal sent by the audio output port (12), and the HDMI video interface (31) sends the audio signal to the image processing unit (37); The extended display identification data records the maximum resolution displayed by the television display (5); The high-speed differential serial bus controller (32) is used to receive a first direction MIPI display signal sent by the high-speed differential serial bus controller (26), and the high-speed differential serial bus controller (32) sends the first direction MIPI display signal to the image scaling unit (38); The image scaling unit (38) is used to swap the horizontal pixel value and the vertical pixel value according to the maximum resolution of the extended display identification data, and scale the resolution of the first direction MIPI display signal according to the swapped resolution, and send the scaled first direction MIPI display signal to the image processing unit (37); The image processing unit (37) is used to exchange the horizontal pixel value and the vertical pixel value of the scaled first-direction MIPI display signal based on the graphics software and output the second-direction MIPI display signal, and the image processing unit (37) sends the HDMI signal to the HDMI video interface (31) and the memory controller (34); The image processing unit (37) is also used to convert the audio signal and the second direction MIPI display signal into an HDMI signal based on the MIPI and HDMI conversion protocols; The memory controller (34) is used for writing and reading cache data of the video buffer 1 (35) and the video buffer 2 (36), and the memory controller (34) sends the HDMI signal to the video buffer 1 (35) and the video buffer 2 (36); The video buffer 1 (35) and the video buffer 2 (36) are used for caching HDMI signals.

9. The FPGA-based dual-screen full-screen display control system according to claim 8, characterized in that: The FPGA programmable logic module 2 (3) further includes a firmware update 2 (39) and a firmware storage 2 (310); The second firmware updater (39) is in communication connection with the second firmware storage (310) and the second serial bus controller (33); The serial bus port 1 (13) sends firmware data 2 to firmware update 2 (39) through serial bus controller 2 (33), and firmware update 2 (39) sends firmware data 2 to firmware storage 2 (310) for storage.

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