Communication rate adaptive configuration data communication system and use method thereof

Abstract

The invention discloses a configuration data communication system with a self-adaptive communication rate and a use method of the configuration data communication system, and relates to the technical field of data communication. The FPGA external chip is used for converting data sent by the upper computer through the internet access into signals which can be read by the FPGA receiving module and converting the signals of the FPGA into data which can be transmitted back to the upper computer through the internet access; a signal cached in the FPGA storage module is read through the FPGA receiving module, the receiving unit and the sending unit with the adaptive frequency are selected to work, and a data packet sent by an upper computer is received through the receiving unit with the adaptive frequency; and a data packet is sent to an upper computer by using a sending unit with adaptive frequency through the FPGA sending module. According to the scheme, the adaptability of the digital control system is greatly improved, meanwhile, the flexibility is improved, and the economical efficiency of system application and deployment can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of data communication technology, and in particular to a communication rate adaptive configuration data communication system and a method for using the same. Background Art

[0002] At present, most of the safety-level digital control systems independently developed on the market are developed using FPGA technology. In actual operation, the digital control system needs to exchange information with the host PC. In previous designs, the rate of information exchange between the two often uses a single fixed rate.

[0003] With the development of the times, the application scenarios of digital control systems are becoming more and more diverse, and the amount of information data interacting per unit time also varies greatly. Even if the same control system is used, the amount of data that needs to be transmitted will vary greatly at different operating times. For security systems with high real-time requirements, the transmission rate needs to be increased, but not all occasions require high-speed transmission. Some older PCs, or due to certain communication stability reasons, have lower transmission rates.

[0004] If the digital control system of the same hardware can only support a single communication rate, different hardware systems need to be configured for different applications; in addition, if the host PC system is upgraded, the digital control system hardware must also be updated, which greatly increases the cost of use and reduces the flexibility and adaptability of use. Based on the above reasons, it is necessary to design a digital control system that adapts to different communication rates. Summary of the invention

[0005] The purpose of the present application is to provide a communication rate adaptive configuration data communication system and a method of using the same, which can adapt to different communication rates and greatly improve the adaptability of the digital control system.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In the first aspect, the present application provides a configuration data communication system with adaptive communication rate, comprising: an FPGA external chip, an FPGA storage module, an FPGA receiving module, an FPGA sending module and a host computer; the FPGA receiving module includes several receiving units with different operating frequencies; the FPGA sending module includes several sending units with different operating frequencies.

[0008] The FPGA external chip is used to convert the data sent from the host computer through the network port into signals that can be read by the FPGA receiving module and to convert the FPGA signals into data that can be transmitted back to the host computer through the network port; the FPGA storage module is used to cache the signals output by the FPGA external chip according to the data sent from the host computer through the network port; the FPGA receiving module is used to read the signals cached in the FPGA storage module, select the receiving unit and the sending unit with adapted frequency to work, and receive the data packets sent from the host computer through the receiving unit with adapted frequency; the FPGA sending module is used to send data packets to the host computer using the sending unit with adapted frequency.

[0009] Optionally, when the communication rate adaptive configuration data communication system is powered on for the first time, the write and read function verification of the FPGA storage module is performed; if the write and read function verification of the FPGA storage module fails, the system stops entering the working state; if the write and read function verification of the FPGA storage module succeeds, the system enters the working state.

[0010] Optionally, when entering the working state, the data in the FPGA storage module is cleared, the working mode of the FPGA external chip is initialized, and the initial value of the data packet to be received and sent by each receiving unit and each sending module is set, and the network connection state is initialized.

[0011] Optionally, the host computer is used to send three connection establishment data packets and a PC verification data packet to the FPGA receiving module; the FPGA sending module is used to send a first FPGA verification data packet and a second FPGA verification data packet to the host computer.

[0012] In a second aspect, the present application provides a method for using a configuration data communication system with adaptive communication rate, which is applied to the configuration data communication system with adaptive communication rate as described above, and the method for using the configuration data communication system with adaptive communication rate comprises the following steps:

[0013] The data sent by the host computer through the network port is converted into a signal that can be read by the FPGA receiving module through the FPGA external chip, and cached in the FPGA storage module.

[0014] The signal cached in the FPGA storage module is read through the FPGA receiving module to determine the receiving unit and the sending unit that are adapted to the frequency to work.

[0015] The data packet sent by the host computer is received by the frequency-adaptive receiving unit in the FPGA receiving module; the FPGA receiving module includes several receiving units with different working frequencies.

[0016] The data packet is sent to the upper computer through the frequency-adaptive sending unit in the FPGA sending module; the FPGA sending module includes a plurality of sending units with different operating frequencies.

[0017] Optionally, when the communication rate adaptive configuration data communication system is powered on for the first time, the method for using the communication rate adaptive configuration data communication system further includes the following steps:

[0018] The write and read functions of the FPGA storage module are verified. If the write and read functions of the FPGA storage module fail to be verified, the system stops and enters the working state. If the write and read functions of the FPGA storage module are verified successfully, the system enters the working state.

[0019] Optionally, after entering the working state, the method for using the communication rate adaptive configuration data communication system further includes the following steps:

[0020] Clear the data in the FPGA storage module.

[0021] Initialize the working mode of the FPGA external chip.

[0022] Set the initial value of the data packet to be received by each receiving unit.

[0023] Set the initial value of the data packet to be sent by each sending module.

[0024] Initialize network connection status.

[0025] Optionally, the host computer is used to send three connection establishment data packets and a PC verification data packet to the FPGA receiving module; the FPGA sending module is used to send a first FPGA verification data packet and a second FPGA verification data packet to the host computer.

[0026] Optionally, after initializing the network connection state, the method for using the communication rate adaptive configuration data communication system further includes the following steps:

[0027] The FPGA receiving module waits to receive three connection establishment data packets sent by the host computer.

[0028] The three connection establishment data packets sent by the host computer are analyzed by each receiving unit in the FPGA receiving module to determine the receiving unit and the sending unit that adapt to the frequency.

[0029] The first FPGA verification data packet is sent to the host computer through the frequency-adaptive sending unit, and the PC verification data packet sent by the host computer is waited for to be received through the frequency-adaptive receiving unit.

[0030] If a PC verification data packet sent by the host computer is received within the waiting time, the PC verification data packet sent by the host computer is verified.

[0031] If the PC verification data packet sent by the host computer is verified correctly, a second FPGA verification data packet is sent to the host computer through the frequency-adaptive sending unit, and the frequency-adaptive sending unit and the receiving unit are put into a normal communication state.

[0032] Optionally, after sending a second FPGA verification data packet to the upper computer through the frequency-adaptive sending unit and making the frequency-adaptive sending unit and the receiving unit enter a normal communication state, the method for using the communication rate adaptive configuration data communication system further includes the following steps:

[0033] During each data packet transmission process in the normal communication state, a CRC check is performed on the data packet sent by the host computer.

[0034] If the CRC check fails three times in a row or the data packet is not received within the time limit, jump to step "waiting to receive three connection establishment data packets sent by the host computer through the FPGA receiving module".

[0035] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0036] The present application provides a communication rate adaptive configuration data communication system and its use method, the system includes: FPGA external chip, FPGA storage module, FPGA receiving module, FPGA sending module and host computer; through the FPGA external chip, the data sent by the host computer through the network port is converted into a signal that can be read by the FPGA receiving module and the FPGA signal is converted into data that can be transmitted back to the host computer through the network port; the FPGA receiving module reads the signal cached in the FPGA storage module, selects the receiving unit and the sending unit of the adaptive frequency to work, and receives the data packet sent by the host computer through the receiving unit of the adaptive frequency; and uses the sending unit of the adaptive frequency to send the data packet to the host computer through the FPGA sending module. The above scheme of the present application meets the diversity and security requirements of the nuclear industry for the safety-level digital control system controller, and takes into account the optimization cost factor. On the FPGA chip, by designing a receiving module and a sending module that support high and low speed adaptation, the digital control system can support both high-speed communication and low-speed communication, which greatly improves the adaptability of the digital control system, while improving flexibility, and can effectively improve the economy of system application and deployment. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of functional modules of a configuration data communication system with adaptive communication rate provided in one embodiment of the present application.

[0039] Figure 2 A flowchart of a method for using a communication rate adaptive configuration data communication system provided by an embodiment of the present application.

[0040] Figure 3 A flowchart of initializing and configuring each FPGA module and network connection status in a method for using a communication rate adaptive configuration data communication system provided in one embodiment of the present application.

[0041] Figure 4 The present invention provides a flow chart of establishing a communication connection between an FPGA and a host computer PC in a method for using a communication rate adaptive configuration data communication system provided in an embodiment of the present application.

[0042] Figure 5 A flow chart of establishing a communication connection from a primary perspective using a host computer PC in a method for using a communication rate adaptive configuration data communication system provided in an embodiment of the present application.

[0043] Figure 6 A flow chart of establishing a communication connection from the FPGA board as the main perspective in a method for using a communication rate adaptive configuration data communication system provided in an embodiment of the present application

[0044] Figure 7 A schematic diagram of the structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0046] In order to make the above-mentioned objects, features and advantages of the present application more obvious and understandable, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0047] In an exemplary embodiment, Figure 1 As shown, a communication rate adaptive configuration data communication system is provided, including: an FPGA external chip, an FPGA storage module, an FPGA receiving module, an FPGA sending module and a host computer; the FPGA receiving module includes several receiving units with different operating frequencies; the FPGA sending module includes several sending units with different operating frequencies.

[0048] The FPGA external chip is used to convert the data sent from the host computer through the network port into signals that can be read by the FPGA receiving module and to convert the FPGA signals into data that can be transmitted back to the host computer through the network port; the FPGA storage module is used to cache the signals output by the FPGA external chip according to the data sent from the host computer through the network port; the FPGA receiving module is used to read the signals cached in the FPGA storage module, select the receiving unit and the sending unit with adapted frequency to work, and receive the data packets sent from the host computer through the receiving unit with adapted frequency; the FPGA sending module is used to send data packets to the host computer using the sending unit with adapted frequency.

[0049] In an exemplary embodiment of the present application, when the communication rate adaptive configuration data communication system is powered on for the first time, the write and read function verification of the FPGA storage module is performed; if the write and read function verification of the FPGA storage module fails, the system stops entering the working state; if the write and read function verification of the FPGA storage module succeeds, the system enters the working state.

[0050] In a further limitation of this embodiment, when entering the working state, the data in the FPGA storage module is cleared, the working mode of the FPGA external chip is initialized, and the initial values ​​of the data packets to be received and sent by each receiving unit and each sending module are set, as well as the network connection state is initialized.

[0051] Specifically in this embodiment, the host computer is used to send three connection establishment data packets and a PC verification data packet to the FPGA receiving module; the FPGA sending module is used to send the first FPGA verification data packet and the second FPGA verification data packet to the host computer.

[0052] Based on the same inventive concept, the present application also provides a method for using a communication rate adaptive configuration data communication system, which is applied to the communication rate adaptive configuration data communication system mentioned in the above embodiment, such as Figure 2 The flowchart shown in the figure shows a method for using the communication rate adaptive configuration data communication system, comprising the following steps:

[0053] A1. The data sent by the host computer through the network port is converted into a signal that can be read by the FPGA receiving module through the FPGA external chip, and cached in the FPGA storage module.

[0054] A2. The FPGA receiving module reads the signal cached in the FPGA storage module to determine the receiving unit and the sending unit that are adapted to the frequency to work.

[0055] A3. Receive the data packet sent by the host computer through the frequency-adaptive receiving unit in the FPGA receiving module; the FPGA receiving module includes several receiving units with different operating frequencies.

[0056] A4. Send data packets to the host computer through the frequency-adaptive sending unit in the FPGA sending module; the FPGA sending module includes several sending units with different operating frequencies.

[0057] In an exemplary embodiment of the present application, when the communication rate adaptive configuration data communication system is powered on for the first time, the method for using the communication rate adaptive configuration data communication system also includes a process of performing write and read verification on the FPGA storage module, specifically:

[0058] B1. Verify the write and read functions of the FPGA storage module. If the write and read function verification of the FPGA storage module fails, the system stops and enters the working state. If the write and read function verification of the FPGA storage module succeeds, the system enters the working state.

[0059] Specifically, in this embodiment, the data bit width of the FPGA storage module RAM is 16 bits. First, all addresses are written with data 16'H5555, and then read out to see if it is correct. If it is correct, the RAM full address is written with data 16'Haaaa again, and all are read out again after writing to see if it is consistent with the written value. If the write and read data of the FPGA storage module cannot be consistent, it is considered that there is a problem with the FPGA storage module, and it cannot pass the inspection to enter the working state. If it is verified that there is no problem with the FPGA storage module, the FPGA board will continue to execute the next step.

[0060] In a further limited embodiment of the present application, when entering the working state, the method for using the communication rate adaptive configuration data communication system also includes a process of initializing the configuration of each FPGA module and the network connection state, such as Figure 3 The flowchart shown in FIG. 1 includes the following steps:

[0061] C1. Clear the data in the FPGA storage module. That is, write data 0 to all RAM addresses in the FPGA storage module.

[0062] C2, initialize the working mode of the FPGA external chip. Specifically, this step initializes the configuration of the FPGA external chip, sets the external phy chip to the autonomous negotiation mode, and the external phy chip negotiates with the host computer PC to establish a physical connection.

[0063] C3. Set the initial value of the data packet to be received by each receiving unit.

[0064] Set the initial values ​​of the three connection establishment data packets (PDATA_A, PDATA_B, PDATA_C) and PC verification data packet (PDATA_C_D) received by each receiving unit in the FPGA receiving module when establishing communication with the PC. Each packet is 128 bytes. In this exemplary embodiment, the data frame header of the first packet PDATA_A is 32'hEB5AA5BA, the data frame header of the second packet PDATA_B is 32'hBBCBACBF, and the data frame header of the third packet PDATA_C is 32'hAACFAEFA. The data frame header of the verification data packet PDATA_C_D sent by the host computer PC is 32'hFECABCDA, and the remaining 124 bytes of each packet are 16'hAA55.

[0065] In this embodiment, there are three receiving units with different frequencies (10M receiving unit, 100M receiving unit, and 1G receiving unit) inside the FPGA receiving module. Each receiving unit must set the initial value (PDATA_A, PDATA_B, PDATA_C, PDATA_C_D), and the initial values ​​set for these three receiving units are the same. When the connection is initially established, the three units must simultaneously compare the received connection establishment data packets to determine the receiving unit and sending unit that are adapted to the frequency.

[0066] When establishing a connection, these three receiving units all receive and cache the data sent by the external phy chip. Because the host PC can only send data at one rate, only one receiving unit with one frequency in the receiving module can correctly receive and parse the data. The correctly receiving unit will give the corresponding LEN value. LEN will prohibit the unit that cannot receive data correctly from working and enable the sending unit with the corresponding frequency to work.

[0067] C4. Set the initial value of the data packet to be sent by each sending module.

[0068] Set the initial value of the FPGA verification data packet (FDATA_C_A and FDATA_C_B) sent by each sending unit of the sending module when establishing a connection with the host computer PC. Each packet is 128 bytes, the data frame header of FDATA_C_A is 32'hBE5ACCFA, the data frame header of FDATA_C_B is 32'hBFAAEE5A, and the remaining 124 bytes of each packet are 16'h55AA; in this embodiment, there are 3 sending units with different frequencies (10M sending unit, 100M sending unit and 1G sending unit) inside the FPGA sending module, and each sending unit must set the initial value of (FDATA_C_A and FDATA_C_B).

[0069] C5. Initialize the network connection state. Set the network to a disconnected state, i.e. configure LEN = 3'b000. The 10M receiving unit, 100M receiving unit, 100M receiving unit, 100M sending unit, 100M sending unit and 100M sending unit are independent units. Each unit runs independently and is located in different areas inside the FPGA. The timing and area constraints are performed independently to ensure that the burning file generated during FPGA compilation can meet the timing requirements, thereby ensuring that the receiving and sending modules can work normally.

[0070] In some implementations, the initialization configurations in steps C1 to C5 may be performed in parallel.

[0071] Specifically in this embodiment, the host computer is used to send three connection establishment data packets and a PC verification data packet to the FPGA receiving module; the FPGA sending module is used to send the first FPGA verification data packet and the second FPGA verification data packet to the host computer.

[0072] As an exemplary embodiment, after completing the above process of initializing and configuring each FPGA module and the network connection status, the method for using the communication rate adaptive configuration data communication system also includes a process of establishing a communication connection between the FPGA and the host computer PC, such as Figure 4 As shown, the process includes the following steps:

[0073] D1. Wait for the reception of three connection establishment data packets sent by the host computer through the FPGA receiving module. The FPGA receiving module (including 10M receiving unit, 100M receiving unit, and 1000M receiving unit) waits for the 3 connection establishment data packets PDATA_A, PDATA_B, and PDATA_C sent by the host computer PC at one time. Each packet is 128 bytes, and CRC check is not added to the end of the data packet. At this time, after sending the 3 connection establishment data packets, the host computer PC will wait to receive the first FPGA verification data packet sent by the FPGA.

[0074] D2. The three connection establishment data packets sent by the host computer are analyzed by each receiving unit in the FPGA receiving module to determine the receiving unit and the sending unit that adapt to the frequency. Specifically, in this step, the 10M receiving unit receives and caches the data, and then analyzes the cached data. If the data is correct, LEN=3'b001, and the 10M sending unit in the sending module is enabled to work. Alternatively, the 100M receiving unit receives and caches the data, and then analyzes the cached data. If the data is correct, LEN=3'b010, and the 100M sending unit in the sending module is enabled to work. Alternatively, the 1G receiving unit receives and caches the data, and then analyzes the cached data. If the data is correct, LEN=3'b100, and the 1G sending unit in the sending module is enabled to work.

[0075] D3. Send the first FPGA verification data packet to the host computer through the frequency-adapted sending unit, and wait for the PC verification data packet sent by the host computer through the frequency-adapted receiving unit. After receiving the 3 connection establishment data packets sent by the host computer PC and determining the frequency-adapted sending unit and receiving unit, the FPGA will send the first FPGA verification data packet to the host computer PC.

[0076] After the host computer PC receives the first FPGA verification data packet FDATA_C_A sent by FPGA, it will check whether it is correct. If it is correct, it will send the PC verification data packet PDATA_C_D. If the host computer PC times out and fails to receive the first FPGA verification data packet FDATA_C_A sent by FPGA or the received data is incorrect, it will resend 3 connection establishment data packets (PDATA_A, PDATA_B, PDATA_C) to re-establish the connection.

[0077] After the FPGA sends the first FPGA verification data packet FDATA_C_A, the receiving units with a certain frequency enabled by LEN in the FPGA receiving module (10M receiving unit, 100M receiving unit and 1G receiving unit) will enter the waiting state, waiting to receive the host computer PC verification data packet PDATA_C_D.

[0078] If the PC verification data packet sent by the host computer is received within the waiting time, step D4 is executed. If the PC verification data packet sent by the host computer is not received within the time limit, the receiving module will wait to receive the 3 packets of connection establishment data packet sent by the host computer PC to re-establish the connection. At the same time, LEN=3'b000 indicates that the network is not connected.

[0079] D4. Verify the PC verification data packet sent by the host computer.

[0080] If the PC verification data packet sent by the host computer is verified correctly, step D5 is executed. If it is received incorrectly, the receiving module will wait to receive the 3 packets of connection establishment data sent by the host computer PC to re-establish the connection. At the same time, LEN=3'b000, indicating that the network is not connected.

[0081] D5. Send the second FPGA verification data packet to the host computer through the frequency-adaptive sending unit, and make the frequency-adaptive sending unit and the receiving unit enter the normal communication state. After the receiving module correctly receives the PC verification data packet PDATA_C_D, the frequency-adaptive sending unit will send the second FPGA verification data packet FDATA_C_B to the host computer PC.

[0082] At this time, after sending the PC verification data packet PDATA_C_D, the host PC will wait to receive the second FPGA verification data packet FDATA_C_B. If it is not received within the time limit or is received incorrectly, the host PC will resend 3 packets to establish a connection (PDATA_A, PDATA_B, PDATA_C). After the FPGA sending module sends the second FPGA verification data packet FDATA_C_B, the units enabled by LEN in the receiving module and the sending module will enter normal communication with the host PC.

[0083] In a further extended embodiment, after step D5, the method for using the communication rate adaptive configuration data communication system further includes the following steps:

[0084] D6. During each data packet transmission process in normal communication status, a CRC check is performed on the data packet sent by the host computer.

[0085] If the CRC check fails three times in a row or the data packet is not received within the time limit, the process jumps to step D1 "waiting to receive three connection establishment data packets sent by the host computer through the FPGA receiving module".

[0086] That is, in normal communication, the last 2 bytes of each data packet are CRC check. If there are 3 consecutive CRC errors, the host PC will resend the connection establishment data packet (PDATA_A, PDATA_B, PDATA_C). The receiving module will wait to receive the connection establishment data packet (PDATA_A, PDATA_B, PDATA_C) sent by the host PC and re-establish the connection. At the same time, LEN = 3'b000, and the sending module will not work until it is enabled by LEN.

[0087] Each time the connection is reestablished, a new communication frequency can be determined based on the connection establishment data packet sent by the host PC for communication. The connection establishment process requires the host PC and FPGA to work together to achieve it. The process of establishing a communication connection between the host PC and the FPGA board, when the host PC is the main perspective, the operation process of establishing communication is as follows: Figure 5 As shown in the figure, when the FPGA board is the main perspective, the operation process of establishing communication is as follows Figure 6 As shown in the figure, the process of establishing communication connection between the host PC and FPGA needs to be compared with the preset value set during initialization, and the next step is determined based on the comparison result.

[0088] The scheme provided by the above-mentioned embodiment of the present application is aimed at the fact that the rate of information interaction between the digital control system and the host PC in the existing nuclear industry safety-level control system often adopts a single fixed rate, which has obvious shortcomings. A high-low speed adaptive configuration data communication system based on FPGA technology is proposed, that is, the digital control system communicates with the host PC, and multiple communication rate communications can be achieved without changing the hardware. This method effectively improves the flexibility and adaptability of the digital control system. Specifically, in the process of communicating with the host PC, different communication rates can be flexibly adopted according to the demand and data volume. At the same time, in the process of communicating with the host PC, multiple communication rates can be adopted, which can adapt to various application scenarios. In addition, when the PC system is upgraded, the digital control system can choose not to upgrade, which reduces the cost of use. Finally, the communication system provided in this embodiment is realized by FPGA technology, making system upgrades easier and more sustainable.

[0089] In an exemplary embodiment, a computer device is provided. The computer device may be a server or a terminal. The internal structure diagram thereof may be as follows: Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the function of a communication rate adaptive configuration data communication system provided in the above embodiment can be realized.

[0090] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0091] In an exemplary embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0092] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0093] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0094] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0095] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0096] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0097] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A communication rate adaptive configuration data communication system, characterized in that: It includes: an FPGA external chip, an FPGA storage module, an FPGA receiving module, an FPGA sending module and a host computer; the FPGA receiving module includes a plurality of receiving units with different operating frequencies; the FPGA sending module includes a plurality of sending units with different operating frequencies; The FPGA external chip is used to convert data sent from the host computer through the network port into signals that can be read by the FPGA receiving module and to convert the FPGA signals into data that can be transmitted back to the host computer through the network port; the FPGA storage module is used to cache the signals output by the FPGA external chip according to the data sent from the host computer through the network port; the FPGA receiving module is used to read the signals cached in the FPGA storage module, select the receiving unit and the sending unit of the adaptive frequency to work, and receive the data packets sent from the host computer through the receiving unit of the adaptive frequency; the FPGA sending module is used to use the sending unit of the adaptive frequency to send data packets to the host computer.

2. The communication rate adaptive configuration data communication system according to claim 1, characterized in that: When the communication rate adaptive configuration data communication system is powered on for the first time, the write and read functions of the FPGA storage module are verified; if the write and read function verification of the FPGA storage module fails, the system stops entering the working state; if the write and read function verification of the FPGA storage module succeeds, the system enters the working state.

3. The communication rate adaptive configuration data communication system according to claim 2, characterized in that: When entering the working state, the data in the FPGA storage module is cleared, the working mode of the FPGA external chip is initialized, and the initial values ​​of the data packets to be received and sent by each receiving unit and each sending module are set, as well as the network connection state is initialized.

4. The communication rate adaptive configuration data communication system according to claim 3, characterized in that: The host computer is used to send three connection establishment data packets and a PC verification data packet to the FPGA receiving module; the FPGA sending module is used to send a first FPGA verification data packet and a second FPGA verification data packet to the host computer.

5. A method for using a communication rate adaptive configuration data communication system, characterized in that: The configuration data communication system with adaptive communication rate as claimed in any one of claims 1 to 4 is applied, and the method for using the configuration data communication system with adaptive communication rate includes: The data sent by the host computer through the network port is converted into a signal that can be read by the FPGA receiving module through the FPGA external chip, and cached in the FPGA storage module; Read the signal cached in the FPGA storage module through the FPGA receiving module to determine the receiving unit and the sending unit of the adapted frequency to work; The data packet sent by the host computer is received by a receiving unit with an adaptive frequency in the FPGA receiving module; the FPGA receiving module includes a plurality of receiving units with different operating frequencies; The data packet is sent to the host computer through a frequency-adaptive sending unit in the FPGA sending module; the FPGA sending module includes a plurality of sending units with different operating frequencies.

6. The method for using the communication rate adaptive configuration data communication system according to claim 5, characterized in that: When the communication rate adaptive configuration data communication system is powered on for the first time, the method for using the communication rate adaptive configuration data communication system further includes: The write and read functions of the FPGA storage module are verified. If the write and read function verification of the FPGA storage module fails, the module stops entering the working state; if the write and read function verification of the FPGA storage module succeeds, the module enters the working state.

7. The method for using the communication rate adaptive configuration data communication system according to claim 6, characterized in that: After entering the working state, the method for using the communication rate adaptive configuration data communication system further includes: Clear the data in the FPGA storage module; Initialize the working mode of the FPGA external chip; Setting the initial value of the data packet to be received by each receiving unit; Set the initial value of the data packet to be sent by each sending module; Initialize network connection status.

8. The method for using the communication rate adaptive configuration data communication system according to claim 7, characterized in that: The host computer is used to send three connection establishment data packets and a PC verification data packet to the FPGA receiving module; the FPGA sending module is used to send a first FPGA verification data packet and a second FPGA verification data packet to the host computer.

9. The method for using the communication rate adaptive configuration data communication system according to claim 8, characterized in that: After initializing the network connection state, the method for using the communication rate adaptive configuration data communication system further includes: Waiting to receive three connection establishment data packets sent by the host computer through the FPGA receiving module; The three connection establishment data packets sent by the host computer are parsed by each receiving unit in the FPGA receiving module to determine the receiving unit and the sending unit of the adapted frequency; Sending a first FPGA verification data packet to the host computer through the transmitting unit of the adaptive frequency, and waiting to receive a PC verification data packet sent by the host computer through the receiving unit of the adaptive frequency; If the PC verification data packet sent by the host computer is received within the waiting time, the PC verification data packet sent by the host computer is verified; If the PC verification data packet sent by the host computer is verified correctly, a second FPGA verification data packet is sent to the host computer through the frequency-adaptive sending unit, and the frequency-adaptive sending unit and the receiving unit are put into a normal communication state.

10. The method for using the communication rate adaptive configuration data communication system according to claim 9, characterized in that: After sending a second FPGA verification data packet to the host computer through the frequency-adaptive sending unit and making the frequency-adaptive sending unit and the receiving unit enter a normal communication state, the method for using the communication rate adaptive configuration data communication system further includes: During each data packet transmission process in the normal communication state, a CRC check is performed on the data packet sent by the host computer; If the CRC check fails three times in a row or the data packet is not received within the time limit, jump to step "waiting to receive three connection establishment data packets sent by the host computer through the FPGA receiving module".

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