An encoding device, a decoding device, an encoding method, and a decoding method

Abstract

The application provides an encoding device, a decoding device, an encoding method and a decoding method. The encoding device comprises a pre-interleaving module, a symbol distribution module, N RS FEC encoding modules and a symbol interleaving module. The pre-interleaving module performs a first interleaving operation on an alignment sequence in a received transmission data stream, so that the alignment sequence is changed in a symbol-granularity original bit sequence. The symbol distribution module distributes the transmission data stream after the first interleaving operation to the N RS FEC encoding modules. Each RS FEC encoding module performs RS FEC encoding on the received transmission data stream, and the N RS FEC encoding modules obtain N transmission encoding data streams. The symbol interleaving module performs a second interleaving operation on the N transmission encoding data streams, and obtains N transmission channel data streams. Each transmission channel data stream is sent to one of the N physical channels. After the second interleaving operation, the original bit sequence of the alignment sequence is restored.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to an encoding device, a decoding device, an encoding method and a decoding method. BACKGROUND

[0002] InfiniBand (IB) protocol is a high-speed data transmission technology, mainly used in high-performance computing, data centers, storage systems and other occasions requiring fast and efficient communication. IB protocol can realize fast and efficient communication between servers, storage devices and other computing systems, and the design goal is to provide low-latency, high-bandwidth and scalable data transmission services to meet the needs of large-scale computing and data transmission. SUMMARY

[0003] The application aims to provide an encoding device, a decoding device, an encoding method and a decoding method, and aims to solve the problems of large delay in the PCS encoding process of the IB network and the need for memory storage in the prior art.

[0004] According to a first aspect of the application, an encoding device is provided, comprising a pre-interleaving module, a symbol distribution module, N RSFEC encoding modules and a symbol interleaving module.

[0005] The pre-interleaving module is configured to perform a first interleaving operation on an alignment sequence in a received transmission data stream, so that the alignment sequence is changed in terms of original bit sequence of a symbol granularity.

[0006] The symbol distribution module is configured to distribute the transmission data stream after the first interleaving operation to the N RSFEC encoding modules.

[0007] Each of the RSFEC encoding modules is configured to perform RSFEC encoding on the received transmission data stream, and N RSFEC encoding modules encode N transmission encoding data streams.

[0008] The symbol interleaving module is configured to perform a second interleaving operation on the N transmission encoding data streams to obtain N transmission channel data streams, and each transmission channel data stream is sent to one of the N physical channels; wherein the original bit sequence of the alignment sequence is restored after the second interleaving operation.

[0009] In an optional embodiment, the symbol distribution module distributes the transmission data stream in a symbol granularity in sequence and in turn, so that the N transmission data streams formed after distribution enter the N RSFEC encoding modules in parallel.

[0010] In an optional embodiment, the second interleaving operation is such that each of the N transmit channel data streams comprises data from a different RS FEC encoding module, and the number of symbols of data from each of the RS FEC encoding modules is equal.

[0011] In an optional embodiment, the alignment sequence comprises N channel identifier symbols arranged in order, and each of the channel identifier symbols identifies one of the physical channels; after the first interleaving operation, the original order of the N channel identifier symbols is disrupted; after the symbol distribution module distributes the symbols, the N channel identifier symbols are distributed to N RS FEC encoding modules respectively, and after the second interleaving operation, different channel identifier symbols are in different transmit channel data streams, and the transmit channel data stream corresponding to each channel identifier symbol is sent to the same physical channel as the physical channel identified by the channel identifier.

[0012] According to a second aspect of the present application, a decoding apparatus is provided, comprising: a symbol aggregation module, N RS FEC decoding modules, and a symbol deinterleaving module;

[0013] The symbol deinterleaving module is configured to receive N receive channel data streams from N physical channels, and perform a third interleaving operation on the N receive channel data streams, and the N receive channel data streams after the third interleaving operation are transmitted to the N RS FEC decoding modules respectively; the N receive channel data streams are obtained after a second interleaving operation of an encoding apparatus at a transmitting end, and the third interleaving operation and the second interleaving operation are inverse operations of each other;

[0014] The N RS FEC decoding modules are configured to perform RS FEC decoding on the N receive channel data streams after the third interleaving operation;

[0015] The symbol aggregation module is configured to aggregate the N receive channel data streams after decoding into one receive data stream.

[0016] In an optional embodiment, the symbol aggregation module receives data from the N RS FEC decoding modules in order and in turn in symbol granularity, and aggregates the data into the receive data stream.

[0017] In an optional embodiment, each of the N receive channel data streams comprises data from a different physical channel, and the number of symbols of data from each of the physical channels is equal.

[0018] According to a third aspect of the present application, a coding method is provided, comprising:

[0019] receiving a transmit data stream;

[0020] performing a first interleaving operation on the alignment sequence in the sending data stream, so that the alignment sequence is changed in original bit sequence with symbol granularity;

[0021] distributing the sending data stream after the first interleaving operation into N sending data streams in parallel;

[0022] performing RS FEC encoding on each of the N sending data streams in parallel to obtain N sending encoded data streams;

[0023] performing a second interleaving operation on the N sending encoded data streams to obtain N sending channel data streams, each of which is sent to one of the N physical channels; wherein the original bit sequence of the alignment sequence after the second interleaving operation is restored.

[0024] In an optional embodiment, distributing the sending data stream after the first interleaving operation into N sending data streams in parallel comprises:

[0025] the sending data stream after the first interleaving operation is distributed in turn in sequence with symbol granularity to form the N sending data streams in parallel;

[0026] converging the N receiving channel data streams after decoding into one receiving data stream comprises:

[0027] acquiring data from the N receiving channel data streams in turn in sequence with symbol granularity and converging the data into the receiving data stream.

[0028] In an optional embodiment, each of the N sending channel data streams comprises data from a different one of the N sending encoded data streams, and the number of symbols of data from each of the N sending encoded data streams is equal.

[0029] In an optional embodiment, the alignment sequence comprises N channel identifier symbols arranged in sequence, each of which identifies one of the physical channels; the original sequence of the N channel identifier symbols is changed after the first interleaving operation; the N channel identifier symbols are distributed to the N sending data streams respectively, and after the second interleaving operation, different channel identifier symbols are in different sending channel data streams, and the sending channel data stream corresponding to each channel identifier symbol is sent to the same physical channel as the physical channel identified by the channel identifier.

[0030] According to a fourth aspect of the present application, a decoding method is provided, further comprising:

[0031] receive N-way receive channel data streams from N physical channels, and perform a third interleaving operation on the N-way receive channel data streams; the N-way receive channel data streams are obtained after a second interleaving operation of an encoding device at a sending end, and the third interleaving operation and the second interleaving operation are inverse operations of each other;

[0032] perform RSFEC decoding on the N-way receive channel data streams after the third interleaving operation;

[0033] converge the decoded N-way receive channel data streams into one receive data stream.

[0034] In an optional implementation, converging the decoded N-way receive channel data streams into one receive data stream comprises:

[0035] receiving data from the N RSFEC decoding modules in sequence and in turn in symbol granularity, and converging the data into the receive data stream.

[0036] In an optional implementation, each of the N-way receive channel data streams comprises data from different physical channels, and the number of symbols of the data from each physical channel is equal.

[0037] Compared with related technologies, the technical solution of the present application has the following advantages:

[0038] The present application adopts a parallel RSFEC encoding and decoding module structure, cancels the memory storage requirement introduced before and after encoding and decoding due to data order preservation, and further introduces the processing procedures of a symbol interleaving module and a pre-interleaving module of an AS sequence, so that the error correction capability and channel synchronization function on each physical channel are not affected. The newly introduced processing procedure does not introduce additional delay. Although this way disrupts the original order of data, the data can still be correctly recovered after decoding. Compared with the serial encoding and decoding mode in related technologies, the present application has the following advantages:

[0039] 1. The delay of high-rate RSFEC encoding and decoding is greatly reduced, and memory resources are saved.

[0040] 2. The newly introduced AS pre-interleaving and symbol interleaving processing does not introduce delay, and has simple logic and good scalability.

[0041] 3. After symbol interleaving, the data streams of the physical channels correspond to different encoding and decoding modules in symbol granularity. Compared with a serial distribution structure, the present application has stronger anti-burst error capability.

[0042] Other features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the application. The purposes and other advantages of the present application will be realized and attained by the structure and processes particularly pointed out in the description and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings described below are only some embodiments of the present application, and the ordinary skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0044] Figure 1 is a schematic diagram of the architecture of a serial encoding device according to the related art in the data sending direction.

[0045] Figure 2 is a schematic diagram of the architecture of an encoding device according to the related art.

[0046] Figure 3 is a schematic diagram of the architecture of an encoding device according to an exemplary embodiment of the present application in the data sending direction.

[0047] Figure 4 is a schematic diagram of the effect of a symbol interleaving process according to an exemplary embodiment of the present application.

[0048] Figure 5 is a schematic diagram of the effect of a pre-interleaving process according to an exemplary embodiment of the present application.

[0049] Figure 6 is a schematic diagram of the architecture of a decoding device according to the related art.

[0050] Figure 7 is a schematic diagram of the flow of an encoding method according to an exemplary embodiment of the present application.

[0051] Figure 8 is a schematic diagram of the flow of a decoding method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the ordinary skilled in the art without any creative effort fall within the protection scope of the present application.

[0053] Low latency is a key performance indicator in IB network, and RSFEC (Reed-Solomon code-based forward error correction coding) as a link in the IB network physical layer signal processing, the calculation, timing pressure is greater, will occupy more processing delay, so the delay of the processing link is controlled and compressed, which will obviously improve the overall delay performance of the system.

[0054] As shown in Figure 1 , in the IB protocol, the data stream is scrambled, 64 / 66b encoded, transcoded, and then serially enters the RSFEC codec. The encoded data is then distributed to lanes according to the symbol.

[0055] This serial processing method cannot be completed by a single RSFEC codec due to the speed of calculation and the timing constraints of the backend physical implementation in the face of high-rate and high-throughput scenarios (such as x8 NDR, with a processing flow of 800 Gbps). Therefore, in engineering implementation, multiple RSFEC codecs are usually used to solve this problem, but inevitably, there will be overhead in terms of resources, area, and processing delay.

[0056] A feasible implementation is to distribute the data stream according to the granularity of the FEC (forward error correction coding technology) block, combine the bit width conversion, distribute the large flow into N small flows, and correspond to multiple RSFEC codecs for ping-pong processing. The N-way data stream after coding is aggregated into a large flow output according to the order of the FEC block, and finally distributed to multiple physical lanes according to the symbol, as shown in Figure 2 Figure 2 Only the data sending process is shown, and the receiving process is the reverse process, which will not be described again.

[0057] This implementation can not only meet the requirements of serial RSFEC codec processing, but also solve the processing bottleneck problem of RSFEC codec in large flow scenarios, but at the same time, the following problems will exist:

[0058] 1. As shown in Figure 2 ①, when distributing the FEC block, due to the fast inlet flow, the flow output to the RSFEC codec is slow, and the data stream needs to be temporarily stored in memory, which will increase the delay.

[0059] 2. As shown in Figure 2 ②, when aggregating the FEC block, due to the slow output flow of a single RSFEC codec, and at the same time, to ensure the original large flow output, the data also needs to be stored in memory, which will increase the delay.

[0060] ​The encoding direction and decoding direction processing procedures of the RSFEC codec are symmetrical, and the delay and memory consumption mentioned above are doubled.

[0061] Therefore, in view of the large delay and large area problems existing in the engineering implementation of the high-rate serial RSFEC codec, the application proposes a coding and decoding device for implementing a parallel RSFEC codec based on the IB protocol.

[0062] The core idea of the coding and decoding device is to place the symbol distribution operation in front, obtain N parallel data streams, and independently operate the corresponding RSFEC codecs in parallel. In order to ensure that the error correction capability of each physical channel lane in the receiving direction is not affected, a symbol interleaving process is introduced. At the same time, in order to ensure that the channel synchronization process in the receiving direction is not affected, an AS (Align sequence, alignment sequence) pre-interleaving process is further introduced. In this way, the memory access requirement introduced before and after coding due to data order preservation can be omitted, thereby greatly reducing the processing delay and reducing the use of memory, and the area of the implemented chip can be reduced.

[0063] Referring to Figure 3 The application exemplarily proposes a coding device, which comprises a pre-interleaving module, a symbol distribution module, N RSFEC encoding modules, and a symbol interleaving module.

[0064] The pre-interleaving module is configured to perform a first interleaving operation on the alignment sequences in the received transmission data stream, so that the original order of the N channel identifier symbols in the alignment sequences is changed.

[0065] The symbol distribution module is configured to distribute the transmission data stream after the first interleaving operation to the N RSFEC encoding modules.

[0066] Each RSFEC encoding module is configured to perform RSFEC encoding on the received transmission data stream, and the N RSFEC encoding modules encode to obtain N transmission encoding data streams.

[0067] The symbol interleaving module is configured to perform a second interleaving operation on the N transmission encoding data streams to obtain N transmission channel data streams, and each transmission channel data stream is sent to one of the N physical channels. After the second interleaving operation, each transmission channel data stream contains one channel identifier symbol of the alignment sequence, and the channel identifier symbols in the N channel data streams are arranged in the original order according to the order of the corresponding N physical channels.

[0068] Exemplarily, from the overall point of view, the application adopts a parallel processing structure, Figure 3 The TX processing procedure (i.e., the processing procedure in the transmission direction) is shown, and the RX processing procedure (i.e., the processing procedure in the receiving direction) is shown. Figure 3For example, the symbol distribution module at ② distributes the symbols of each physical lane to the RSFEC encoding module in advance, and does not further split the FEC block before encoding, but only distributes the symbols in granularity, and the distributed data streams of each lane are transmitted into the RSFEC encoding module in parallel and are encoded.

[0069] The symbol interleaving module at ③ performs symbol interleaving on each lane of the encoded data stream before sending it to each physical lane. After interleaving, the data on each physical lane comes from different RSFEC encoding modules, which ensures that the error correction capability of each physical lane at the receiving end is not affected, and even has stronger error correction capability for burst reception errors.

[0070] For example, after receiving the transmitted data stream at the receiving end, synchronization and rearrangement operations need to be performed according to the AS (Align sequence) sequence. The interleaving operation performed by the symbol interleaving module will disrupt the original order of the AS sequence. To ensure that the AS sequence is not affected after interleaving, the present application adds a pre-interleaving module (see Figure 3 at ① of FIG. 1) before the RSFEC encoding module, which performs a first interleaving operation on the AS sequence, so that after the second interleaving operation of the symbol interleaving module, the AS sequence can recover the original order. That is, at the pre-interleaving module, the original bit sequence of the alignment sequence in the transmitted data stream is disrupted, and after the second interleaving operation at the symbol interleaving module, the original bit sequence of the disrupted alignment sequence is recovered. Here, the original bit sequence recovered can be understood as the order of the alignment sequence transmitted to each physical lane after the first interleaving operation and the second interleaving operation being consistent with the order of the alignment sequence directly transmitted to the physical lane without performing the first interleaving operation and the second interleaving operation. Since the purpose of adding the pre-interleaving module is to maintain the original bit sequence of the AS sequence after the second interleaving operation of the symbol interleaving module, the first interleaving operation performed by the pre-interleaving module is related to the second interleaving operation, and can be designed based on the specific interleaving process of the second interleaving operation.

[0071] For example, as can be seen from Figure 3 , the AS sequence is inserted by the corresponding circuit module before the transmitted data stream enters the pre-interleaving module. Figure 3 The encoding device shown in FIG. 1 is a circuit in the PCS (Physical Coding Sublayer) of the IB network. Before the pre-interleaving module, there are also scrambling modules, 64 / 66B encoding modules, transcoding modules, and AS insertion modules, etc. The details of the above modules can be referred to the related art, and the present disclosure does not make specific limitations thereto.

[0072] In some alternative embodiments, the symbol distribution module distributes the transmission data stream in order by symbol granularity, so that the N transmission data streams formed after distribution enter the N RSFEC encoding modules in parallel.

[0073] Exemplarily, the symbol distribution module distributes by symbol granularity, and the transmission data streams enter the RSFEC encoding modules in parallel and complete encoding. The symbol herein can be understood as a piece of data bits with a certain length, such as 10 bits of data. The distribution by symbol granularity can be understood as distributing the transmission data stream in order by 10 bits as a group to the N physical channels line0-lineN-1. For example, the first 10 bits of the transmission data stream are distributed to the first RSFEC encoding module Rsfec enc0, the second 10 bits are distributed to the second RSFEC encoding module Rsfec enc1, and so on, and the Nth 10 bits are distributed to the Nth RSFEC encoding module Rsfec encN-1. Starting from the N+1th 10 bits, the first RSFEC encoding module Rsfec enc0 is used again for transmission, and so on.

[0074] In some alternative embodiments, the second interleaving operation is such that each of the N transmission channel data streams includes data from different RSFEC encoding modules, and the number of symbols of data from each RSFEC encoding module is equal.

[0075] Exemplarily, the second interleaving operation is located after RSFEC encoding. Taking an RSFEC encoding module with a parallel degree of 160 bits as an example, in an x8 mode, 8 RSFEC encoding modules are used to perform parallel encoding processing, and each RSFEC encoding module outputs 16 symbols of data (1 symbol of data corresponds to 10 bits) per single shot. The interleaving result of the output data of the 8 RSFEC encoding modules is as shown in FIG. 8. Figure 4 It should be noted that, Figure 4 Only one clock cycle (i.e., single shot) of data processed is schematically shown.

[0076] Wherein, E0-7 is the number of RSFEC encoding module, the same number of symbols are output by the same RSFEC encoding module, s0-15 is the symbol number within a single shot, s0 is the lowest bit symbol. Wherein the number of RSFEC encoding module is the same as the number of physical channels, the N-way sending encoded data stream after RSFEC encoding module is obtained after the symbol interleaving module N-way sending channel data stream and physical channel one-to-one correspondence, that is, the first sending channel data stream corresponds to the first physical channel, and is sent out through the first physical channel, the second sending channel data stream corresponds to the second physical channel, and is sent out through the second physical channel, …, the N-way sending channel data stream corresponds to the Nth physical channel, and is sent out through the Nth physical channel.

[0077] From Figure 4 The symbol block shown in bold in the above table can be seen that after the second interleaving operation, the output data sent to the first physical channel Lane0 comes from all 8 RSFEC encoding modules, and the number of symbols provided by each RSFEC encoding module is equal. In this embodiment, the purpose of the second interleaving operation is to sequentially correspond different RSFEC encoding modules according to symbol granularity for the continuous data stream on each physical channel, so that at the receiving side, when the receiving data on one or more physical channels appears burst error, all 8 RSFEC decoders can simultaneously share the burst error, thus achieving strong anti-burst error capability.

[0078] For Figure 4The second interleaving operation is described as follows: First, the first symbol output by each RSFEC encoding module is sent sequentially to its corresponding physical channel. That is, the first physical channel lane0 receives the first symbol s0 / E0 output by the first RSFEC encoding module, the second physical channel lane1 receives the first symbol s0 / E1 output by the second RSFEC encoding module, and so on, and the eighth physical channel lane7 receives the first symbol s0 / E7 output by the eighth RSFEC encoding module. Then, starting from the second symbol, the first channel (lane0) receives the second symbol (s1 / E1) output by the second RSFEC encoding module; the second physical channel (lane1) receives the second symbol (s1 / E2) output by the third RSFEC encoding module, and so on. The eighth physical channel (lane7) receives the second symbol (s1 / E0) output by the first RSFEC encoding module. Starting from the third symbol, the first channel (lane0) receives the third symbol (s2 / E2) output by the third RSFEC encoding module, and the second physical channel (lane1) receives the fourth RSFEC symbol. The third symbol s2 / E3, ..., output by the encoding module, the eighth physical channel lane7 receives the third symbol s2 / E1 output by the second RSFEC encoding module. That is, starting from the second symbol, in each round, the nth channel receives the mth symbol output by the (n+m-1)th RSFEC encoding module, where m is the number of the symbol received by the current channel in the current round. When the RSFEC encoding module number n+m-1 is greater than 8, the number should be returned to (n+m-1)-8. When the number n+m-1 is greater than 16, the number should be returned to (n+m-1)-16.

[0079] It is understandable that the inverse operation of the second interleaving operation performed by the symbol deinterleaving module is the operation on... Figure 4 The data shown in the right figure is processed to obtain the data shown in the left figure. The data received by the symbol deinterleaving module is as follows: Figure 4 As shown in the right figure, the first symbol received from each physical channel is sent to each RSFEC encoding module in a one-to-one correspondence. Starting from the second symbol, in each round, the m-th symbol received from the n-th channel is sent to the (n+m-1)-th RSFEC decoding module, where m is the number of the symbol received in the current round by the current channel. When the number n+m-1 is greater than 8, the number should be returned to (n+m-1)-8. When the number n+m-1 is greater than 16, the number should be returned to (n+m-1)-16.

[0080] In some embodiments, the alignment sequence includes N channel identifiers arranged in order, and each channel identifier identifies one of the physical channels; after the first interleaving operation, the original order of the N channel identifiers is shuffled; after distribution by the symbol distribution module, the N channel identifiers are distributed to N RSFEC encoding modules respectively, and after the second interleaving operation, different channel identifiers are in different transmit channel data streams, and the transmit channel data stream corresponding to each channel identifier is sent to the same physical channel as the physical channel identified by the channel identifier.

[0081] For example, the AS pre-interleaving operation is performed before symbol distribution in this application. Taking the x8 mode as an example, the AS sequence in this mode consists of AM s0~4, ld0~7 repeated 8 times per symbol, and several pad (space padding) values. The original bit order of this alignment sequence, the order after the first interleaving operation, and the symbol bit order corresponding to the physical channel after the second interleaving operation are as follows: Figure 5 As shown.

[0082] Among them, Figure 5 At point ①, after the first interleaving operation, the order of the lds (i.e., channel identifiers) within the AS is temporarily shuffled. The channel identifier is a 10-bit data set used to identify physical channels. Taking x8 mode as an example, there are 8 channel identifiers, each identifying one of the 8 channels. ld0 identifies the first logistics channel, ..., ld7 identifies the 8th physical channel. At point ②, after the second interleaving operation, the original bit order of the AS sequence encoded by the RSFEC encoding module is restored. At point ③, taking the first physical channel, Lane0, as an example, the AS sequence after the first and second interleaving operations is output on Lane0 with the same bit order as the original sequence. This ensures proper synchronization and correct rearrangement of the physical channels during data reception at the data receiving end.

[0083] It should be noted that, Figure 5The data stream shown in the original AS symbol bit sequence and the pre-interleaved AS symbol bit sequence is actually one data stream. In order to facilitate description, the one data stream is shown as data arranged in rows and columns in the figure, the number of rows is the same as the number of physical channels and the number of RSFEC encoding modules, wherein s0-s7 are the numbers of symbols for convenience of description, and E0-E7 are the numbers of RSFEC encoding modules. Each data in the one data stream is a symbol, that is, 10 bits, such as AM s0-AM s7, ld0-ld7, pad0, dat1-dat4, which are each a 10-bit symbol. The arrangement order of the symbols in the one data stream is: AM s0 in the first column of the first row from the right to AM s0 in the eighth column of the first row, then AM s1 in the second column of the first row to AM s1 in the eighth column of the first row, and so on, ld0 in the sixth column of the first row to ld7 in the eighth column of the first row, Figure 5 The pad0 in the seventh column of the first row to the third row shown in the figure is a padding bit, and dat0 in the seventh column of the fourth row to dat4 in the eighth column is service data after the AS sequence. This is only an example for illustration. In actual application, a large amount of service data will continue to follow after the seventh column, which is not shown in the figure.

[0084] As described above, the purpose of the pre-interleaving, that is, the first interleaving operation, is to make the arrangement order of the channel identifier symbols in the AS sequence before pre-interleaving and after symbol interleaving, that is, the second interleaving operation, consistent, that is, the original bit sequence of the channel identifier symbols in the AS sequence and the channel identifiers of each sending channel data stream to which the channel identifier symbols are distributed after the second interleaving operation are sorted according to the actual corresponding physical channels, and the order is consistent. For example, the original bit sequence of the eight channel identifier symbols in the AS sequence is ld0-ld7, and after the second interleaving operation, ld0-ld7 are respectively distributed to the sending channel data streams corresponding to the first physical channel lane0 to the eighth physical channel lane7, and the order of the two is consistent.

[0085] Therefore, the pre-interleaving, that is, the first interleaving operation, only needs to disorder the order of ld0-ld7 in the AS sequence, and the principle of disordering is to restore the original order after the second interleaving operation. For example Figure 5In the embodiment, the 6th symbol of the 1st physical channel after the second interleaving operation is from the data output by the 6th RS FEC encoding module, i.e., ldO / E5 in the figure. Therefore, for the AS sequence, in order to maintain the original bit sequence of the channel symbol identifier in the AS sequence, the 6th symbol of the 1st physical channel after the second interleaving operation should be ldO, and therefore, in the first interleaving operation, ld0 needs to be exchanged to the position of the 6th row, and ld1 after ld0 is exchanged to the next row of the 6th row, i.e., the 7th row, ld2 is exchanged to the 8th row, and the remaining channel identifier symbols starting from ld3 are exchanged to the 1st row to the 5th row. It should be noted that, Figure 5 The pre-interleaving process is only an example, and the specific pre-interleaving operation depends on the symbol interleaving operation, i.e., the second interleaving operation; and Figure 4 The second interleaving operation shown is also only an example, as long as each channel sending data after the second interleaving operation contains data from all RS FEC encoding modules, and the number of symbols from each RS FEC encoding module is equal, and the AS sequence sent on each physical channel satisfies the predetermined bit sequence.

[0086] The application adopts the parallel RS FEC encoding and decoding module structure, cancels the memory storage requirement introduced before and after encoding and decoding due to data sequence preservation, and further introduces the processing process of the symbol interleaving module and the AS sequence pre-interleaving module to make the error correction capability and channel synchronization function on each physical channel not be affected. The newly introduced processing process does not introduce additional delay. Although this way disrupts the original order of data, it can still be correctly recovered after decoding. Compared with the serial encoding and decoding mode in the related art, the application has the following advantages:

[0087] 1. The delay of high-rate RS FEC encoding and decoding is greatly reduced, and the memory resources are saved.

[0088] 2. The newly introduced AS pre-interleaving and symbol interleaving processing do not introduce delay, and the logic is simple and has good scalability.

[0089] 3. After symbol interleaving, the data stream of the physical channel is corresponded to different encoding and decoding modules in symbol granularity. Compared with the serial distribution structure, the application has stronger anti-burst error capability.

[0090] Correspondingly, referring to Figure 6 The application exemplarily proposes a decoding device, which is used for decoding the data stream of the RS FEC encoding and decoding device. Figure 3The encoding device shown corresponds to the actual application, wherein the encoding device encodes data at a data sending end, and the decoding device decodes data encoded by the encoding device and sent to the data receiving end at a data receiving end. The decoding device comprises a symbol aggregation module, N RS FEC decoding modules, and a symbol deinterleaving module.

[0091] The symbol deinterleaving module is configured to receive N-way receive channel data streams from the N physical channels, and perform a third interleaving operation on the N-way receive channel data streams. The N-way receive channel data streams after the third interleaving operation are transmitted to the N RS FEC decoding modules respectively. The N-way receive channel data streams are obtained after the second interleaving operation of the encoding device at the sending end. The third interleaving operation and the second interleaving operation are inverse operations of each other.

[0092] The N RS FEC decoding modules are configured to perform RS FEC decoding on the N-way receive channel data streams after the third interleaving operation.

[0093] The symbol aggregation module is configured to aggregate the decoded N-way receive channel data streams into one receive data stream.

[0094] Exemplarily, in the RX direction, the decoding device comprises a symbol aggregation module, N RS FEC decoding modules, and a symbol deinterleaving module. The operation of the symbol deinterleaving module and the symbol interleaving module is inverse of each other. The operation of the symbol aggregation module and the symbol distribution module is inverse of each other. The operation of the RS FEC decoding module and the RS FEC encoding module is inverse of each other. The aggregation process of the symbol aggregation module is as follows: starting from the first receive channel data stream, data is received from the N receive channel data streams in symbol granularity in turn, and the receiving is performed in a loop. The received data is combined into one receive data stream in the order of receiving. For example, 10-bit data in the lowest position is received from the first receive channel data stream, 10-bit data in the lowest position is received from the second receive channel data stream, and so on. If the width of each channel is greater than 10 bits, 10-bit data in the next lowest position is received from the first receive channel data stream, and so on, until all data is received. The one receive data stream obtained by the symbol aggregation module can be sent to a subsequent circuit, such as a circuit module for deleting AS sequences. It can be understood that the order of the AS alignment sequence in the one receive data stream is not the original bit sequence, but since the AS sequence will be deleted in the subsequent circuit module, a circuit module for performing the inverse process of the pre-interleaving module is not provided in the RX direction. The third interleaving operation performed by the symbol deinterleaving module is inverse of the second interleaving operation performed by the symbol interleaving module of the encoding device. Therefore, the specific details of the third interleaving operation can be referred to the description of the encoding device above.

[0095] In some optional embodiments, the symbol aggregation module receives data from the N RS FEC decoding modules in turn in order with symbol granularity, and aggregates into a received data stream.

[0096] Exemplarily, the symbol aggregation module aggregates in symbol granularity as well. Here, a symbol can be understood as a piece of data bits with a certain length, such as 10 bits of data. Aggregation in symbol granularity can be understood as receiving data from the RS FEC decoding modules Rsfec dec0-N-1 in turn in symbol granularity, such as receiving one symbol (i.e. 10 bits of data) from the first RS FEC decoding module Rsfec dec0, receiving one symbol from the second RS FEC decoding module Rsfec dec 1,..., receiving one symbol from the Nth RS FEC decoding module Rsfec decN-1, and then starting from the first decoding module Rsfec dec0 again for receiving, and so on. The received symbols are aggregated into one data stream.

[0097] In some optional embodiments, each of the N received channel data streams after the third interleaving operation includes data from different physical channels, and the number of symbols of data from each physical channel is equal.

[0098] Exemplarily, the structure and data processing flow of the decoding device are just opposite to those of the encoding device. Therefore, each of the N received channel data streams after the third interleaving operation includes data from different physical channels, that is, the third interleaving operation actually exchanges data in symbol granularity for the original N received channel data streams, so that each of the received channel data streams after the third interleaving operation includes data from all physical channels, and for each of the received channel data streams after the third interleaving operation, the number of symbols of data from each physical channel is equal.

[0099] Details of the decoding device in this embodiment can be referred to the description of the encoding device above, and will not be described here again.

[0100] Correspondingly, referring to FIG. 7, the present application exemplarily provides an encoding method, comprising: Figure 7

[0101] In step S701, a sending data stream is received.

[0102] In step S702, a first interleaving operation is performed on an alignment sequence in the sending data stream, so that the original bit sequence of the alignment sequence in symbol granularity is changed.

[0103] In step S703, the sending data stream after the first interleaving operation is distributed into N sending data streams in parallel. ​

[0104] In step S704, RS FEC encoding is performed on each of the N parallel sending data streams to obtain N parallel sending encoded data streams.

[0105] In step S705, a second interleaving operation is performed on the N parallel sending encoded data streams to obtain N parallel sending channel data streams, each of which is sent to one of the N physical channels; after the second interleaving operation, the original bit sequence of the alignment sequence is restored.

[0106] In some optional embodiments, the sending data stream after the first interleaving operation is distributed in parallel into N parallel sending data streams, including:

[0107] The sending data stream after the first interleaving operation is distributed in sequence in symbol granularity to form N parallel sending data streams.

[0108] In some optional embodiments, each of the N parallel sending channel data streams includes different ones of the N parallel sending encoded data streams, and the number of symbols of data from each of the parallel sending encoded data streams is equal.

[0109] In some optional embodiments, the alignment sequence includes N channel identifier symbols arranged in sequence, and each channel identifier symbol identifies one of the physical channels; after the first interleaving operation, the original order of the N channel identifier symbols is disturbed; the N channel identifier symbols are respectively distributed to the N parallel sending data streams, and after the second interleaving operation, different channel identifier symbols are in different parallel sending channel data streams, and the physical channel to which the sending channel data stream corresponding to each channel identifier symbol is sent is the same as the physical channel identified by the channel identifier.

[0110] The above method can be implemented by the encoding device provided in the above embodiments, and the specific implementation manner can be referred to the description of the encoding device in the above embodiments, which will not be described here.

[0111] Correspondingly, referring to FIG. 8, Figure 8 The decoding method provided by the present application includes:

[0112] In step S801, N parallel receiving channel data streams are received from N physical channels, and a third interleaving operation is performed on the N parallel receiving channel data streams; the N parallel receiving channel data streams are obtained after the second interleaving operation of the encoding device at the sending end, and the third interleaving operation and the second interleaving operation are inverse operations of each other.

[0113] In step S802, RS FEC decoding is performed on the N parallel receiving channel data streams after the third interleaving operation.

[0114] In step S803, the decoded N-channel data streams are converged into one received data stream.

[0115] In some optional embodiments, converging the decoded N-channel data streams into one received data stream comprises:

[0116] sequentially receiving data from the N RS FEC decoding modules in turn in symbol granularity, and converging the data into a received data stream.

[0117] In some optional embodiments, each of the N-channel data streams comprises data from different physical channels, and the number of symbols of data from each physical channel is equal.

[0118] The above method can be implemented by the decoding apparatus provided in the above embodiments, and the specific implementation manners can refer to the description of the decoding apparatus in the above embodiments, which will not be repeated here.

[0119] Correspondingly, the present application also exemplarily provides a coding and decoding apparatus, which comprises the encoding apparatus as described above, and the decoding apparatus as described above.

[0120] Correspondingly, the present application also exemplarily provides a coding and decoding method, which comprises the encoding method steps as described above, and the decoding method steps as described above.

[0121] The above coding and decoding apparatus comprises the encoding apparatus and the decoding apparatus provided in the above embodiments, and the specific details can refer to the description of the encoding apparatus and the decoding apparatus in the above embodiments, which will not be repeated here.

[0122] The above coding and decoding method is implemented by the encoding apparatus and the decoding apparatus provided in the above embodiments, and the specific details can refer to the description of the encoding apparatus and the decoding apparatus in the above embodiments, which will not be repeated here.

[0123] It can be understood that the circuit structure, name and parameter described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to the use needs, and the concept of the present application should not be limited to the specific details of the above examples.

[0124] Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An encoding device, characterized in that, include: The system consists of a pre-interleaving module, a symbol distribution module, N RSFEC coding modules, and a symbol interleaving module. The pre-interleaving module is used to perform a first interleaving operation on the alignment sequence in the received transmitted data stream, so that the original bit order of the alignment sequence is changed at the symbol granularity. The symbol distribution module is used to distribute the transmitted data stream after the first interleaving operation to the N RSFEC encoding modules; Each of the RSFEC encoding modules is used to perform RSFEC encoding on the received transmit data stream, and N RSFEC encoding modules encode N transmit encoded data streams; The symbol interleaving module is used to perform a second interleaving operation on the N transmitted encoded data streams to obtain N transmitted channel data streams, each of which is sent to one of the N physical channels; wherein, after the second interleaving operation, the original bit order of the alignment sequence that was scrambled is restored; The symbol distribution module distributes the transmitted data streams sequentially in turn, with symbols as the granularity, so that the N transmitted data streams formed after distribution enter the N RSFEC encoding modules in parallel.

2. The encoding device according to claim 1, characterized in that, The second interleaving operation causes each of the N transmit channel data streams to include data from different RSFEC encoding modules, and the number of symbols in the data from each RSFEC encoding module is equal.

3. The encoding device according to claim 2, characterized in that, The alignment sequence includes N channel identifiers arranged in order, and each channel identifier identifies one of the physical channels; After the first interleaving operation, the original order of the N channel identifier symbols is shuffled; After being distributed by the symbol distribution module, the N channel identifiers are distributed to the N RSFEC encoding modules respectively. After the second interleaving operation, the different channel identifiers are in different transmit channel data streams, and the physical channel to which the transmit channel data stream corresponding to each channel identifier is sent is the same as the physical channel identified by the channel identifier.

4. A decoding device, characterized in that, The decoding device is used to decode the N transmission channel data streams obtained by the encoding device as described in any one of claims 1-3, and includes: a symbol aggregation module, N RSFEC decoding modules and a symbol deinterleaving module; The symbol deinterleaving module is used to receive N data streams from N physical channels and perform a third interleaving operation on the N data streams. The N data streams after the third interleaving operation are then transmitted to the N RSFEC decoding modules. The N data streams are obtained after the second interleaving operation of the encoding device at the transmitting end. The third interleaving operation is the inverse of the second interleaving operation. The N RSFEC decoding modules are used to perform RSFEC decoding on the N received channel data streams after the third interleaving operation. The symbol aggregation module is used to aggregate the decoded N-channel receive data streams into a single receive data stream.

5. The decoding device according to claim 4, characterized in that, The symbol aggregation module receives data from the N RSFEC decoding modules in sequence, using symbols as the granularity, and aggregates them into the received data stream.

6. The decoding device according to claim 4 or 5, characterized in that, Each of the N receiving channel data streams includes data from different physical channels, and the number of symbols in the data from each physical channel is equal.

7. An encoding method, characterized in that, include: Receive and send data streams; A first interleaving operation is performed on the alignment sequence in the transmitted data stream, such that the original bit order of the alignment sequence is changed at the symbol level; The transmitted data stream after the first interleaving operation is distributed in parallel into N transmitted data streams; Each transmitted data stream is RSFEC encoded in parallel to obtain N transmitted encoded data streams; A second interleaving operation is performed on the N transmitted encoded data streams to obtain N transmitted channel data streams, each of which is sent to one of the N physical channels; wherein, after the second interleaving operation, the original bit order of the alignment sequence that was scrambled is restored.

8. The encoding method according to claim 7, characterized in that, The transmitted data stream after the first interleaving operation is distributed in parallel into N transmitted data streams, including: After the first interleaving operation, the transmitted data stream is distributed sequentially in turn at the symbol granularity, forming N parallel transmitted data streams.

9. The encoding method according to claim 7 or 8, characterized in that, Each of the N transmit channel data streams includes different paths from the N transmit encoded data streams, and the number of symbols in the data from each transmit encoded data stream is equal.

10. The encoding method according to claim 7 or 8, characterized in that, The alignment sequence includes N channel identifiers arranged in order, and each channel identifier identifies one of the physical channels; After the first interleaving operation, the original order of the N channel identifiers is shuffled; the N channel identifiers are distributed to the N transmit data streams respectively, and after the second interleaving operation, different channel identifiers are in different transmit channel data streams, and the physical channel to which the transmit channel data stream corresponding to each channel identifier is sent is the same as the physical channel identified by the channel identifier.

11. A decoding method, characterized in that, The decoding method is used to decode the N-channel transmission channel data stream obtained by the encoding method as described in any one of claims 7-10, including: N data streams are received from N physical channels, and a third interleaving operation is performed on the N data streams. The N data streams are obtained after the second interleaving operation of the encoding device at the transmitting end. The third interleaving operation is the inverse of the second interleaving operation. RSFEC decoding is performed on the N-channel receive data streams after the third interleaving operation; The decoded N receiving channel data streams are aggregated into one receiving data stream.

12. The decoding method according to claim 11, characterized in that, The decoded N receiving channel data streams are aggregated into one receiving data stream, including: Data is received sequentially from N RSFEC decoding modules at the symbol level and then aggregated into the received data stream.

13. The decoding method according to claim 11 or 12, characterized in that, Each of the N receiving channel data streams includes data from different physical channels, and the number of symbols in the data from each physical channel is equal.

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