Frame header and payload normalization splicing method and multiple interconnection protocol frame generation device

Abstract

The present invention relates to the field of data processing and exchange forwarding technology, and provides a method for normalizing and splicing frame headers and payloads and a device for generating frames of various interconnected protocols. The method processes the generated frame header data beat by beat, and the last beat of the frame header and the first beat of the payload are generated simultaneously in the same beat through a set synchronization control signal, thereby seamlessly connecting the frame header and the payload for splicing operations to form a complete data frame. In the splicing module, both the frame header and the payload are specifically implemented as whole-beat segmented inputs. The splicing method provided by the present invention can meet the needs of generating data frames of different protocol types, significantly reduce the complexity of the heterogeneous protocol frame generation process, improve the hardware resource utilization by more than or equal to N times, enhance the cost and power consumption advantages of the environment, and facilitate the flexible expansion of the environment to new types of protocols.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing and switching forwarding, and in particular to a method for normalizing and splicing frame headers and payloads and a device for generating frames of multiple interconnection protocols. Background Art

[0002] In various interconnection protocols, a complete data frame consists of a header, payload, CRC, header and trailer flags, and more. The key parameters required for splicing the header and payload are header length, header data, and payload data. Traditional methods for splicing headers and payloads only support the generation of data frames for a single protocol, limiting their application scenarios. Therefore, the header length is fixed, and the location at which the header data is intercepted during splicing is also fixed. Therefore, a set of protocol-specific splicing logic can be used to achieve this.

[0003] As the number of supported protocols increases within a hardware environment, the need to splice headers and payloads generated by heterogeneous protocol data frames leads to random header interception locations during splicing, significantly increasing the amount of splicing logic. When the environment supports a limited number of supported protocols, the conventional approach is to create separate case studies for splicing headers and payloads for each protocol. Each protocol's processing logic is completely independent within the code module. Without a commonality in splicing operations, the resulting redundant logic leads to high programming resource overhead, and the code logic becomes increasingly complex as the number of protocol types increases.

[0004] Based on the above drawbacks, since Verilog does not support dynamic bit width interception of vector data, in order to support the generation of multiple protocol data frames in one environment, the first traditional method proposed generally uses for loops to achieve splicing, such as Figure 1 As shown, the for loop implements the data interception algorithm of arbitrary frame header length.

[0005] To ensure randomness in the frame header interception position in multi-protocol scenarios, using a for loop to implement dynamic bit width interception is logically clear. However, in hardware, for statements should not be used too frequently. This is because each loop replicates the same circuit multiple times. In other words, if N different protocol types need to be supported in the same environment, the same hardware circuit must be replicated more than N times, and this operation must be repeated for each heterogeneous protocol expansion.

[0006] At this point, the splicing logic becomes particularly complex, and it's impossible to directly and accurately determine the splicing position of the frame header, resulting in significant consumption of hardware resources and system power. Because splicing the frame header and payload is crucial for generating frames for multiple protocol types, the traditional "list-style" splicing method, where each protocol's logic is independent of each other, is not conducive to flexible expansion of supported protocol types. Summary of the Invention

[0007] In order to solve the problem of complex operation when splicing different frame header lengths and payloads of different protocol types in the existing technology, the present invention provides a normalized splicing method for frame headers and payloads and a multi-interconnection protocol frame generation device. The frame header data is generated by beat-by-beat processing, and the tail beat of the frame header and the head beat of the payload are simultaneously generated in the same beat by setting a synchronization control signal, so that the frame header and the payload are seamlessly connected and spliced ​​to form a complete data frame, which can effectively reduce the complexity of data splicing and reduce the waste of time and resources.

[0008] In a first aspect, the present invention provides a method for normalizing and splicing frame headers and payloads in a process of generating frames of multiple interconnection protocols, comprising:

[0009] Step 1: Obtain the frame header and payload of the protocol frame to be generated, and determine the frame header length;

[0010] Step 2: searching a lookup table based on the frame header length to determine whether there is a splicing parameter that matches the frame header length;

[0011] When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number;

[0012] When the lookup table does not contain the splicing parameter, processing the frame header data byte by byte and recording the frame header index, determining whether the frame header length is a whole beat, and determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat;

[0013] Wherein, the frame header index is used to indicate the process of processing the frame header data;

[0014] Step 3: Determine whether to start a synchronization signal based on the frame header index and the number of splicing beats, process the payload data when the synchronization signal is started, and record the payload index;

[0015] Step 4: performing a splicing operation on the frame header data and the payload data according to the splicing position, and completing the splicing of the protocol frame to be generated.

[0016] Furthermore, the method further comprises:

[0017] Step 5: Add the splicing parameters of the protocol frame to be generated to the lookup table, and reset the splicing parameters to prepare for the splicing operation when the next data frame is generated.

[0018] Furthermore, in step 2, determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat specifically includes:

[0019] The number of splicing beats is the frame header length / whole beat length;

[0020] Wherein, the splicing beat number is an integer value;

[0021] When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data;

[0022] When the frame header length is not a whole beat, the splicing position is a data bit in the last beat of the frame header data where the frame header length is equal to or less than the whole beat length.

[0023] Furthermore, in step 4, the splicing operation on the frame header data and the payload data according to the splicing position specifically includes: when the synchronization signal is started, performing splicing boundary processing according to whether the frame header length in step 2 is a whole beat:

[0024] When the frame header length is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data and the first beat of the payload data is generated, and splicing is performed directly;

[0025] When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0026] In a second aspect, the present invention provides an FPGA-based multiple interconnection protocol frame generation device, on which a preset FPGA is provided, wherein the FPGA includes a multi-protocol SerDes module, a multi-protocol controller module, a protocol frame generation module, and a protocol frame splicing module;

[0027] The multi-protocol SerDes module is used to implement a serializer / deserializer for multiple communication protocols, and adapts to different communication standards by configuring different protocols;

[0028] The multi-protocol controller module is used to configure the multi-protocol SerDes module to support a specific communication protocol according to the requirements of generating a protocol frame, and pass information of the specified protocol to the protocol frame generation module;

[0029] The protocol frame generation module is used to generate a frame header that conforms to a specified protocol frame format, and a payload of a specified length and content;

[0030] The protocol frame splicing module is used to splice the frame header and payload generated by the protocol frame generation module to form complete data frames of different protocols.

[0031] Furthermore, the protocol frame splicing module includes:

[0032] A frame header length determination unit, configured to obtain a frame header and a payload of a protocol frame to be generated, and determine a frame header length;

[0033] a splicing position determining unit, configured to search a lookup table based on the frame header length to determine whether there is a splicing parameter matching the frame header length;

[0034] When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number;

[0035] When the lookup table does not contain the splicing parameter, processing the frame header data byte by byte and recording the frame header index, determining whether the frame header length is a whole beat, and determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat;

[0036] Wherein, the frame header index is used to indicate the process of processing the frame header data;

[0037] A dynamic synchronization signal unit, configured to determine whether to start a synchronization signal according to the frame header index and the number of splicing beats, process payload data when the synchronization signal is started, and record the payload index;

[0038] The frame header and payload splicing unit is configured to perform a splicing operation on the frame header data and the payload data according to the splicing position, so that the protocol frame to be generated is spliced.

[0039] Furthermore, the frame header payload splicing unit is further configured to:

[0040] When the to-be-generated protocol frame is completed in splicing, the splicing parameters of the to-be-generated protocol frame are added to the lookup table, and the splicing parameters in the protocol frame splicing module are reset to prepare for the splicing operation when the next data frame is generated.

[0041] Furthermore, the splicing position determining unit is specifically configured to:

[0042] The number of splicing beats is the frame header length / whole beat length;

[0043] Wherein, the splicing position determining unit is specifically used to:

[0044] The number of splicing beats is the frame header length / whole beat length;

[0045] Wherein, the splicing beat number is an integer value;

[0046] When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data;

[0047] When the frame header length is not a whole beat, the splicing position is a data bit in the last beat of the frame header data where the frame header length is equal to or less than the whole beat length.

[0048] Furthermore, the frame header payload splicing unit is specifically configured to:

[0049] When the synchronization signal is activated, splicing boundary processing is performed according to the result of the determination of whether the frame header length is a whole beat in the splicing position determination unit:

[0050] When the frame header length is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data and the first beat of the payload data is generated, and splicing is performed directly;

[0051] When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0052] Beneficial effects of the present invention:

[0053] The proposed method, which dynamically obtains frame header lengths and uses a synchronization mechanism to control frame header and payload splicing, can achieve a standardized splicing process for arbitrary frame header lengths and payloads. In a hardware environment supporting N heterogeneous protocols, the splicing logic for frame headers and payloads, which originally required N or more sets of N protocols, is reduced to a single set. The implemented logic structure is clear and simple, eliminating the tedious, time-consuming, and resource-intensive operations of accumulating multiple calculations.

[0054] The splicing logic provided by the present invention can meet the needs of generating data frames of different protocol types, significantly reduce the complexity of the heterogeneous protocol frame generation process, increase hardware resource utilization by more than or equal to N times, enhance the cost and power consumption advantages of the environment, and facilitate flexible expansion of the environment with new types of protocols.

[0055] In addition, the present invention uses a lookup table to record the frame header length of each splicing, and directly looks up and uses the relevant parameters used for splicing during the next splicing (under the same protocol, there will not be too many types of frame header lengths), avoiding repeated calculation of splicing positions and comparison operations, reducing resource consumption and thus improving utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A logic diagram of a method for implementing arbitrary frame header length data in a for loop in the prior art;

[0057] Figure 2 This is a diagram of the physical layer frame header field format of the prior art PCIe protocol;

[0058] Figure 3 A schematic flow chart of a method for normalizing and splicing frame headers and payloads applicable to the generation process of frames of various interconnection protocols provided in an embodiment of the present invention;

[0059] Figure 4 A schematic diagram of the structure of a device for generating multiple interconnection protocol frames based on FPGA provided by an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of the FPGA workflow provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In the communication of various interconnection protocols, data frames (packets) are the basic units of data transmission. They contain control information and user data and are used for communication between interconnection protocols. Different network layers and protocols use different types of data frames, but their basic structures and functions are similar. A complete data frame consists of a frame header, payload, CRC, frame header and frame tail flags, etc. The main parameters needed for splicing the frame header and payload are the frame header length, frame header data, and payload data. It can be seen that the splicing problem of the frame header and payload is the key to the generation of frames of various protocol types. Taking the communication of the PCIe protocol as an example, the format of the physical layer frame header field is as follows: Figure 2 As shown in the figure, during the communication process, it is first necessary to generate a PCIe data frame as the basic unit of communication. According to the data frame format specified by PCIe, it is divided into a frame header field and a payload field. These two parts of information are not generated as a whole. Instead, after the frame header and payload are generated separately, they need to be spliced ​​one by one in the corresponding order to form a complete data frame for communication.

[0062] Similarly, communication protocols such as RapidIO, Ethernet, and FC also face similar challenges in splicing data frames when generating them. Only by splicing the frame header and payload together can a complete data frame (packet) be formed. It's important to note that the lengths of the frame header and payload can vary within the same protocol or between different protocols. Therefore, when faced with splicing different frame header lengths and payloads from different protocol types within the same hardware environment, certain methods are required. This invention addresses this dilemma: how to support multi-protocol data frame generation within a single hardware environment and reduce the complexity of the splicing process.

[0063] The design idea of ​​the present invention is: first, the frame header data generated is processed beat by beat, and the last beat of the frame header and the first beat of the payload are generated simultaneously in the same beat through the set synchronization control signal, so as to seamlessly connect the frame header and the payload for splicing operation to form a complete data frame. In the splicing module, the frame header and the payload are specifically implemented with whole-beat segmented input. The lookup table records the splicing position corresponding to different frame header lengths, the beat number of the splicing beat, and other parameters. Each time splicing is performed, the lookup table is searched first. If the same frame header length is matched, the splicing position is directly obtained without calculation, and there is no need to cyclically compare the size of the frame header index and the frame header length / whole beat length. After adding it to the specific splicing beat number, the splicing data is assigned and then spliced; if there is no record of the same frame header length, the splicing is performed according to the unknown length, and the specific parameters are recorded in the lookup table. The technical solution in the embodiment of the present invention will be clearly described below in conjunction with the drawings in the embodiment of the present invention.

[0064] like Figure 3 As shown, an embodiment of the present invention provides a normalized splicing method for frame headers and payloads applicable to the generation process of frames of multiple interconnection protocols, including:

[0065] Step 1: Determine the dynamic frame header length.

[0066] Obtain the frame header and payload of the protocol frame to be generated, and determine the frame header length;

[0067] When generating arbitrary frame header length data of different protocol types, the frame header length is temporarily stored through the configuration register. Each time the frame header data is generated, the specific length of the frame header is dynamically read from the configuration register to generate the frame header data.

[0068] Step 2: Process the frame header to determine the splicing position.

[0069] Based on the frame header length, the lookup table is searched to see if there are any splicing parameters that match the frame header length. The splicing parameters in the lookup table are as follows: Figure 4 As shown;

[0070] When the lookup table contains splicing parameters, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; the splicing parameters include the splicing position, frame header length and splicing beat number;

[0071] Specifically, when the same frame header length type is retrieved in the lookup table, the splicing parameters are directly obtained to obtain the splicing position, and the frame header index header_index is cyclically added to the splicing beat number to directly obtain the frame header data header_data.

[0072] When the lookup table does not contain splicing parameters, the frame header data is processed byte by byte and the frame header index is recorded to determine whether the frame header length is a whole beat. Based on whether the frame header length is a whole beat, the splicing position and number of splicing beats of the protocol frame to be generated are determined; the frame header index is used to indicate the process of processing the frame header data.

[0073] Specifically, when the lookup table does not contain splicing parameters, the frame header data header_data is processed byte by byte, and the frame header index header_index is recorded in real time. When the frame header index header_index does not reach the splicing beat number, the value of the frame header data header_data is continuously updated, and the frame header index header_index is incremented by 1 according to the beat number.

[0074] The frame header length is used to determine whether the frame header is a full-frame data. If the frame header is a full-frame data, that is, the last frame data is all valid data; if the frame header is not a full-frame data, that is, only part of the last frame data is valid data. In this embodiment, the full-frame data is 128 bits, and the following logic can be used to determine:

[0075] if(header_length%128 != 0)

[0076] Specifically, the splicing position and the number of splicing beats of the protocol frame to be generated are determined according to whether the frame header length is a whole beat, including:

[0077] The number of splicing beats is the frame header length / the whole beat length, that is, the number of splicing beats = header_length / 128.

[0078] The number of splicing beats is an integer value, and the decimal value is directly truncated to get the integer.

[0079] When the frame header length is a full beat, the splicing position is the last data bit in the last beat of the frame header data;

[0080] When the frame header length is not a whole beat, the data bits of the frame header length% the whole beat length in the last beat of the frame header data at the splicing position are spliced, that is, the splicing position is the position of header_length%128 in the last beat, and the value in the frame header data header_data is assigned to the valid data bits in the last beat of the frame header.

[0081] Step 3: Dynamic synchronization signal setting.

[0082] Determine whether to start the synchronization signal based on the frame header index and the number of splicing beats. When the synchronization signal is started, process the payload data and record the payload index.

[0083] Specifically, when the frame header index header_index reaches the number of splicing beats header_length / 128, the synchronization signal is started and the payload begins to be generated:

[0084] if(header_index== header_length / 128)begin

[0085] sync_signal<= 1'b1 .

[0086] Step 4: Frame header payload splicing operation.

[0087] The frame header data and payload data are spliced ​​according to the splicing position, and the splicing is completed after the protocol frame is generated.

[0088] Specifically, when the synchronization signal is started, splicing boundary processing is performed according to whether the frame header length in step 2 is a whole beat: that is, splicing boundary processing needs to be performed according to whether the last beat of the frame header is a whole beat.

[0089] When the frame header length is a full beat, the synchronization signal ends at the end of the last beat of the frame header data and the first beat of the payload data is generated, and splicing is performed directly;

[0090] Specifically, the synchronization signal is generated when the last beat of the frame header data ends, and the first beat of the payload data is generated. That is, the first beat of the payload data payload_data arrives just at the end of the frame header. After the splicing is completed, it can be continuously output. At this time, the following simple splicing operation can be used:

[0091] if(payload_index== 1&&sync_signal == 1)begin

[0092] Data_out<= {header_data,payload_data};

[0093] When the frame header length is not a full beat, the last beat of the frame header data and the first beat of the payload data are generated at the same time. After splicing, the remaining data of the last beat of the payload data is split into a beat and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0094] Specifically, the last beat of the frame header is not a full beat, but the last beat of the frame header and the first beat of the payload are still generated at the same beat. After being spliced ​​together using the same splicing logic, the remaining last beat of the payload is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0095] Step 5: Continue processing logic.

[0096] The splicing parameters of the protocol frame to be generated are added to the lookup table, and the splicing parameters are reset to prepare for the splicing operation when the next data frame is generated.

[0097] Specifically, if the splicing parameters are not obtained from the lookup table, the relevant splicing parameters are added to the lookup table to facilitate the next generation of protocol frames with the same frame header length. Since the frame header and payload are continuously generated, it is necessary to generate a certain amount of data based on actual needs. Therefore, it is necessary to continuously process the splicing operation of the frame header and payload of the next frame. Therefore, it is necessary to reset the corresponding signal to prepare for the next splicing operation. The example logic is as follows:

[0098] If(tlast== 1&&sync_signal == 1)begin

[0099] header_index<= 0;

[0100] payload_index<= 0;

[0101] sync_signal<= 1'b0;

[0102] header_length<= 0;

[0103] tlast<= 0;

[0104] The splicing logic provided by the present invention can meet the needs of generating data frames of different protocol types, significantly reducing the complexity of the heterogeneous protocol frame generation process. When the splicing method provided by the present invention is applied to hardware, compared with the existing technology, the hardware resource utilization rate is significantly improved, the cost and power consumption advantages of the environment are enhanced, and the environment can be flexibly expanded with new types of protocols.

[0105] Examples of splicing methods:

[0106] 1) The header length header_length read from the configuration register is 480 bits. The lookup table is searched, but no splicing parameters with the same header length are found.

[0107] 2) The frame header data is input in segments of 128 bits per frame, and the header index header_index increases by 1 each time a segment is input;

[0108] 3) When the third segment is input, the header index header_index = header length header_length / whole beat 128 = 3. At this time, the synchronization signal sync_signal is set to 1 and payload generation is started. When the payload generates the first beat, the payload index payload_index is incremented by 1, and the frame header continues to generate the remaining 96 bits of data and input them into header_data.

[0109] 4) Perform the splicing operation, add the header_data and the first beat of the frame header data payload_data, and put the remaining 32-bit data in the last beat of the payload into the next splicing process until the splicing ends when the payload recognizes the tlast indicator bit.

[0110] 5) After the splicing operation is completed and the protocol frame is output, the splicing signals such as the frame header length header_length, frame header index header_index, synchronization signal sync_signal and payload index payload_index should be reset to facilitate the next splicing.

[0111] The embodiment of the present invention also provides a device for generating multiple interconnection protocol frames based on FPGA, which is configured with a preset FPGA, such as Figure 4 As shown, the FPGA includes a multi-protocol SerDes module, a multi-protocol controller module, a protocol frame generation module, and a protocol frame splicing module;

[0112] Multi-protocol SerDes module, used to implement serialization / deserialization of multiple communication protocols, adapting to different communication standards by configuring different protocols;

[0113] The multi-protocol controller module is used to configure the multi-protocol SerDes module to support a specific communication protocol according to the requirements of generating protocol frames, and pass the information of the specified protocol to the protocol frame generation module;

[0114] The protocol frame generation module is used to generate a frame header that conforms to the specified protocol frame format, as well as a payload of specified length and content;

[0115] The protocol frame splicing module is used to splice the frame header and payload generated by the protocol frame generation module to form complete data frames of different protocols.

[0116] It can be understood that the protocol frame splicing module is the splicing operation of this design, which is used to splice the frame header and payload generated by the protocol frame generation module to form complete data frames of different protocols. The FPGA workflow diagram is as follows: Figure 5 As shown in the figure, the FPGA completes the configuration of the multi-protocol controller registers according to the commands. Under the action of the multi-protocol control module whose output is determined by the configuration registers, the protocol frame generation module generates a frame header that conforms to the specified protocol frame format, as well as a payload of the specified length and content.

[0117] Specifically, the protocol frame splicing module includes:

[0118] A frame header length determination unit, configured to obtain a frame header and a payload of a protocol frame to be generated, and determine a frame header length;

[0119] A splicing position determining unit, configured to search a lookup table based on the frame header length to determine whether there is a splicing parameter matching the frame header length;

[0120] When the lookup table contains splicing parameters, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; the splicing parameters include the splicing position, frame header length and splicing beat number;

[0121] When the lookup table does not contain splicing parameters, the frame header data is processed byte by byte, and the frame header index is recorded to determine whether the frame header length is a whole beat. The splicing position and number of splicing beats of the protocol frame to be generated are determined based on whether the frame header length is a whole beat.

[0122] Among them, the frame header index is used to indicate the process of processing the frame header data;

[0123] The dynamic synchronization signal unit is used to determine whether to start the synchronization signal according to the frame header index and the number of splicing beats, process the payload data when the synchronization signal is started, and record the payload index;

[0124] The frame header and payload splicing unit is used to splice the frame header data and payload data according to the splicing position, and complete the splicing after generating the protocol frame.

[0125] Furthermore, the frame header payload splicing unit is further configured to:

[0126] When the protocol frame to be generated is completed, the splicing parameters of the protocol frame to be generated are added to the lookup table, and the splicing parameters in the protocol frame splicing module are reset to prepare for the splicing operation when the next data frame is generated.

[0127] Specifically, the splicing position determination unit is specifically used to:

[0128] The number of splicing beats is the frame header length / whole beat length;

[0129] Among them, the number of splicing beats is an integer value;

[0130] When the frame header length is a full beat, the splicing position is the last data bit in the last beat of the frame header data;

[0131] When the frame header length is not a full beat, the splicing position is the data bit of the last beat of the frame header data that is the frame header length% of the full beat length;

[0132] Specifically, the frame header payload splicing unit is used to:

[0133] When the synchronization signal starts, the splicing position is determined based on whether the frame header length in the unit is a full beat, and the splicing boundary processing is performed:

[0134] When the frame header length is a full beat, the synchronization signal ends at the end of the last beat of the frame header data and the first beat of the payload data is generated, and splicing is performed directly;

[0135] When the frame header length is not a full beat, the last beat of the frame header data and the first beat of the payload data are generated at the same time. After splicing, the remaining data of the last beat of the payload data is split into a beat and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A normalized splicing method for frame headers and payloads applicable to the frame generation process of multiple interconnection protocols, characterized in that: include: Step 1: Obtain the frame header and payload of the protocol frame to be generated, and determine the frame header length; Step 2: searching a lookup table based on the frame header length to determine whether there is a splicing parameter that matches the frame header length; When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number; When the lookup table does not contain the splicing parameter, processing the frame header data byte by byte and recording the frame header index, determining whether the frame header length is a whole beat, and determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat; The frame header index is used to indicate the process of processing the frame header data; determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a full beat, specifically including: The number of splicing beats is the frame header length / whole beat length; wherein, / represents a division sign, and the number of splicing beats is an integer value; When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data; When the frame header length is not a whole beat, the splicing position is the data bit of the frame header length% the whole beat length in the last beat of the frame header data; % represents a remainder operation; Step 3: Determine whether to start a synchronization signal based on the frame header index and the number of splicing beats, process the payload data when the synchronization signal is started, and record the payload index; Step 4: performing a splicing operation on the frame header data and the payload data according to the splicing position, and completing the splicing of the protocol frame to be generated.

2. The normalized splicing method for frame headers and payloads applicable to the generation process of frames of multiple interconnection protocols according to claim 1, characterized in that: The method further comprises: Step 5: Add the splicing parameters of the protocol frame to be generated to the lookup table, and reset the splicing parameters to prepare for the splicing operation when the next data frame is generated.

3. The normalized splicing method for frame headers and payloads applicable to the generation process of frames of multiple interconnection protocols according to claim 1, characterized in that: In step 4, the splicing operation is performed on the frame header data and the payload data according to the splicing position, specifically including: when the synchronization signal is started, performing splicing boundary processing according to whether the frame header length in step 2 is a whole beat: When the frame header length is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data and the first beat of the payload data is generated, and splicing is performed directly; When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

4. A device for generating frames of multiple interconnection protocols based on FPGA, wherein a preset FPGA is provided on the device, characterized in that: The FPGA includes a multi-protocol SerDes module, a multi-protocol controller module, a protocol frame generation module and a protocol frame splicing module; The multi-protocol SerDes module is used to implement a serializer / deserializer for multiple communication protocols, and adapts to different communication standards by configuring different protocols; The multi-protocol controller module is used to configure the multi-protocol SerDes module to support a specific communication protocol according to the requirements of generating a protocol frame, and pass information of the specified protocol to the protocol frame generation module; The protocol frame generation module is used to generate a frame header that conforms to a specified protocol frame format, and a payload of a specified length and content; The protocol frame splicing module is used to splice the frame header and payload generated by the protocol frame generation module to form a complete data frame of different protocols; specifically includes: a frame header length determination unit, which is used to obtain the frame header and payload of the protocol frame to be generated and determine the frame header length; a splicing position determining unit, configured to search a lookup table based on the frame header length to determine whether there is a splicing parameter matching the frame header length; When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number; When the lookup table does not contain the splicing parameter, processing the frame header data byte by byte and recording the frame header index, determining whether the frame header length is a whole beat, and determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat; The frame header index is used to indicate the process of processing the frame header data; the splicing beat number is the frame header length / whole beat length; wherein, / represents a division sign, and the splicing beat number takes an integer value; When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data; When the frame header length is not a whole beat, the splicing position is the data bit of the frame header length% the whole beat length in the last beat of the frame header data; % represents a remainder operation; A dynamic synchronization signal unit, configured to determine whether to start a synchronization signal according to the frame header index and the number of splicing beats, process payload data when the synchronization signal is started, and record the payload index; The frame header and payload splicing unit is configured to perform a splicing operation on the frame header data and the payload data according to the splicing position, so that the protocol frame to be generated is spliced.

5. The FPGA-based multiple interconnection protocol frame generation device according to claim 4, characterized in that: The frame header payload splicing unit is further used for: When the to-be-generated protocol frame is completed in splicing, the splicing parameters of the to-be-generated protocol frame are added to the lookup table, and the splicing parameters in the protocol frame splicing module are reset to prepare for the splicing operation when the next data frame is generated.

6. The FPGA-based multiple interconnection protocol frame generation device according to claim 4, characterized in that: The frame header payload splicing unit is specifically used to: When the synchronization signal is activated, splicing boundary processing is performed according to the result of the determination of whether the frame header length is a whole beat in the splicing position determination unit: When the frame header length is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data and the first beat of the payload data is generated, and splicing is performed directly; When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

Images