Asymmetric groove type SiC power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) based on integrated channel

Abstract

The asymmetric groove type SiC power MOSFET comprises a drain electrode, a substrate, a drift layer, a buffer layer and a source electrode from bottom to top, a groove structure is arranged in the middle of the upper side of the buffer layer, a P well is arranged on the left side of the groove structure and located on the buffer layer, and a P well is arranged on the left side of the P well. A first P + shielding region A is arranged between the lower side of the sinking part and the upper side of the buffer layer, and the right side of the sinking part is in contact with the drift layer on the lower side of the P well to form an SBD; on the right side of the groove structure, the source electrode sinks, a second P + shielding region is arranged between the lower side of the sinking part and the upper side of the buffer layer, and the right side of the sinking part is in contact with the drift layer on the upper side of the second P + shielding region to form a carrier channel. According to the structure, on the basis that the forward conduction performance of the device is not affected, the reverse recovery current and the reverse conduction voltage are reduced compared with an existing improvement method.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an asymmetric trench SiC power MOSFET based on an integrated channel. Background Art

[0002] Trench power MOS (ΜMOS) refers to a power semiconductor device that forms a MOSFET gate on the sidewall of a groove formed on the surface of the chip. This structure buries the gate of the device into the substrate to form a vertical channel. Due to the need to form a groove, the process is relatively complicated, and the consistency and avalanche energy of the unit are worse than those of the planar gate MOSFET. However, it is precisely because of the existence of the trench structure that the unit density has increased, and this structure has no JFET effect, the channel crystal plane achieves the best channel mobility, the on-resistance is significantly reduced compared to the planar gate structure, the parasitic capacitance of the device is smaller, the switching speed is very fast, and the switching loss is very low. Therefore, the new generation of SiC MOSFET mainly studies and adopts this structure.

[0003] In the MMOS structure, due to the contact between the P+ shielding region and the source metal, a PIN-type diode structure is formed through the P well, the depletion layer, and the N+ substrate. The characteristics of this diode correspond to the third quadrant of the MOSFET IV characteristic curve. However, for the same blocking voltage, the turn-off characteristics of the intrinsic diode are relatively poor compared with the optimized PIN-type diode and the Schottky barrier diode. Therefore, a higher storage charge and a higher diode peak reverse current are generated in the traditional MOSFET, which is an obstacle for many applications of MOSFET devices.

[0004] Existing protection measures mainly include integrating Schottky diodes between source and drain, integrating heterojunctions, and integrating channel diodes. The implementation of integrated channel diodes is mainly to use the sidewall N layer under the source connection dummy gate as the reverse current path from the N+ source to the N drift region, which has a small potential barrier. However, its disadvantages are also obvious, mainly manifested as follows:

[0005] 1. The shielding area has a greater impact on the body diode characteristics;

[0006] 2. Although the existing improvement methods can reduce the reverse recovery current, there are limitations on the improvement of the potential barrier between the P+ shielding region and the depletion layer. Summary of the invention

[0007] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide an asymmetric trench SiC power MOSFET based on an integrated channel, so as to reduce the reverse recovery current and the reverse conduction voltage compared with the existing improved method without affecting the forward conduction performance of the device.

[0008] In order to achieve the above object, the technical solution adopted by the present invention is:

[0009] An asymmetric trench SiC power MOSFET based on an integrated channel comprises, from bottom to top, a drain, a substrate, a drift layer, a buffer layer and a source, wherein the middle position on the upper side of the buffer layer is a trench structure, and on the left side of the trench structure, a P well is arranged on the buffer layer, and on the left side of the P well, the source is sunken and a first P+ shielding region A is provided between the lower side of the sunken part and the upper side of the buffer layer, and the right side of the sunken part contacts the drift layer on the lower side of the P well to form an SBD; on the right side of the trench structure, the source is sunken and a second P+ shielding region is provided between the lower side of the sunken part and the upper side of the buffer layer, and the right side of the sunken part contacts the drift layer on the upper side of the second P+ shielding region to form a carrier channel.

[0010] In one embodiment, a first P+ shielding region B and an N+ region A are arranged in contact on the upper side of the P well, the first P+ shielding region B contacts the corner of the source sinker portion on the left side of the P well, and the N+ source region A contacts the trench structure to form a MOS channel.

[0011] In one embodiment, the first P+ shielding region A extends to the right, and a buffer layer portion is reserved on the upper side and the lower side of the P well, so that the source sinker portion on the left side of the P well contacts the buffer layer to form an SBD.

[0012] In one embodiment, the second P+ shielding region wraps around the lower right corner of the source sinking portion on the right side of the trench structure, and a buffer layer portion is left on the right side and the upper side to form the carrier channel.

[0013] In one embodiment, an N+ region B is arranged above the second P+ shielding region, and a buffer layer portion for forming a carrier channel with a sinking portion on the right side of the trench structure is located between the N+ region B and the second P+ shielding region.

[0014] In one embodiment, the doping concentration of the substrate is 5*10 18 cm -3 The doping concentration of the drift layer is 1*10 14 -9*10 15 cm -3 The doping concentration of the first P+ shielding region A, the first P+ shielding region B and the second P+ shielding region is 1*10 18 -9*10 18 cm -3 The doping concentration of the P well is 1*10 17 -9*10 17 cm -3 The doping concentration of the N+ source region A and the N+ source region B is 1*10 19 -9*1019 cm -3 .

[0015] The present invention defines the left-right direction as the width direction, the up-down direction as the length direction, and the front-back direction as the thickness. In one embodiment, the overall width of the device is 2.8 μm, the length is 20 μm, and the thickness is 1 μm. The length of the drift layer is 8-12 μm, the length of the trench structure is 0.5-1.2 μm, and the length of the P well is 0.7-1 μm.

[0016] In one embodiment, on the basis of ensuring that the second P+ shielding region wraps around the gate chamfer, its doping concentration and region size are adjusted to change the device output characteristics.

[0017] In one embodiment, the N-type region of the device is a region formed by doping SiC with pentavalent nitrogen ions, and the P-type region is a region formed by doping SiC with trivalent boron ions.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The present invention reduces the P+ shielding area on the right side of the channel without affecting the corner of the protection gate, widens the carrier channel to the maximum extent, reduces the reverse conduction voltage and reverse recovery current of the device, and improves the double-click degradation problem.

[0020] 2. The SBD on the left side of the channel of the present invention is prepared simultaneously with the dummy gate, which greatly reduces the difficulty of the device manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the overall structure of the MOSFET device of the present invention.

[0022] Figure 2 It is a schematic diagram of the top structure of the MOSFET device of the present invention.

[0023] Figure 3 FIG. 1 is a schematic diagram of an existing asymmetric trench MOS structure.

[0024] Figure 4 Schematic diagram of the existing asymmetric trench MOS structure.

[0025] Figure 5 Schematic diagram comparing the third quadrant IV characteristics of the manual structure curve, the prior art structure curve and the structure of the present invention.

[0026] Figure 6 It is a schematic diagram comparing the first quadrant output characteristics of the manual structure curve, the prior art structure curve and the structure of the present invention.

[0027] Figure 7It is a schematic diagram comparing the first quadrant transconductance characteristics of the manual structure curve, the prior art structure curve and the structure of the present invention.

[0028] Figure 8 It is a schematic diagram comparing the breakdown characteristics of the prior art structure curve and the structure of the present invention.

[0029] Fig. 9 1 is a process diagram for preparing SiC MOSFET of the present invention, wherein (a) to (l) represent different steps. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0031] Theoretically, the use of trench gate structure can greatly improve device parameters, reliability and lifespan, but its difficulties are also obvious. The larger bandgap width of silicon carbide causes the SiC MOSFET body diode to produce a higher reverse recovery current and higher stored charge, resulting in greater losses when the body diode is used as a freewheeling diode.

[0032] There are three main existing protection measures. The main way to integrate a channel between the source and drain is to use the N-type substrate as an accumulation channel under the dummy gate in the shielding area, which can reduce the peak reverse current of the SiC MOSFET body diode to a certain extent. However, this structure has limitations on the improvement of the potential barrier between the P+ shielding area and the depletion layer.

[0033] On this basis, the present invention proposes to change the electron channel to the right side of the MOSFET and add SBD to the left side of the device. The purpose is to further reduce the potential barrier at the interface between the shielding region and the depletion layer without affecting the forward characteristics of the device, eliminate bipolar degradation, and use sentaurus software for structural design and verification.

[0034] like Figure 1 and Figure 2 As shown, the asymmetric trench SiC power MOSFET based on the integrated channel of the present invention includes a drain, a substrate, a drift layer, a buffer layer and a source from bottom to top, and the middle position on the upper side of the buffer layer is a trench structure, and the trench structure is covered by the source. The middle position here does not need to be strictly the center.

[0035] The present invention arranges a P-well on the buffer layer on the left side of the trench structure. On the left side of the P-well, the source is sunk and the sunken part exceeds the P-well downward, and there is a first P+ shielding area A between the lower side of the sunken part and the upper side of the buffer layer. Specifically, the first P+ shielding area A extends to the right, and the upper side and the lower side of the P-well leave a buffer layer part. Thus, the right side of the sunken part and the lower side of the P-well here are still the buffer layer part, and the source sunken part here contacts the buffer layer part here to form an SBD. By way of example, the left side of the sunken part here is already the edge of the device. Compared with the existing structure, the present invention changes the original P-well area into an SBD without basically affecting other performances of the device, and retains the lower part of the P-well to protect the SBD corner.

[0036] In the present invention, on the right side of the trench structure, the source is sunken and the sunken part has the same bottom as the trench structure, and the second P+ shielding area is only arranged between the lower side of the sunken part and the upper side of the buffer layer, and the right side and upper side of the second P+ shielding area are still the buffer layer part. Specifically, the second P+ shielding area wraps the lower right corner of the source sinking part on the right side of the trench structure, and the buffer layer part is reserved on the right side and the upper side. As a result, the right side of the sunken part here contacts the drift layer part on the upper side of the second P+ shielding area to form a carrier channel. The present invention connects a carrier channel in parallel on the basis of the traditional trench tube carrier channel, and integrates it inside the chip, that is, the integrated channel described in the present invention. Compared with the existing structure, the present invention divides the P+ shielding area on the right side of the device into two, and introduces a carrier channel.

[0037] According to the above structure, the specific principle of the present invention is:

[0038] The device of the present invention arranges the source on the right side of the trench structure and has a very special asymmetric trench. Most of the bottom of the trench is embedded in the second P+ shielding area extending below the trench. The second P+ shielding area can extend all the way to the bottom of the trench, protecting the gate oxide at the corner of the trench from the influence of the excessive electric field caused by the drain bias, and playing the role of a body diode. Due to this asymmetric trench, the present invention forms a virtual gate, which means that only half of the trench space is used for the gate, thereby reducing the gate-drain capacitance. During reverse conduction, the carrier channel reserved on the right side of the gate can be used to suppress the conduction of the body diode, thereby helping to alleviate the impact of bipolar degradation. The carrier buffer layer on the lower side of the trench can improve the current distribution and improve the performance and stability of the device. The SBD on the left side of the trench can further reduce the reverse conduction voltage drop, thereby achieving the purpose of optimizing the third quadrant. The remaining structural parts of the present invention can directly adopt the concentration and depth required by standard trench devices.

[0039] Furthermore, in an embodiment of the present invention, a first P+ shielding region B and an N+ region A with contacting top surfaces are arranged on the upper side of the P-well, the first P+ shielding region B contacts the corner of the source sinker portion on the left side of the P-well, and the N+ source region A contacts the trench structure to form a MOS channel, which is aligned with the plane to optimize the mobility of the channel.

[0040] Furthermore, in an embodiment of the present invention, an N+ region B is arranged symmetrically with the N+ region A along the sinking portion on the right side of the P well. The N+ region B should also be located above the second P+ shielding region, and between it and the second P+ shielding region is a buffer layer portion for forming a carrier channel with the sinking portion on the right side of the trench structure.

[0041] Furthermore, the present invention adjusts the doping concentration and area size of the second P+ shielding region on the basis of ensuring that the second P+ shielding region wraps the gate chamfer, thereby changing the device output characteristics. The doping concentration and area size of different regions can change the output characteristics, especially the doping concentration of CSL. The present invention can also change the trench tube into a planar tube or a double trench tube.

[0042] The device of the present invention is made of SiC material, wherein the N-type region is a region formed by doping pentavalent nitrogen ions in SiC, and the P-type region is a region formed by doping trivalent boron ions in SiC.

[0043] In the present invention, the preferred range of the doping concentration of the drift layer is 1*10 14 -9*10 15 cm -3 The doping concentrations of the first P+ shielding region A, the first P+ shielding region B and the second P+ shielding region are preferably the same, in 1*10 18 -9*10 18 cm -3 The optimal value is between 1 and 10. 17 -9*10 17 cm -3 , the doping concentration of N+ source region A and N+ source region B is the same, and the preferred range is 1*10 19 -9*10 19 cm -3 The present invention defines the left-right direction as the width direction, the up-down direction as the length direction, and the front-back direction as the thickness. The corresponding preferred size ranges of the main parts are: the length of the drift layer is 8-12 μm, the length of the trench structure is 0.5-1.2 μm, and the length of the P well is 0.7-1 μm.

[0044] To illustrate the effect of the present invention, Figure 1 and Figure 2 In the structure shown, the device has an overall width of 2.8 μm, a length of 20 μm, a thickness of 1 μm, and a substrate doping concentration of 5*1018 cm -3 , the doping concentration of the drift layer is 9*10 15 cm -3 , with a length of 8.5 μm. The doping concentration of the first P+ shielding region A and the first P+ shielding region B is 5*10 18 cm -3 , the trench depth is 0.5μm, the P well length is 0.7μm, and the doping concentration is 2*10 17 cm -3 The PN junction formed by the P well and the drift layer is the main voltage-bearing area. The doping concentration of the N+ source region A and the N+ source region B is 2*10 19 cm -3 The gate polysilicon is surrounded by an oxide layer, and the gate oxide layer is SiO 2 The doping concentration of the second P+ shielding region is the same as that of the first P+ shielding region, which is 5*10 18 cm -3 , which can wrap the chamfer of the groove, thereby alleviating the phenomenon of electric field concentration.

[0045] According to the above embodiment, Figure 3 and Figure 4 The existing structure shown was verified using sentaurus software.

[0046] according to Figure 5 As shown in the figure, the reverse conduction voltage of the existing structure (the current extraction standard is set to 100mA) is 3.12V, and the reverse recovery current is 15.3A when the source-drain voltage is -4.5V. The reverse conduction voltage of the improved structure is 1.36V, and the reverse recovery current is 27.76A when the source-drain voltage is -4.5V. Since the barrier formed by the carrier channel reserved on the right side of the gate is lower than the built-in potential formed by the PN junction of the SiC material, the third quadrant characteristics can be improved. According to Figure 6 It shows that under different gate voltage conditions, a larger drain current can be obtained when the same drain voltage is taken; Figure 7 The device threshold voltage (the threshold voltage extraction standard is 100mA) is reduced from 4.56V to 3.38V, which proves that the first quadrant output characteristics and first quadrant transconductance characteristics of the device have been improved to a certain extent. Under the condition of gate voltage of 20V, the device is added to the drain voltage of 1500V. Figure 8 It was observed that the breakdown voltage of the improved device was reduced from the original 1328V to the current 1352V, proving that the breakdown characteristics of the device were improved.

[0047] The present invention also provides a preparation process of the asymmetric trench SiC power MOSFET based on the integrated channel, referring to Fig. 9 As shown in , the following steps are included:

[0048] Step 1, growing a drift layer and a buffer layer in sequence on the substrate, growing a P+ shielding region on the buffer layer, and etching the P+ shielding region to form a first P+ shielding region A and a second P+ shielding region on the left side;

[0049] Step 2, growing a buffer layer again on the first P+ shielding area A and the second P+ shielding area and the original buffer layer to completely cover the first P+ shielding area A and the second P+ shielding area;

[0050] Step 3: Since there is an order of magnitude difference between the buffer layer concentration and the P-well doping concentration, doping compensation can be performed in the buffer layer to form a P-well, which is flush with the top surface of the buffer layer. A first P+ shielding region B is formed on the left side of the P-well, and an N+ region is formed on the right side of the P-well and on the buffer layer.

[0051] Step 4, etching the buffer layer on the left side of the P well, the lower side of the etched portion is the first P+ shielding area A; etching part of the buffer layer and part of the N+ region on the right side of the P well, the lower right corner of the etched portion is wrapped by the second P+ shielding area, and the N+ region is reserved as the N+ source region A and the N+ source region B on the left and right sides of the etched portion respectively;

[0052] Step 5, processing the gate oxide layer and the gate on the left side of the etched part on the right side of the P well, and depositing metal on the top of the device as the source, wherein the metal on the left side of the P well contacts the buffer layer to form an SBD, and the metal on the right side of the gate serves as a virtual gate;

[0053] Step 6: grow a drain electrode below the substrate.

Claims

1. An asymmetric trench SiC power MOSFET based on an integrated channel, comprising a drain, a substrate, a drift layer, a buffer layer and a source from bottom to top, wherein the middle position on the upper side of the buffer layer is a trench structure, characterized in that: On the left side of the trench structure, a P well is arranged on the buffer layer. On the left side of the P well, the source is sunk and there is a first P+ shielding region A between the lower side of the sunken part and the upper side of the buffer layer. The right side of the sunken part contacts the drift layer on the lower side of the P well to form an SBD. On the right side of the trench structure, the source is sunk and there is a second P+ shielding region between the lower side of the sunken part and the upper side of the buffer layer. The right side of the sunken part contacts the drift layer on the upper side of the second P+ shielding region to form a carrier channel.

2. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1, characterized in that: A first P+ shielding region B and an N+ region A are arranged in contact on the upper side of the P well. The first P+ shielding region B contacts the corner of the source sinker on the left side of the P well, and the N+ source region A contacts the trench structure to form a MOS channel.

3. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1, characterized in that: The first P+ shielding region A extends to the right, and a buffer layer portion is reserved on the upper side and the lower side of the P well, so that the source sinking portion on the left side of the P well contacts the buffer layer to form an SBD.

4. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1, characterized in that: The second P+ shielding region wraps around the lower right corner of the source sinking portion on the right side of the trench structure, and a buffer layer portion is left on the right side and the upper side to form the carrier channel.

5. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1 or 4, characterized in that: An N+ region B is arranged above the second P+ shielding region, and a buffer layer portion for forming a carrier channel with a sinking portion on the right side of the trench structure is located between the N+ region B and the second P+ shielding region.

6. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 5, characterized in that: The doping concentration of the drift layer is 1*10 14 -9*10 15 cm -3 The doping concentration of the first P+ shielding region A, the first P+ shielding region B and the second P+ shielding region is 1*10 18 -9*10 18 cm -3 The doping concentration of the P well is 1*10 17 -9*10 17 cm -3 The doping concentration of the N+ source region A and the N+ source region B is 1*10 19 -9*10 19 cm -3 .

7. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1, characterized in that: The left-right direction is defined as the width direction, the up-down direction is defined as the length direction, and the front-back direction is defined as the thickness. The length of the drift layer is 8-12 μm, the length of the trench structure is 0.5-1.2 μm, and the length of the P-well is 0.7-1 μm.

8. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1, characterized in that: On the basis of ensuring that the second P+ shielding region wraps the gate chamfer, its doping concentration and region size are adjusted, thereby changing the output characteristics of the device.

9. The asymmetric trench SiC power MOSFET based on integrated channel according to claim 1, characterized in that: The N-type region of the device is formed by doping pentavalent nitrogen ions in SiC, and the P-type region is formed by doping trivalent boron ions in SiC.

10. The process for preparing an asymmetric trench SiC power MOSFET based on an integrated channel according to any one of claims 1 to 9, characterized in that: The steps include: Step 1, growing a drift layer and a buffer layer in sequence on the substrate, growing a P+ shielding region on the buffer layer, and etching the P+ shielding region to form a first P+ shielding region A and a second P+ shielding region on the left side; Step 2, growing a buffer layer again on the first P+ shielding area A and the second P+ shielding area and the original buffer layer to completely cover the first P+ shielding area A and the second P+ shielding area; Step 3, a P well is processed on the buffer layer, the P well is flush with the top surface of the buffer layer, a first P+ shielding area B is processed on the left side of the P well, and an N+ area is processed on the right side of the P well and on the buffer layer; Step 4, etching the buffer layer on the left side of the P well, and the lower side of the etched part is the first P+ shielding area A; Etching part of the buffer layer and part of the N+ region on the right side of the P well, the lower right corner of the etched part is wrapped by the second P+ shielding area, and the N+ region is retained as N+ source region A and N+ source region B on the left and right sides of the etched part respectively; Step 5, processing the gate oxide layer and the gate on the left side of the etched portion on the right side of the P well, and growing the source electrode on the right side and the etched portion on the left side of the P well and the top of the device; Step 6: grow a drain electrode below the substrate.

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