Method for quickly searching faults of secondary circuit of power system

Abstract

The invention relates to the technical field of power fault detection, in particular to a power system secondary circuit fault quick search method, which comprises the following steps of: establishing a circuit topological graph according to a wiring diagram of a secondary circuit, analyzing and marking high-risk nodes with parasitic circuits, and establishing a power system secondary circuit topological graph; performing signal feature extraction on voltage, current and impedance data during normal operation, and forming a baseline feature set after feature extraction; arranging a sensor at a high-risk node, collecting real-time voltage, current and impedance data in a secondary loop, carrying out signal feature extraction again, detecting a deviation with a baseline feature set in combination with a principal component analysis algorithm, and identifying an abnormal signal; comparing the abnormal signal with a parasitic loop fault feature library, and preliminarily positioning a fault position in combination with a topology model; and injecting a test signal at the preliminarily positioned fault position, and verifying existence of a parasitic loop. According to the invention, deviation detection is carried out on abnormal signals through real-time monitoring and a principal component analysis algorithm, and potential parasitic loop faults can be rapidly identified.

Description

Technical Field

[0001] The present invention relates to the technical field of power fault detection, and in particular to a method for quickly finding faults in secondary circuits of a power system. Background Art

[0002] The secondary circuit of the power system undertakes the key functions of protection, control and signal transmission. The reliability of its operation directly affects the safety and stability of the power system. However, in a complex secondary circuit, a parasitic circuit may be formed due to improper design or construction. This parasitic circuit refers to a closed loop accidentally formed in the secondary circuit, usually caused by multiple grounding points, irregular wiring or electromagnetic coupling between equipment.

[0003] Parasitic circuit faults have the following characteristics: parasitic circuits are easily affected by primary equipment operations (such as circuit breaker opening and closing) or changes in external magnetic fields, generating electromagnetic induced voltage or circulating current, resulting in abnormal voltage distribution in the secondary circuit. This abnormal signal may interfere with the normal operation of the relay protection device, resulting in false operation or refusal to operate.

[0004] Parasitic circuit fault signals usually appear as weak high-frequency induced voltages or dynamic electromagnetic characteristics, which are not easily captured by traditional detection methods. In addition, the impact of parasitic circuits is often hidden and only appears under specific operating conditions (such as high magnetic field change rate or sudden load changes), which increases the complexity of detection.

[0005] Parasitic circuits may be distributed in a complex secondary circuit network, and their specific locations are difficult to locate quickly through traditional means. Traditional methods usually rely on manual inspections, disconnection inspections at each section, or general testing equipment, but they are inefficient and have limited positioning accuracy. Summary of the invention

[0006] Based on the above purpose, the present invention provides a method for quickly finding faults in secondary circuits of an electric power system.

[0007] A method for quickly finding faults in a secondary circuit of an electric power system comprises the following steps:

[0008] S1, topology modeling and feature baseline establishment: According to the wiring diagram of the secondary circuit, a circuit topology diagram is established, high-risk nodes with parasitic circuits are analyzed and marked, and voltage, current, and impedance data during normal operation of the power system are collected. Signal feature extraction is performed on the voltage, current, and impedance data during normal operation, and a baseline feature set is formed after feature extraction;

[0009] S2, real-time acquisition of multi-point signals: sensors are placed at high-risk nodes to collect real-time voltage, current and impedance data in the secondary circuit, covering the weak electromagnetic induction signals caused by parasitic circuits, and signal feature extraction is performed again on the real-time detected voltage, current and impedance data. The principal component analysis algorithm is used to detect deviations from the baseline feature set and identify abnormal signals.

[0010] S3, parasitic loop feature classification and location: compare the abnormal signal with the parasitic loop fault feature library, determine the length and nodes of the parasitic loop, and preliminarily locate the fault location based on the topological model;

[0011] S4, dynamic verification and isolation: inject test signals at the preliminary fault location, analyze node response characteristics, and verify the existence of parasitic loops through disconnection or isolation operations.

[0012] Furthermore, the S1 specifically includes:

[0013] S11, wiring data analysis: obtain the wiring diagram and related design data of the secondary circuit, including wire connection relationship, node distribution, equipment port information and grounding configuration;

[0014] S12, topology modeling: Based on the wiring diagram analysis data, the secondary circuit is modeled as a circuit topology diagram of nodes (connection points) and edges (wires) using graph theory methods. The weight of the edge represents the wire characteristics (such as impedance value, electrical length, etc.), and the node attribute marks the device type (such as relay, protection device);

[0015] S13, Electromagnetic Induction Risk Analysis: By analyzing the spatial layout of primary equipment and secondary circuits, the electromagnetic coupling risks of nodes and edges in the secondary circuits are evaluated, including long conductors, cross-region ground loops, and paths close to primary equipment;

[0016] S14, parasitic loop detection rules: according to the grounding point distribution and loop connection characteristics of the secondary loop, detect the path forming a closed parasitic loop and mark multiple grounding points or unclosed suspended nodes;

[0017] S15, high-risk node marking: Based on the loop topology, screen and mark high-risk nodes with the following characteristics:

[0018] There are intersection nodes where multiple paths are closed;

[0019] Long distance wires and high induction area nodes;

[0020] Multiple ground nodes.

[0021] Furthermore, the loop topology is represented as: G = (V, E), where V is a node set, indicating key points in the loop including device connection points and grounding points, and E is an edge set, indicating wire connections between nodes, with weights w ij , weight w ij The calculation formula is: ij =R ij +jX ij , where R ij is the resistance of the wire between nodes i and j, calculated from the material parameters, X ij is the reactance between nodes i and j. The loop topology graph formed by nodes V and edges E is used for subsequent parasitic loop detection. Based on the loop topology graph G, the path set P = {p x |x=1,2,...n} Check whether the node v∈V appears in multiple closed paths at the same time. If it appears multiple times, mark the node as an intersection node with multiple closed paths.

[0022] Furthermore, each path p in the path set P x satisfy: Indicates that the path voltage phase sum is an integer multiple of 2π. When path p k There are g>1 grounding points in the path, g is the number of grounding points in the path, and all nodes on the corresponding path are marked as multi-grounding nodes.

[0023] Furthermore, in the electromagnetic induction risk analysis, the induced voltage caused by electromagnetic induction Calculated from Faraday's law of induction:

[0024] Among them, Φ ij =B·A ij is the magnetic flux between nodes i and j, B is the magnetic field strength in the sensing area, and A ij It is the effective area of ​​the cross-sectional area of ​​the conductor and the projection of the magnetic flux direction, combined with the conductor length L ij and induced voltage Mark long distance conductors and nodes with high induction areas.

[0025] Furthermore, the construction of the baseline feature set specifically includes:

[0026] S16, install sensors at high-risk nodes in the secondary circuit of the power system to collect the following data:

[0027] Voltage data: record transient power frequency voltage U(t);

[0028] Current data: monitoring the working current I(t) in the circuit;

[0029] Impedance data: By injecting a small test signal, the equivalent impedance between nodes is measured, Z = R + jX, where R is resistance and X is reactance;

[0030] De-noise the collected original signal and normalize the amplitude for subsequent feature extraction;

[0031] S17, signal feature extraction: Extract key signal features through time-frequency domain analysis, including:

[0032] Power frequency amplitude and phase characteristics: Extract the transient amplitude U of voltage and current rms ,I rms and Phase

[0033] Harmonic component: Calculate the high-order harmonic component U based on fast Fourier transform n ,I n ;

[0034] Impedance characteristics: Extract the modulus value |Z| and angle θ of equivalent impedance;

[0035] S18, baseline feature set generation: Based on the extracted signal features, a normal operating baseline feature matrix F is constructed. base :

[0036] The feature matrix is ​​stored as a baseline feature set, which is used to compare with the features of real-time collected data to identify abnormal signals.

[0037] Furthermore, in S2, the voltage, current and impedance data detected in real time are again subjected to signal feature extraction to obtain a real-time feature matrix F real , based on the principal component analysis algorithm, the real-time feature matrix F real , baseline feature matrix F base Project them into the principal component space respectively and extract the principal characteristic components PC:

[0038] PC real =Q·F real ;

[0039] PC base =Q·F base ;

[0040] Where Q is the principal component transformation matrix;

[0041] Baseline comparison: principal component center PC of real-time features real The principal component center PC with baseline characteristics base For comparison, calculate the Euclidean distance d: b represents the serial number of the principal component and the number of principal components selected;

[0042] Threshold judgment: Compare the distance d with the set threshold d threshold For comparison:

[0043] If d≤d threshold , the data are considered normal;

[0044] If d>d threshold , identified as abnormal.

[0045] Furthermore, the S3 specifically includes:

[0046] S31, extract the feature vector F of the abnormal signal anomaly ,include Call the historical feature set F that is consistent with the feature vector dimension from the parasitic circuit fault feature library library , calculate the similarity between the two:

[0047] Among them, w e is the weight of feature e, Range e is the value range of feature e, S is the similarity score (ranging from 0 to 1, the closer to 1, the more similar), F anomaly,e is the e-th eigenvalue of the abnormal signal, F library,e is the e-th characteristic value in the parasitic circuit fault characteristic library;

[0048] S32, extracting the following parasitic circuit information from the fault feature library according to the fault feature record with the highest similarity:

[0049] Length: The equivalent wire length of the parasitic loop, reflecting the physical scope of the fault loop;

[0050] Node distribution: the set of key nodes in the parasitic loop.

[0051] Furthermore, the S3 also includes S33, in the loop topology graph G=(V, E), mapping the extracted key node distribution to the actual loop, marking all nodes and paths related to the parasitic loop, and preliminarily locating the faulty node through the following conditions:

[0052] The node closest to the high-risk node;

[0053] The node with the largest electromagnetic induction intensity in the connected path;

[0054] Output preliminary positioning results.

[0055] Furthermore, the S4 specifically includes:

[0056] S41, test signal injection: select one or more initially located faulty nodes and inject a test signal;

[0057] S42, node response characteristics analysis: collect the voltage, current, impedance and high-order harmonic response data of each node after the test signal is injected, and analyze its time domain and frequency domain characteristics, including:

[0058] Time domain analysis: record the transient voltage and current waveforms of each node to check whether they are consistent with the characteristics of the parasitic loop;

[0059] Frequency domain analysis: Analyze the frequency spectrum of the node through fast Fourier transform to identify whether the signal contains abnormal frequency components (such as high-order harmonics or resonant frequencies);

[0060] Impedance analysis: Measures impedance changes between nodes, including changes in frequency response, to determine if there are changes in loop inductance or capacitance;

[0061] S43, disconnection or isolation operation verification: according to the node response characteristics, the node or path is disconnected or isolated to verify the existence of the parasitic loop. The specific operations include:

[0062] Disconnect the path: According to the initially located fault path, disconnect part of the suspected fault path and observe the changes in node voltage and current. If the fault signal disappears or weakens, it is confirmed that there is a parasitic loop on the path.

[0063] Isolate nodes: Disconnect the suspected faulty node and observe the response changes of other nodes. If the fault characteristics disappear after isolation, it indicates that the node is associated with a parasitic loop fault.

[0064] Beneficial effects of the present invention:

[0065] The present invention realizes efficient positioning of secondary circuit faults in power systems by combining circuit topology models, real-time signal acquisition and signal feature extraction technology. During normal operation, the collected voltage, current, impedance and other data are analyzed in the time-frequency domain to extract signal features to form a baseline feature set, which provides an accurate reference for subsequent abnormality detection. Based on these baseline feature sets, deviation detection of abnormal signals is performed through real-time monitoring and principal component analysis algorithms, which can quickly identify potential parasitic circuit faults. After the faulty node is initially located, the accuracy of the fault is further verified through test signal injection and node response analysis, avoiding possible incorrect positioning and misjudgment in traditional methods.

[0066] The present invention introduces means such as feature library comparison and test signal injection of parasitic loops, which greatly improves the accuracy and reliability of fault location. By matching the parasitic loop fault feature library with the real-time abnormal signal, it can accurately analyze and locate the length, nodes and impact range of the parasitic loop, providing a more detailed and accurate positioning result for the traditional fault location method. In addition, by injecting test signals and analyzing the node response characteristics, combined with the feedback verification of the disconnection or isolation operation, the existence and location of the parasitic loop are multiple confirmed, greatly improving the accuracy and robustness of fault detection. Compared with the traditional fault location method, the present invention can not only identify conventional faults, but also effectively detect and locate subtle parasitic loop faults that are difficult to detect, especially in complex environments such as high-risk nodes and long-distance wires. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0068] Figure 1 A schematic diagram of a method flow of an embodiment of the present invention;

[0069] Figure 2 A schematic diagram of constructing a baseline feature set according to an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0071] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0072] like Figure 1-Figure 2As shown, a method for quickly finding faults in secondary circuits of a power system comprises the following steps:

[0073] S1, topology modeling and feature baseline establishment: According to the wiring diagram of the secondary circuit, a loop topology diagram is established, high-risk nodes with parasitic circuits are analyzed and marked, and voltage, current, and impedance data during normal operation of the power system are collected. Signal feature extraction is performed on the voltage, current, and impedance data during normal operation. After feature extraction, a baseline feature set is formed as a reference;

[0074] S2, real-time acquisition of multi-point signals: sensors are placed at high-risk nodes to collect real-time voltage, current and impedance data in the secondary circuit, covering the weak electromagnetic induction signals caused by parasitic circuits, and signal feature extraction is performed again on the real-time detected voltage, current and impedance data. The principal component analysis algorithm is used to detect deviations from the baseline feature set and identify abnormal signals.

[0075] S3, parasitic loop feature classification and location: compare the abnormal signal with the parasitic loop fault feature library, determine the length and nodes of the parasitic loop, and preliminarily locate the fault location based on the topological model;

[0076] S4, dynamic verification and isolation: inject test signals at the preliminary fault location, analyze node response characteristics, and verify the existence of parasitic loops through disconnection or isolation operations.

[0077] S1 specifically includes:

[0078] S11, wiring data analysis: obtain the wiring diagram and related design data of the secondary circuit, including wire connection relationship, node distribution, equipment port information and grounding configuration;

[0079] S12, topology modeling: Based on the wiring diagram analysis data, the secondary circuit is modeled as a circuit topology diagram of nodes (connection points) and edges (wires) using graph theory methods. The weight of the edge represents the wire characteristics (such as impedance value, electrical length, etc.), and the node attribute marks the device type (such as relay, protection device);

[0080] S13, Electromagnetic Induction Risk Analysis: By analyzing the spatial layout of primary equipment and secondary circuits, the electromagnetic coupling risks of nodes and edges in the secondary circuits are evaluated, including long conductors, cross-region ground loops, and paths close to primary equipment;

[0081] S14, parasitic loop detection rules: according to the grounding point distribution and loop connection characteristics of the secondary loop, detect the path forming a closed parasitic loop and mark multiple grounding points or unclosed suspended nodes;

[0082] S15, high-risk node marking: Based on the loop topology, screen and mark high-risk nodes with the following characteristics:

[0083] There are intersection nodes where multiple paths are closed;

[0084] Long distance wires and high induction area nodes;

[0085] Multiple ground nodes.

[0086] The loop topology is represented as: G = (V, E), where V is a node set, indicating the key points in the loop including device connection points and grounding points, and E is an edge set, indicating the wire connection between nodes, with weight w ij , weight w ij The calculation formula is: ij =R ij +jX ij , where R ij is the resistance of the wire between nodes i and j, calculated from the material parameters: Where ρ is the resistivity of the wire material, L ij is the length of the wire, A is the cross-sectional area of ​​the wire, X ij is the reactance between nodes i and j, calculated as: X ij =2πf·L, where f is the system frequency and L is the inductive reactance of the conductor, which is determined by the geometric parameters of the conductor. The loop topology diagram composed of nodes V and edges E is used for subsequent parasitic loop detection. Based on the loop topology diagram G, through the path set P = {p x |x=1,2,...n} Check whether the node v∈V appears in multiple closed paths at the same time. If it appears multiple times, mark the node as an intersection node with multiple closed paths.

[0087] Each path p in the path set P x satisfy: Indicates that the path voltage phase sum is an integer multiple of 2π. When path p k There are g>1 grounding points in the path, where g is the number of grounding points in the path. For a loop path, if there are multiple grounding points (for example, two or more grounding points) on the path, multi-point grounding may be formed, resulting in a parasitic loop. The path has a multi-point grounding problem, and all nodes on the corresponding path are marked as multi-grounding nodes.

[0088] In electromagnetic induction risk analysis, the induced voltage caused by electromagnetic induction Calculated from Faraday's law of induction:

[0089] Among them, Φ ij =B·A ij is the magnetic flux between nodes i and j, B is the magnetic field strength in the sensing area, and A ij It is the effective area of ​​the cross-sectional area of ​​the conductor and the projection of the magnetic flux direction, combined with the conductor length L ijand induced voltage Mark long distance conductors and nodes with high induction areas.

[0090] The construction of the baseline feature set specifically includes:

[0091] S16, install sensors at high-risk nodes in the secondary circuit of the power system to collect the following data:

[0092] Voltage data: record transient power frequency voltage U(t);

[0093] Current data: monitoring the working current I(t) in the circuit;

[0094] Impedance data: By injecting a small test signal, the equivalent impedance between nodes is measured, Z = R + jX, where R is resistance and X is reactance;

[0095] The above is obtained through voltage sensor, current sensor and resistance sensor;

[0096] De-noise the collected original signal and normalize the amplitude for subsequent feature extraction;

[0097] S17, signal feature extraction: Extract key signal features through time-frequency domain analysis, including:

[0098] Power frequency amplitude and phase characteristics: Extract the transient amplitude U of voltage and current rms ,I rms and Phase

[0099] Harmonic component: Calculate the high-order harmonic component U based on fast Fourier transform n ,I n ;

[0100] Impedance characteristics: Extract the modulus value |Z| and angle θ of equivalent impedance;

[0101] S18, baseline feature set generation: Based on the extracted signal features, a normal operating baseline feature matrix F is constructed. base :

[0102] The feature matrix is ​​stored as a baseline feature set, which is used to compare with the features of real-time collected data to identify abnormal signals.

[0103] 1. Power frequency amplitude and phase feature extraction:

[0104] Power frequency transient amplitude (effective value):

[0105] Among them, U(t) is the transient voltage signal, I(t) is the transient current signal, is the power frequency period, f is the system frequency, Urms ,I rms are the transient amplitudes of voltage and current respectively;

[0106] Power frequency phase difference: It is the phase difference between the power frequency voltage and current.

[0107] 2. Harmonic component extraction:

[0108] Harmonic Amplitude: Among them, U k ,I k is the voltage and current signal of the discrete sampling points, N is the total number of sampling points, n is the harmonic number, U n ,I n are the voltage and current amplitudes of the nth harmonic;

[0109] Total harmonic distortion (THD): Among them, U1, I1 are the fundamental wave amplitudes.

[0110] 3. Impedance characteristics extraction:

[0111] Impedance modulus: Where, |U| is the voltage amplitude at the measurement point, |I| is the current amplitude at the measurement point, and |Z| is the impedance modulus;

[0112] Impedance phase angle: Where R is the real part of the impedance, representing the resistive component, X is the imaginary part of the impedance, representing the reactive component, and θ is the phase angle of the impedance.

[0113] In S2, the signal features of the real-time detected voltage, current and impedance data are extracted again to obtain the real-time feature matrix F real , based on the principal component analysis algorithm, the real-time feature matrix F real , baseline feature matrix F base Project them into the principal component space respectively and extract the principal characteristic components PC:

[0114] PC real =Q·F real ;

[0115] PC base =Q·F base ;

[0116] Where Q is the principal component transformation matrix;

[0117] Baseline comparison: principal component center PC of real-time features real The principal component center PC with baseline characteristics base For comparison, calculate the Euclidean distance d: b represents the serial number of the principal component and the number of principal components selected;

[0118] Threshold judgment: Compare the distance d with the set threshold d threshold For comparison:

[0119] If d≤d threshold , the data are considered normal;

[0120] If d>d threshold , identified as abnormal.

[0121] Principal component analysis is a dimensionality reduction and feature extraction method that uses the main direction of change of the data (principal components) to simplify high-dimensional data while retaining the main characteristics of the data. base Take principal component analysis as an example:

[0122] 1. Input data: baseline feature matrix F base is an m×n matrix, representing m normal operation records, each record includes n features, and each real-time collected data F real It is also a 1×n vector, representing the characteristics of the current moment:

[0123] 2. Covariance matrix calculation: based on F base Compute the covariance matrix ∑:

[0124] Among them, μ base is the mean vector of the baseline feature set, and the covariance reflects the correlation between features;

[0125] 3. Principal component extraction: Perform eigenvalue decomposition on the covariance matrix ∑ to obtain the eigenvalue λ i and the corresponding eigenvector q i :∑q i =λ i q i ; Sort by eigenvalue size, select the eigenvectors corresponding to the first s largest eigenvalues ​​to form the principal component matrix Q s ;

[0126] 4. Dimensionality reduction and feature mapping: project the feature vector into the principal component space.

[0127] S3 specifically includes:

[0128] S31, extract the feature vector F of the abnormal signal anomaly ,include Call the historical feature set F that is consistent with the feature vector dimension from the parasitic circuit fault feature library library , calculate the similarity between the two:

[0129] Among them, w eis the weight of feature e (assigned according to the degree of influence of the feature on the parasitic loop), Range e is the value range of feature e, S is the similarity score (ranging from 0 to 1, the closer to 1, the more similar), F anomaly,e is the e-th eigenvalue of the abnormal signal, F library,e is the e-th characteristic value in the parasitic circuit fault characteristic library;

[0130] S32, extracting the following parasitic circuit information from the fault feature library according to the fault feature record with the highest similarity:

[0131] Length: The equivalent wire length of the parasitic loop, reflecting the physical scope of the fault loop;

[0132] Node distribution: the set of key nodes in the parasitic loop.

[0133] S3 also includes S33, in the loop topology graph G = (V, E), mapping the extracted key node distribution to the actual loop, marking all nodes and paths related to the parasitic loop, and preliminarily locating the faulty node through the following conditions:

[0134] The node closest to the high-risk node (crossing nodes with multiple closed paths; nodes with long-distance wires and high-sensing areas; nodes with multiple grounding);

[0135] The node with the largest electromagnetic induction intensity in the connected path;

[0136] Output preliminary positioning results.

[0137] S4 specifically includes:

[0138] S41, test signal injection: select one or more initially located faulty nodes to inject a test signal, the test signal selection includes:

[0139] Single-frequency power frequency signal: inject an AC signal with a frequency of 50Hz;

[0140] Pulse signal: inject a short pulse signal to stimulate the transient response of the circuit;

[0141] Harmonic signal: inject a signal containing multiple high-order harmonics to test the response characteristics of the circuit to harmonics;

[0142] S42, node response characteristics analysis: collect the voltage, current, impedance and high-order harmonic response data of each node after the test signal is injected, and analyze its time domain and frequency domain characteristics, including:

[0143] Time domain analysis: record the transient voltage and current waveforms of each node to check whether they are consistent with the characteristics of the parasitic loop;

[0144] Frequency domain analysis: Analyze the frequency spectrum of the node through fast Fourier transform to identify whether the signal contains abnormal frequency components (such as high-order harmonics or resonant frequencies);

[0145] Impedance analysis: Measures impedance changes between nodes, including changes in frequency response, to determine if there are changes in loop inductance or capacitance;

[0146] S43, disconnection or isolation operation verification: according to the node response characteristics, the node or path is disconnected or isolated to verify the existence of the parasitic loop. The specific operations include:

[0147] Disconnect the path: According to the initially located fault path, disconnect part of the suspected fault path and observe the changes in node voltage and current. If the fault signal disappears or weakens, it is confirmed that there is a parasitic loop on the path.

[0148] Isolate nodes: Disconnect the suspected faulty node and observe the response changes of other nodes. If the fault characteristics disappear after isolation, it indicates that the node is associated with a parasitic loop fault.

[0149] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present invention is limited to these examples. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0150] The present invention is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for quickly finding faults in secondary circuits of a power system, characterized in that: The following steps are involved: S1, topology modeling and feature baseline establishment: According to the wiring diagram of the secondary circuit, a circuit topology diagram is established, high-risk nodes with parasitic circuits are analyzed and marked, and voltage, current, and impedance data during normal operation of the power system are collected. Signal feature extraction is performed on the voltage, current, and impedance data during normal operation, and a baseline feature set is formed after feature extraction; S2, real-time acquisition of multi-point signals: sensors are placed at high-risk nodes to collect real-time voltage, current and impedance data in the secondary circuit, covering the weak electromagnetic induction signals caused by parasitic circuits, and signal feature extraction is performed again on the real-time detected voltage, current and impedance data. The principal component analysis algorithm is used to detect deviations from the baseline feature set and identify abnormal signals. S3, parasitic loop feature classification and location: compare the abnormal signal with the parasitic loop fault feature library, determine the length and nodes of the parasitic loop, and preliminarily locate the fault location based on the topological model; S4, dynamic verification and isolation: inject test signals at the preliminary fault location, analyze node response characteristics, and verify the existence of parasitic loops through disconnection or isolation operations.

2. A method for quickly finding faults in secondary circuits of a power system according to claim 1, characterized in that: The S1 specifically includes: S11, wiring data analysis: obtain the wiring diagram and related design data of the secondary circuit, including wire connection relationship, node distribution, equipment port information and grounding configuration; S12, topology modeling: Based on the wiring diagram analysis data, the secondary circuit is modeled as a circuit topology diagram of nodes and edges using graph theory. The edge weight represents the wire characteristics, and the node attribute marks the device type. S13, Electromagnetic Induction Risk Analysis: By analyzing the spatial layout of primary equipment and secondary circuits, the electromagnetic coupling risks of nodes and edges in the secondary circuits are evaluated, including long conductors, cross-region ground loops, and paths close to primary equipment; S14, parasitic loop detection rules: according to the grounding point distribution and loop connection characteristics of the secondary loop, detect the path forming a closed parasitic loop and mark multiple grounding points or unclosed suspended nodes; S15, high-risk node marking: Based on the loop topology, screen and mark high-risk nodes with the following characteristics: There are intersection nodes where multiple paths are closed; Long distance wires and high induction area nodes; Multiple ground nodes.

3. A method for quickly finding faults in secondary circuits of a power system according to claim 2, characterized in that: The loop topology graph is represented as: G = (V, E), where V is a node set, indicating key points in the loop including device connection points and grounding points, and E is an edge set, indicating wire connections between nodes, with weights w ij , weight w ij The calculation formula is: ij =R ij +jX ij , where R ij is the resistance of the wire between nodes i and j, calculated from the material parameters, X ij is the reactance between nodes i and j. The loop topology graph formed by nodes V and edges E is used for subsequent parasitic loop detection. Based on the loop topology graph G, the path set P = {p x |x=1,2,...n} Check whether the node v∈V appears in multiple closed paths at the same time. If it appears multiple times, mark the node as an intersection node with multiple closed paths.

4. A method for quickly finding faults in secondary circuits of a power system according to claim 3, characterized in that: Each path p in the path set P x satisfy: Indicates that the path voltage phase sum is an integer multiple of 2π. When path p k There are g>1 grounding points in the path, g is the number of grounding points in the path, and all nodes on the corresponding path are marked as multi-grounding nodes.

5. A method for quickly finding faults in secondary circuits of a power system according to claim 4, characterized in that: In the electromagnetic induction risk analysis, the induced voltage caused by electromagnetic induction Calculated from Faraday's law of induction: Among them, Φ ij =B·A ij is the magnetic flux between nodes i and j, B is the magnetic field strength in the sensing area, and A ij It is the effective area of ​​the cross-sectional area of ​​the conductor and the projection of the magnetic flux direction, combined with the conductor length L ij and induced voltage Mark long distance conductors and nodes with high induction areas.

6. A method for quickly finding faults in secondary circuits of a power system according to claim 2, characterized in that: The construction of the baseline feature set specifically includes: S16, install sensors at high-risk nodes in the secondary circuit of the power system to collect the following data: Voltage data: record transient power frequency voltage U(t); Current data: monitoring the working current I(t) in the circuit; Impedance data: By injecting a small test signal, the equivalent impedance between nodes is measured, Z = R + jX, where R is resistance and X is reactance; De-noise the collected original signal and normalize the amplitude; S17, signal feature extraction: Extract key signal features through time-frequency domain analysis, including: Power frequency amplitude and phase characteristics: Extract the transient amplitude U of voltage and current rms ,I rms and Phase Harmonic component: Calculate the high-order harmonic component U based on fast Fourier transform n ,I n ; Impedance characteristics: Extract the modulus value |Z| and angle θ of equivalent impedance; S18, baseline feature set generation: Based on the extracted signal features, a normal operating baseline feature matrix F is constructed. base : Store the feature matrix as the baseline feature set.

7. A method for quickly finding faults in secondary circuits of a power system according to claim 6, characterized in that: In S2, the signal features of the voltage, current and impedance data detected in real time are extracted again to obtain a real-time feature matrix F real , based on the principal component analysis algorithm, the real-time feature matrix F real , baseline feature matrix F base Project them into the principal component space respectively and extract the principal characteristic components PC: PC real =Q·F real ; PC base =Q·F base ; Where Q is the principal component transformation matrix; Baseline comparison: principal component center PC of real-time features real The principal component center PC with baseline characteristics base For comparison, calculate the Euclidean distance d: b represents the serial number of the principal component and the number of principal components selected; Threshold judgment: Compare the distance d with the set threshold d threshold For comparison: If d≤d threshold , the data are considered normal; If d>d threshold , identified as abnormal.

8. A method for quickly finding faults in secondary circuits of a power system according to claim 7, characterized in that: The S3 specifically includes: S31, extract the feature vector F of the abnormal signal anomaly ,include Call the historical feature set F that is consistent with the feature vector dimension from the parasitic circuit fault feature library library , calculate the similarity between the two: Among them, w e is the weight of feature e, Range e is the value range of feature e, S is the similarity score, and F anomaly,e is the e-th eigenvalue of the abnormal signal, F library,e is the e-th characteristic value in the parasitic circuit fault characteristic library; S32, extracting the following parasitic circuit information from the fault feature library according to the fault feature record with the highest similarity: Length: The equivalent wire length of the parasitic loop, reflecting the physical scope of the fault loop; Node distribution: the set of key nodes in the parasitic loop.

9. A method for quickly finding faults in secondary circuits of a power system according to claim 8, characterized in that: The S3 also includes S33, in the loop topology graph G=(V, E), mapping the extracted key node distribution to the actual loop, marking all nodes and paths related to the parasitic loop, and preliminarily locating the faulty node through the following conditions: The node closest to the high-risk node; The node with the largest electromagnetic induction intensity in the connected path; Output preliminary positioning results.

10. A method for quickly finding faults in secondary circuits of a power system according to claim 1, characterized in that: The S4 specifically includes: S41, test signal injection: select one or more initially located faulty nodes and inject a test signal; S42, node response characteristics analysis: collect the voltage, current, impedance and high-order harmonic response data of each node after the test signal is injected, and analyze its time domain and frequency domain characteristics, including: Time domain analysis: record the transient voltage and current waveforms of each node to check whether they are consistent with the characteristics of the parasitic loop; Frequency domain analysis: Analyze the frequency spectrum of the node through fast Fourier transform to identify whether the signal contains abnormal frequency components; Impedance analysis: Measures impedance changes between nodes, including changes in frequency response, to determine if there are changes in loop inductance or capacitance; S43, disconnection or isolation operation verification: according to the node response characteristics, the node or path is disconnected or isolated to verify the existence of the parasitic loop. The specific operations include: Disconnect the path: According to the initially located fault path, disconnect part of the suspected fault path and observe the changes in node voltage and current. If the fault signal disappears or weakens, it is confirmed that there is a parasitic loop on the path. Isolate nodes: Disconnect the suspected faulty node and observe the response changes of other nodes. If the fault characteristics disappear after isolation, it indicates that the node is associated with a parasitic loop fault.

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