A method for quickly finding power system secondary circuit faults

Abstract

The application relates to the technical field of power failure detection, in particular to a power system secondary circuit fault rapid searching method, which comprises the following steps: according to a wiring diagram of a secondary circuit, a circuit topology diagram is established, high-risk nodes with parasitic circuits are analyzed and marked, signal feature extraction is carried out on voltage, current and impedance data in normal operation, and a baseline feature set is formed after feature extraction; sensors are arranged at the high-risk nodes, real-time voltage, current and impedance data in the secondary circuit are collected, signal feature extraction is carried out again, deviation detection is carried out in combination with a principal component analysis algorithm and abnormal signals are identified in combination with the baseline feature set; the abnormal signals are compared with a parasitic circuit fault feature library, and a fault position is preliminarily located in combination with a topology model; test signals are injected at the preliminarily located fault position, and the existence of the parasitic circuit is verified. According to the application, real-time monitoring and the principal component analysis algorithm are used for deviation detection on abnormal signals, so that potential parasitic circuit faults can be rapidly identified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power failure detection, and particularly relates to a method for quickly finding secondary circuit failure of a power system. BACKGROUND

[0002] The secondary circuit of a power system undertakes the key functions of protection, control and signal transmission, and its reliability directly affects the safety and stability of the power system. However, in a complex secondary circuit, due to improper design or construction, a parasitic loop may be formed. The parasitic loop refers to a closed loop accidentally formed in the secondary circuit, which is usually caused by multi-point grounding, non-standard wiring or electromagnetic coupling between devices.

[0003] The parasitic loop failure has the following characteristics: the parasitic loop is easily affected by the operation of primary equipment (such as the opening and closing of a circuit breaker) or the change of an external magnetic field, resulting in an electromagnetic induction voltage or a circulating current, which causes abnormal voltage distribution of the secondary circuit. This abnormal signal may interfere with the normal operation of a relay protection device, resulting in misoperation or refusal to operate.

[0004] The parasitic loop failure signal usually exhibits weak high-frequency induction voltage or dynamic electromagnetic characteristics, which is not easy to be captured by traditional detection methods. In addition, the influence of the parasitic loop is usually implicit, and only under specific operating conditions (such as high magnetic field change rate or load mutation) it will be revealed, increasing the complexity of detection.

[0005] The parasitic loop may be distributed in a complex secondary circuit network, and its specific location is difficult to be quickly positioned by traditional methods. Traditional methods usually rely on manual inspection, step-by-step disconnection inspection or general test equipment, but the efficiency is low and the positioning accuracy is limited. SUMMARY

[0006] Based on the above purpose, the present application provides a method for quickly finding secondary circuit failure of a power system.

[0007] A method for quickly finding secondary circuit failure of a power system, comprising the following steps:

[0008] S1, topology modeling and characteristic baseline establishment: according to the wiring diagram of the secondary circuit, a loop topology graph is established, high-risk nodes with parasitic loops are analyzed and marked, voltage, current and impedance data during normal operation of the power system are collected, signal characteristics of the voltage, current and impedance data during normal operation are extracted, and a baseline feature set is formed after the characteristic extraction;

[0009] S2, real-time acquisition of multi-point signals: sensors are arranged at high-risk nodes to acquire real-time voltage, current and impedance data in the secondary circuit, cover weak electromagnetic induction signals caused by parasitic loops, and perform signal feature extraction on the real-time detected voltage, current and impedance data, detect deviations from the baseline feature set in combination with principal component analysis algorithm, and identify abnormal signals;

[0010] S3, parasitic loop feature classification and positioning: compare the abnormal signals with the parasitic loop fault feature library to determine the length and nodes of the parasitic loop, and preliminarily locate the fault position in combination with the topology model;

[0011] S4, dynamic verification and isolation: inject test signals at the preliminarily located fault position, analyze the node response characteristics, and verify the existence of the parasitic loop through disconnection or isolation operation.

[0012] Further, the S1 specifically includes:

[0013] S11, wiring data analysis: obtain the wiring diagram and related design data of the secondary circuit, including the connection relationship of conductors, node distribution, device port information and grounding configuration;

[0014] S12, topology modeling: based on the wiring diagram analysis data, the secondary circuit is modeled as a loop topology graph of nodes (connection points) and edges (conductors) using graph theory method, and the weight of the edge represents the conductor characteristics (such as impedance value, electrical length, etc.), and the node attribute marks the device type (such as relay, protection device);

[0015] S13, electromagnetic induction risk analysis: by analyzing the spatial layout of primary devices and secondary circuits, the electromagnetic coupling risk of nodes and edges in the secondary circuit is evaluated, including long conductors, cross-region grounding loops and paths close to primary devices;

[0016] S14, parasitic loop detection rule: according to the grounding point distribution and loop connection characteristics of the secondary circuit, the path forming a closed parasitic loop is detected, and multiple grounding points or suspended nodes that are not closed are marked;

[0017] S15, high-risk node marking: based on the loop topology graph, high-risk nodes with the following characteristics are screened and marked:

[0018] There are multiple paths closed at the intersection node;

[0019] Long-distance conductors and high-induction zone nodes;

[0020] Multiple grounding nodes.

[0021] Further, the loop topology graph is represented as: G=(V, E), wherein, V is a node set, representing key points in the loop including device connection points and grounding points, E is an edge set, representing wire connections between nodes, with weight w ij The calculation formula of the weight w ij is as follows: w ij =R ij +jX ij , wherein, R ij is the resistance of the wire between nodes i and j, calculated from material parameters, and X ij is the reactance between nodes i and j, the loop topology graph composed of nodes V and edges E is used for subsequent parasitic loop detection, based on the loop topology graph G, whether a node v∈V appears in multiple closed paths at the same time is checked through a path set P={p x |x=1, 2,...n}, if it appears multiple times, the node is marked as a cross node with multiple path closures.

[0022] Further, each path p x in the path set P satisfies: , which represents that the phase sum of the path voltage is an integer multiple of 2π, when there are g>1 grounding points in the path p k , g is the number of grounding points in the path, all nodes on the corresponding path are marked as multi-grounding nodes.

[0023] Further, in the electromagnetic induction risk analysis, the induced voltage V induced by electromagnetic induction is calculated by Faraday's law of induction:

[0024] , wherein, Φ ij =B·A ij is the magnetic flux between nodes i and j, B is the magnetic field strength of the induction region, A ij is the effective area of the wire cross-sectional area projected in the direction of magnetic flux, combined with the wire length L ij and the induced voltage V , long-distance wires and nodes in high induction regions are marked.

[0025] Further, the construction of the baseline feature set specifically includes:

[0026] S16, install sensors at high-risk nodes of the power system secondary loop, and collect the following data:

[0027] Voltage data: record transient power frequency voltage U(t);

[0028] Current data: monitor the working current I(t) in the loop;

[0029] Impedance data: By injecting a small test signal, the equivalent impedance between nodes is measured, Z = R + jX, where R is the resistance and X is the reactance;

[0030] The collected original signal is denoised and the amplitude is normalized for subsequent feature extraction;

[0031] S17, signal feature extraction: key signal features are extracted through time-frequency domain analysis, including:

[0032] Power frequency amplitude and phase features: extract the transient amplitude U rms ,I rms and phase

[0033] Harmonic components: based on fast Fourier transform, calculate the high-order harmonic component U n ,I n ;

[0034] Impedance characteristics: extract the modulus |Z| and angle θ of the equivalent impedance;

[0035] S18, baseline feature set generation: according to the extracted signal features, construct the normal operation baseline feature matrix F base :

[0036] Store the feature matrix as the baseline feature set, which is used for comparison with the features of real-time collected data to identify abnormal signals.

[0037] Further, the S2 again performs signal feature extraction on the real-time detected voltage, current and impedance data, obtaining the real-time feature matrix F real Based on the principal component analysis algorithm, project the real-time feature matrix F real and the baseline feature matrix F base into the principal component space respectively, and extract the principal component PC:

[0038] PC real = Q·F real ;

[0039] PC base = Q·F base ;

[0040] Where Q is the principal component transformation matrix;

[0041] Baseline comparison: compare the principal component center PC real of the real-time feature with the principal component center PC base of the baseline feature, and calculate the Euclidean distance d: b represents the serial number of the principal component, and the number of selected principal components;

[0042] Threshold judgment: compare the distance d with the set threshold d threshold

[0043] If d≤d threshold , the data is considered normal;

[0044] If d>d threshold , it is identified as abnormal.

[0045] Further, the S3 specifically includes:

[0046] S31, extracting the feature vector F of the abnormal signal anomaly , including Calling a set of historical features F consistent with the dimension of the feature vector from the parasitic loop fault feature library library , calculating the similarity between the two:

[0047] Where w e is the weight of feature e, Range e is the value range of feature e, S is the similarity score (range from 0 to 1, the closer to 1 indicates the more similar), F anomaly,e is the e-th feature value of the abnormal signal, F library,e is the e-th feature value in the parasitic loop fault feature library;

[0048] S32, according to the highest similarity fault feature record, extract the following parasitic loop information from the fault feature library:

[0049] Length: the equivalent wire length of the parasitic loop, reflecting the physical range of the fault loop;

[0050] Node distribution: the key node set in the parasitic loop.

[0051] Further, the S3 also includes S33, in the loop topology graph G=(V,E), the extracted key node distribution is mapped to the actual loop, all nodes and paths related to the parasitic loop are marked, and the fault node is preliminarily located through the following conditions:

[0052] The node closest to the high-risk node;

[0053] The node with the maximum electromagnetic induction strength in the connected path;

[0054] Output the preliminary positioning result.

[0055] Further, the S4 specifically includes:

[0056] S41, test signal injection: selecting one or more preliminarily located fault nodes to inject test signals;

[0057] ​S42, node response characteristic analysis: collect the voltage, current, impedance and high harmonic response data of each node after the test signal injection, analyze the time domain and frequency domain characteristics, including:

[0058] Time domain analysis: record the transient voltage and current waveforms of each node, and check whether they are consistent with the characteristics of the parasitic loop;

[0059] Frequency domain analysis: analyze the frequency spectrum of the node by fast Fourier transform, and identify whether the signal contains abnormal frequency components (such as high harmonics or resonance frequency);

[0060] Impedance analysis: measure the impedance change between nodes, including the change of frequency response, to determine whether there is a change in loop inductance or capacitance;

[0061] S43, disconnect or isolate operation verification: according to the node response characteristics, disconnect or isolate the node and path, verify the existence of the parasitic loop, the specific operation includes:

[0062] Disconnect the path: according to the preliminary positioning of the fault path, disconnect part of the suspected fault path, and observe the changes of node voltage and current, if the fault signal disappears or weakens, it is confirmed that there is a parasitic loop on the path.

[0063] Isolate the node: by disconnecting the suspected fault node, observe the response change of other nodes, if the fault characteristics disappear after isolation, it indicates that the node is associated with the parasitic loop fault.

[0064] The beneficial effects of the present application are:

[0065] The present application realizes efficient positioning of power system secondary loop faults by combining loop topology model, real-time signal acquisition and signal feature extraction technology. In normal operation, the collected voltage, current, impedance and other data are analyzed by time-frequency domain analysis to extract signal characteristics, forming a baseline feature set, which provides accurate reference for subsequent anomaly detection. Based on these baseline feature sets, real-time monitoring and principal component analysis algorithm are used to detect deviations of abnormal signals, which can quickly identify potential parasitic loop faults. After preliminary positioning of the fault node, the accuracy of the fault is further verified by test signal injection and node response analysis, avoiding false positioning and misjudgment that may occur in traditional methods.

[0066] The application introduces the comparison of the characteristic library of the parasitic loop and the injection of the test signal, which greatly improves the accuracy and reliability of fault positioning. Through the matching of the parasitic loop fault characteristic library and the real-time abnormal signal, the length, node and influence range of the parasitic loop can be accurately analyzed and positioned, which provides more detailed and accurate positioning results for the traditional fault positioning method. In addition, through the injection of the test signal and the analysis of the node response characteristics, combined with the feedback verification of the disconnection or isolation operation, the existence and position of the parasitic loop are confirmed multiple times, which greatly improves the accuracy and robustness of fault detection. Compared with the traditional fault positioning method, the application can not only identify the conventional fault, but also effectively detect and position the weak parasitic loop fault which is difficult to detect, especially in the complex environment of high-risk nodes and long-distance conductors. BRIEF DESCRIPTION OF DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only illustrate the application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0068] Fig. 1 The method flowchart of the embodiment of the application is shown in the figure.

[0069] Fig. 2 The baseline feature set construction schematic diagram of the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the application more clear, the following will further illustrate the application in detail with specific embodiments.

[0071] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the application should be understood as the usual meaning understood by those skilled in the art. The "first", "second" and similar words used in the application do not represent any order, quantity or importance, but are only used to distinguish different components. "Include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent the relative positional relationship, when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0072] As Figs. 1-2As shown, a power system secondary circuit fault rapid finding method, comprising the following steps:

[0073] S1, topology modeling and characteristic baseline establishment: according to the wiring diagram of the secondary circuit, the circuit topology graph is established, the high-risk nodes with parasitic loops are analyzed and marked, the voltage, current and impedance data during normal operation of the power system are collected, the voltage, current and impedance data during normal operation are extracted for signal characteristics, and the baseline feature set is formed after feature extraction as a reference;

[0074] S2, real-time signal acquisition at multiple points: sensors are arranged at high-risk nodes to collect real-time voltage, current and impedance data in the secondary circuit, covering weak electromagnetic induction signals caused by parasitic loops, and the voltage, current and impedance data detected in real time are extracted for signal characteristics again, combined with principal component analysis algorithm to detect the deviation from the baseline feature set and identify abnormal signals;

[0075] S3, parasitic loop characteristic classification and positioning: compare the abnormal signals with the parasitic loop fault characteristic library to determine the length and nodes of the parasitic loop, and preliminarily locate the fault position combined with the topology model;

[0076] S4, dynamic verification and isolation: inject test signals at the preliminary fault location, analyze the node response characteristics, and verify the existence of the parasitic loop by disconnecting or isolating operation.

[0077] S1 specifically includes:

[0078] S11, wiring data analysis: obtain the wiring diagram and related design data of the secondary circuit, including conductor connection relationship, node distribution, device port information and grounding configuration;

[0079] S12, topology structure modeling: based on the wiring diagram analysis data, the secondary circuit is modeled as a loop topology graph of nodes (connection points) and edges (conductors) using graph theory method, the weight of the edge represents the conductor characteristics (such as impedance value, electrical length, etc.), and the node attribute marks the device type (such as relay, protection device);

[0080] S13, electromagnetic induction risk analysis: by analyzing the spatial layout of primary equipment and secondary circuit, the electromagnetic coupling risk of nodes and edges in the secondary circuit is evaluated, including long conductors, cross-region grounding loops and paths close to primary equipment;

[0081] S14, parasitic loop detection rule: according to the grounding point distribution and loop connection characteristics of the secondary circuit, the path forming a closed parasitic loop is detected, and multiple grounding points or suspended nodes that are not closed are marked;

[0082] S15, high-risk node marking: based on the loop topology graph, the high-risk nodes with the following characteristics are screened and marked:

[0083] There are multiple paths closed intersection nodes;

[0084] Long distance wire and high induction area node;

[0085] Multi-ground node.

[0086] Loop topology graph is represented as: G=(V, E), where V is the set of nodes, representing the key points in the loop including device connection points, grounding points, E is the edge set, representing the wire connection between nodes, with weight w ij , the calculation formula of weight w ij is: w ij =R ij +jX ij , where R ij is the resistance of the wire between nodes i and j, which is calculated from the material parameters: Where ρ is the resistivity of the wire material, L ij is the length of the wire, A is the cross-sectional area of the wire, X ij is the reactance between nodes i and j, calculated as: X ij =2πf·L, where f is the system frequency, L is the inductance value of the wire, determined by the geometric parameters of the wire, the loop topology graph composed of nodes V and edges E is used for subsequent parasitic loop detection, based on the loop topology graph G, through the path set P={p x | x=1,2,...n} check whether the node v∈V appears in multiple closed paths at the same time, if multiple times, mark the node as an intersection node with multiple paths closed.

[0087] Each path p x in the path set P satisfies: Indicates that the phase sum of the path voltage is an integer multiple of 2π, when there are g>1 grounding points in the path p k , g is the number of grounding points in the path, for a loop path, if there are multiple grounding points (such as two or more grounding points) on the path, it may form a multi-point grounding, which may cause a parasitic loop, the path has a multi-point grounding problem, mark all nodes on the corresponding path as multi-ground nodes.

[0088] In the electromagnetic induction risk analysis, the induced voltage V induced by electromagnetic induction is calculated by Faraday's law of induction:

[0089] Where Φ ij =B·A ij is the magnetic flux between nodes i and j, B is the magnetic field strength of the induction area, A ij is the effective area of the wire cross-sectional area projected in the direction of magnetic flux, combined with the wire length L ijand induced voltage Mark long-distance conductor and high-induction area node.

[0090] The construction of the baseline feature set specifically includes:

[0091] S16, install sensors at high-risk nodes of the power system secondary circuit, and collect the following data:

[0092] Voltage data: record transient power frequency voltage U(t);

[0093] Current data: monitor the working current I(t) in the circuit;

[0094] Impedance data: measure the equivalent impedance Z=R+jX between nodes by injecting a small test signal, where R is resistance and X is reactance;

[0095] The above is obtained through voltage sensors, current sensors, and resistance sensors;

[0096] The collected raw signals are denoised and the amplitudes are normalized for subsequent feature extraction;

[0097] S17, signal feature extraction: extract key signal features through time-frequency domain analysis, including:

[0098] Power frequency amplitude and phase features: extract the transient amplitude U rms ,I rms and phase

[0099] Harmonic components: calculate high-order harmonic components U n ,I n based on fast Fourier transform;

[0100] Impedance characteristics: extract the modulus |Z| and angle θ of the equivalent impedance;

[0101] S18, baseline feature set generation: construct a baseline feature matrix F base based on the extracted signal features:

[0102] Store the feature matrix as a baseline feature set for comparison with the features of real-time collected data to identify abnormal signals.

[0103] 1. Power frequency amplitude and phase feature extraction:

[0104] Power frequency transient amplitude (effective value):

[0105] where U(t) is the transient voltage signal, I(t) is the transient current signal, is the power frequency period, f is the system frequency, and Urms , I rms are the instantaneous amplitudes of voltage and current, respectively;

[0106] Power frequency phase difference: is the phase difference of power frequency voltage and current.

[0107] 2. Harmonic component extraction:

[0108] Harmonic amplitude: where U k , I k are the voltage and current signals of discrete sampling points, N is the total number of sampling points, n is the harmonic order, U n , I n are the voltage and current amplitudes of the nth harmonic;

[0109] Total harmonic distortion (THD): where U1,I1 are the fundamental amplitudes.

[0110] 3. Impedance characteristic extraction:

[0111] Impedance modulus: where |U| is the voltage amplitude at the measurement point, |I| is the current amplitude at the measurement point, and |Z| is the impedance modulus;

[0112] Impedance phase angle: where R is the impedance real part, representing the resistance component, X is the impedance imaginary part, representing the reactance component, and θ is the impedance phase angle.

[0113] In S2, real-time voltage, current and impedance data are again subjected to signal feature extraction, obtaining real-time feature matrix F real , based on principal component analysis algorithm, real-time feature matrix F real , baseline feature matrix F base are projected into the principal component space, and the principal feature components PC are extracted:

[0114] PC real = Q·F real ;

[0115] PC base = Q·F base ;

[0116] where Q is the principal component transformation matrix;

[0117] Baseline comparison: the principal component centers PC real of real-time features are compared with the principal component centers PC base of baseline features, and the Euclidean distance d is calculated: b represents the serial number of principal components, and the number of selected principal components;

[0118] Threshold judgment: compare the distance d with the set threshold d threshold :

[0119] If d≤d threshold , the data is considered normal;

[0120] If d>d threshold , it is identified as abnormal.

[0121] Principal component analysis is a dimension reduction and feature extraction method, which uses the main variation direction (principal component) of the data to simplify high-dimensional data while retaining the main characteristics of the data, with the baseline feature matrix F base as an example:

[0122] 1. Input data: baseline feature matrix F base is an m×n matrix, representing m normal operation records, each record including n features, and each real-time collected data F real is also a 1×n vector, representing the current time characteristics:

[0123] 2. Covariance matrix calculation: based on F base , the covariance matrix ∑ is calculated:

[0124] Where μ base is the mean vector of the baseline feature set, and the covariance reflects the correlation between the features;

[0125] 3. Principal component extraction: eigenvalue decomposition is performed on the covariance matrix ∑ to obtain eigenvalues λ i and corresponding eigenvectors q i : ∑q i = λ i q i ; sort the eigenvalues by size, and select the eigenvectors corresponding to the first s largest eigenvalues to form the principal component matrix Q s ;

[0126] 4. Dimension reduction and feature mapping: project the eigenvectors into the principal component space.

[0127] S3 specifically includes:

[0128] S31, extract the eigenvector F anomaly of the abnormal signal, including calling a historical feature set F library consistent with the dimension of the eigenvector from the parasitic loop fault feature library, and calculating the similarity between the two:

[0129] Where w eis the weight of feature e (assigned according to the degree of influence of the feature on the parasitic loop), Range e is the range of feature e, S is the similarity score (ranging from 0 to 1, the closer to 1, the more similar), F anomaly,e is the e-th feature value of the abnormal signal, F library,e is the e-th feature value in the parasitic loop fault feature library;

[0130] S32, according to the fault feature record with the highest similarity, extract the following parasitic loop information from the fault feature library:

[0131] Length: the equivalent wire length of the parasitic loop, reflecting the physical range of the fault loop;

[0132] Node distribution: the set of key nodes in the parasitic loop.

[0133] S3 also includes S33, in the loop topology graph G=(V,E), the extracted key node distribution is mapped to the actual loop, all nodes and paths related to the parasitic loop are marked, and the fault node is preliminarily located through the following conditions:

[0134] The node closest to the high-risk node (the intersection node where multiple paths are closed; the node with long-distance wire and high-induction area; the multi-ground node);

[0135] The node with the maximum electromagnetic induction strength in the connected path;

[0136] Output the preliminary positioning result.

[0137] S4 specifically includes:

[0138] S41, test signal injection: select one or more preliminarily positioned fault nodes to inject test signals, the selection of test signals includes:

[0139] Single-frequency power frequency signal: inject an alternating current signal with a frequency of power frequency 50Hz;

[0140] Impulse signal: inject a short pulse signal to stimulate the transient response of the circuit;

[0141] Harmonic signal: inject a signal containing multiple high-order harmonics to test the response characteristics of the loop to harmonics;

[0142] S42, node response characteristic analysis: collect the voltage, current, impedance and high-order harmonic response data of each node after test signal injection, analyze its time domain and frequency domain characteristics, including:

[0143] Time domain analysis: record the transient voltage and current waveforms of each node, and check whether they are consistent with the characteristics of the parasitic loop;

[0144] Frequency domain analysis: analyze the frequency spectrum of the node through fast Fourier transform, identify whether there are abnormal frequency components (such as high harmonics or resonance frequency) in the signal;

[0145] Impedance analysis: measure the impedance change between nodes, including the change of frequency response, to determine whether there is a change in loop inductance or capacitance;

[0146] S43, disconnect or isolate operation verification: according to the response characteristics of the node, disconnect or isolate the operation of the node and the path, verify the existence of the parasitic loop, the specific operation includes:

[0147] Disconnect the path: according to the preliminary positioning of the fault path, disconnect part of the suspected fault path, and observe the change of node voltage and current, if the fault signal disappears or weakens, it is confirmed that there is a parasitic loop on the path.

[0148] Isolate the node: disconnect the suspected fault node, observe the response change of other nodes, if the fault characteristics disappear after isolation, it indicates that the node is associated with the parasitic loop fault.

[0149] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the scope of the present application is limited to these examples; under the idea of the present application, the above embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the present application as described above. In order to be brief, they are not provided in details.

[0150] The present application is intended to cover all such alternatives, modifications and variations as fall within the broad scope of the claims. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for rapid fault location in secondary circuits of a power system, characterized in that, Includes the following steps: S1, Topology Modeling and Feature Baseline Establishment: Based on the secondary loop wiring diagram, establish the loop topology diagram, analyze and mark high-risk nodes with parasitic loops, collect voltage, current, and impedance data during normal power system operation, extract signal features from the voltage, current, and impedance data during normal operation, and form a baseline feature set after feature extraction; specifically including: S11, Wiring Data Parsing: Obtain the wiring diagram and related design data of the secondary circuit, including wire connection relationships, node distribution, equipment port information and grounding configuration; S12, Topology Modeling: Based on the wiring diagram analysis data, the secondary loop is modeled as a loop topology graph of nodes and edges using graph theory methods. The weight of the edge represents the characteristics of the conductor, and the node attributes are labeled with the equipment type. S13, Electromagnetic Induction Risk Analysis: By analyzing the spatial layout of primary equipment and secondary circuits, assess the electromagnetic coupling risks of nodes and edges in the secondary circuits, including long conductors, cross-regional grounding circuits, and paths adjacent to primary equipment. S14, Parasitic loop detection rules: Based on the distribution of grounding points and loop connection characteristics of secondary loops, detect the path that forms a closed parasitic loop and mark multiple grounding points or unclosed floating nodes; S15, High-risk node labeling: Based on the loop topology graph, filter and label high-risk nodes with the following characteristics: There are intersections where multiple paths close together; Long-distance conductors and nodes in high-sensitivity areas; Multiple grounding nodes; S2, Real-time acquisition of multi-point signals: Sensors are deployed at high-risk nodes to collect real-time voltage, current and impedance data in the secondary circuit, covering the weak electromagnetic induction signals caused by parasitic circuits. The real-time detected voltage, current and impedance data are subjected to signal feature extraction again, and the deviation from the baseline feature set is detected by combining the principal component analysis algorithm and abnormal signals are identified. S3, Parasitic loop feature classification and location: Compare abnormal signals with the parasitic loop fault feature database to determine the length and nodes of the parasitic loop, and use the topology model to initially locate the fault location; S4, Dynamic Verification and Isolation: Inject test signals at the initial fault location, analyze node response characteristics, and verify the existence of parasitic loops through disconnection or isolation operations; specifically including: S41, Test signal injection: Select one or more initially located fault nodes and inject test signals; S42, Node Response Characteristic Analysis: After the test signal is injected, the voltage, current, impedance, and higher harmonic response data of each node are collected, and their time-domain and frequency-domain characteristics are analyzed, including: Time-domain analysis: Record the transient voltage and current waveforms of each node and check whether they are consistent with the characteristics of the parasitic loop; Frequency domain analysis: By analyzing the spectrum of nodes using Fast Fourier Transform, it can identify whether the signal contains abnormal frequency components; Impedance analysis: Measure the impedance changes between nodes, including changes in frequency response, to determine if there are changes in loop inductance or capacitance. S43, Disconnect or Isolate Operation Verification: Based on the node response characteristics, disconnect or isolate the node and path to verify the existence of the parasitic loop. Specific operations include: Disconnect the path: Based on the initially located fault path, disconnect a part of the suspected fault path and observe the changes in node voltage and current. If the fault signal disappears or weakens, it is confirmed that there is a parasitic loop on the path. Isolate nodes: By disconnecting the suspected faulty node, observe the response changes of other nodes. If the fault characteristics disappear after isolation, it indicates that the node is associated with a parasitic loop fault.

2. The method for rapid fault location in a power system secondary circuit according to claim 1, characterized in that, The loop topology diagram is represented as follows: ,in, It is a set of nodes, representing key points in the loop, including device connection points and grounding points. It is a set of edges, representing wire connections between nodes, with weights. Weight The calculation formula is: ,in, For nodes and The resistance of the conductors between them is calculated from the material parameters. For nodes and Reactance between nodes and edge The constructed loop topology map is used for subsequent parasitic loop detection, based on the loop topology map. via path set Check nodes If a node appears in multiple closed paths, it is marked as an intersection node with multiple closed paths.

3. The method for rapid fault location in a power system secondary circuit according to claim 2, characterized in that, The path set Each path satisfy: This indicates that the sum of the path voltage phases is an integer multiple. When the path There exists The number of grounding points, It represents the number of grounding points in the path, marking all nodes on the corresponding path as multi-grounding nodes.

4. The method for rapid fault location in a power system secondary circuit according to claim 3, characterized in that, In the electromagnetic induction risk analysis, the induced voltage caused by electromagnetic induction... Calculated using Faraday's law of induction: ,in, It is a node and The magnetic flux between them It is the magnetic field strength of the sensing area. It is the effective area of ​​the conductor's cross-sectional area projected onto the magnetic flux direction, combined with the conductor length. and induced voltage Mark long-distance wires and nodes in high-sensitivity areas.

5. The method for rapid fault location in a power system secondary circuit according to claim 1, characterized in that, The construction of the baseline feature set specifically includes: S16. Install sensors at high-risk nodes in the secondary circuit of the power system to collect the following data: Voltage data: Record transient power frequency voltage ; Current data: Operating current in the monitoring circuit ; Impedance data: The equivalent impedance between nodes is measured by injecting a small test signal. ,in For resistance, For reactance; The acquired raw signal is denoised and the amplitude is normalized. S17, Signal Feature Extraction: Extract key signal features through time-frequency domain analysis, including: Power frequency amplitude and phase characteristics: Extracting transient amplitudes of voltage and current and phase ; Harmonic components: Calculation of higher harmonic components based on Fast Fourier Transform ; Impedance characteristics: Extracting the magnitude of the equivalent impedance and angle ; S18, Baseline Feature Set Generation: Based on the extracted signal features, construct a baseline feature matrix for normal operation. : The feature matrix is ​​stored as a baseline feature set.

6. The method for rapid fault location in a power system secondary circuit according to claim 5, characterized in that, In step S2, signal feature extraction is performed again on the real-time detected voltage, current, and impedance data to obtain a real-time feature matrix. Based on the principal component analysis algorithm, the real-time feature matrix is... Baseline feature matrix Projected onto the principal component space respectively, the principal feature components (PCs) are extracted: ； ； in, It is the principal component transformation matrix; Baseline Comparison: Principal Component Centers of Real-Time Features Principal component centers with baseline characteristics Compare and calculate the Euclidean distance. : ; Indicates the principal component number and the number of principal components selected; Threshold determination: Distance With the set threshold Comparison: if The data was considered normal; if It was identified as abnormal.

7. The method for rapid fault location in a power system secondary circuit according to claim 6, characterized in that, S3 specifically includes: S31, Extract the feature vector of the abnormal signal ,include ; Retrieve a historical feature set with the same dimension as the feature vector from the parasitic loop fault feature library. Calculate the similarity between the two: ,in, It is a feature The weight, It is a feature The range of values, It is a similarity score. It is the e-th characteristic value of the abnormal signal. It is the e-th feature value in the parasitic loop fault feature library; S32. Based on the fault feature record with the highest similarity, extract the following parasitic loop information from the fault feature database: Length: The equivalent conductor length of the parasitic loop, reflecting the physical extent of the faulty loop; Node distribution: The set of key nodes in a parasitic loop.

8. The method for rapid fault location in a power system secondary circuit according to claim 7, characterized in that, S3 further includes S33, which maps the extracted key node distribution to the actual loop in the loop topology graph G=(V,E), marks all nodes and paths related to the parasitic loop, and initially locates the fault node using the following conditions: The node closest to the high-risk node; The node with the strongest electromagnetic induction in the connected path; Output preliminary localization results.

Images