Chip reliability test interference synchronization method based on self-learning and related equipment

Abstract

The invention provides a self-learning-based chip reliability test interference synchronization method and related equipment, and the method comprises the steps: carrying out the self-learning interference delay after receiving a synchronous interference instruction outputted before a chip executes a sensitive instruction, triggering an interference source to generate an interference signal, and carrying out the self-learning interference delay in a self-learning process, if the operation state signal of the chip is not received in the waiting period, it is considered that the chip operates abnormally under the interference signal, and an abnormity confirmation signal is sent to the chip; and after the chip receives the abnormity confirmation signal, resetting the wrong sensitive instruction, continuing to carry out the self-learning process of the interference delay, and when the number of times of receiving the synchronous interference instruction reaches a preset number of times and the interference delay after self-learning is not less than the execution period, generating a test result of the chip according to the number of abnormities under all interference delays. The method does not need to use an oscilloscope or manually modify a delay parameter, adaptively adjusts the interference signal generation time, and further improves the automation efficiency of chip reliability problem detection in an interference environment.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a chip reliability testing interference synchronization method based on self-learning and related equipment. Background Art

[0002] At present, the interference generated by inductive loads, relays, etc. during startup or operation will have a strong impact on the main control chip, the "brain" of home appliances. Home appliances generally need to conduct periodic impact tests on various ports of the chip using a fast transient generator to generate interference pulse groups. They can only enter the market after meeting the relevant standards such as GB-T 17626.4-2008.

[0003] Although the interference pulse group impact test can detect chip reliability problems in an interference environment to a certain extent, the interference signal input time and the chip sensitive instruction execution time are asynchronous during the experiment. The interference signal cannot affect the sensitive instructions, resulting in many qualified products gradually exposing problems after entering the market. Summary of the invention

[0004] In view of this, the present application provides a chip reliability test interference synchronization method and related equipment based on self-learning, which improves the automation efficiency of chip reliability problem detection in an interference environment, reduces the difficulty of operation, and saves manpower and time costs.

[0005] The first aspect of the present application provides a chip reliability test interference synchronization method based on self-learning, comprising:

[0006] Receiving a synchronous interference instruction from a chip; wherein the chip executes the sensitive instruction according to an execution cycle and outputs the synchronous interference instruction before executing the sensitive instruction;

[0007] Setting the first interference delay and triggering the interference source to generate an interference signal;

[0008] If the operating status signal of the chip is not received within the waiting period, the number of abnormalities under the current first interference delay is recorded, and an abnormality confirmation signal is sent to the chip; wherein, after receiving the abnormality confirmation signal, the chip resets the erroneous sensitive instruction, continues to execute the sensitive instruction according to the execution cycle, and outputs a synchronous interference instruction before executing the sensitive instruction;

[0009] If the operating status signal of the chip is received during the waiting period, and the number of received synchronization interference instructions does not reach the preset number, the waiting period is reset, and the step of executing the synchronization interference instruction of the receiving chip is returned;

[0010] If the number of received synchronization interference instructions reaches a preset number, the first interference delay is increased by a preset step length to obtain a second interference delay;

[0011] If the second interference delay is less than the execution period, the second interference delay is used as the new first interference delay, and the process returns to the step of setting the first interference delay and triggering the interference source to generate an interference signal;

[0012] If the second interference delay is not less than the execution period, a test result of the chip is generated according to the number of exceptions under all first interference delays.

[0013] Optionally, if the second interference delay is not less than the execution period, generating a test result of the chip according to the number of exceptions under all first interference delays, includes:

[0014] If the number of abnormalities under all first interference delays is 0, a normal test result of the chip is generated;

[0015] If the number of abnormalities under any first interference delay is not 0, a test result of chip abnormality is generated.

[0016] Optionally, if the second interference delay is not less than the execution period, after generating the test result of the chip according to the number of exceptions under all first interference delays, the method further includes:

[0017] If the test result of the chip indicates that the chip is abnormal, a normal distribution curve is generated according to the number of abnormalities corresponding to the chip under each first interference delay.

[0018] Optionally, if the test result of the chip indicates that the chip is abnormal, after generating a normal distribution curve according to the number of abnormalities corresponding to the chip under each first interference delay, the method further includes:

[0019] When a target chip is tested, the target interference delay in the normal distribution curve is selected as the first interference delay, and the steps of setting the first interference delay and triggering the interference source to generate an interference signal are performed.

[0020] The second aspect of the present application provides a chip reliability test interference synchronization device based on self-learning, comprising:

[0021] A receiving unit, used to receive a synchronous interference instruction from a chip; wherein the chip executes sensitive instructions according to an execution cycle and outputs the synchronous interference instruction before executing the sensitive instruction;

[0022] A trigger unit, used to set a first interference delay and trigger an interference source to generate an interference signal;

[0023] A sending unit, configured to record the number of abnormalities under the current first interference delay if the operating status signal of the chip is not received within the waiting period, and send an abnormality confirmation signal to the chip; wherein, after receiving the abnormality confirmation signal, the chip resets the erroneous sensitive instruction, continues to execute the sensitive instruction according to the execution cycle, and outputs a synchronous interference instruction before executing the sensitive instruction;

[0024] A first activation unit, configured to reset the waiting period and activate the receiving unit to execute the step of receiving the synchronous interference instruction of the chip if the operating status signal of the chip is received within the waiting period and the number of received synchronous interference instructions does not reach a preset number;

[0025] A first generating unit, configured to increase the first interference delay by a preset step length to obtain a second interference delay if the number of received synchronization interference instructions reaches a preset number;

[0026] A second activation unit, configured to use the second interference delay as a new first interference delay if the second interference delay is less than an execution period, activate the trigger unit to execute the step of setting the first interference delay, and trigger the interference source to generate an interference signal;

[0027] The second generating unit is used to generate the test result of the chip according to the number of exceptions under all the first interference delays if the second interference delay is not less than the execution period.

[0028] Optionally, the second generating unit includes:

[0029] A second generating subunit is used to generate a normal test result of the chip if the number of abnormalities under all first interference delays is 0;

[0030] The second generating subunit is further configured to generate a chip abnormality test result if the number of abnormalities under any first interference delay is not 0.

[0031] Optionally, the chip reliability test interference synchronization device based on self-learning further includes:

[0032] The third generating unit is configured to generate a normal distribution curve according to the number of abnormalities corresponding to the chip under each first interference delay if the test result of the chip indicates that the chip is abnormal.

[0033] Optionally, the chip reliability test interference synchronization device based on self-learning further includes:

[0034] The selection unit is used to select the target interference delay in the normal distribution curve as the first interference delay when a target chip is tested, execute the step of setting the first interference delay, and trigger the interference source to generate an interference signal.

[0035] A third aspect of the present application provides an electronic device, including:

[0036] one or more processors;

[0037] a storage device having one or more programs stored thereon;

[0038] When the one or more programs are executed by the one or more processors, the one or more processors implement the chip reliability test interference synchronization method based on self-learning as described in any one of the first aspects.

[0039] A fourth aspect of the present application provides a computer storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the chip reliability test interference synchronization method based on self-learning as described in any one of the first aspects is implemented.

[0040] It can be seen from the above scheme that the present application provides a chip reliability test interference synchronization method and related equipment based on self-learning, by performing self-learning interference delay after receiving the synchronous interference instruction output before the chip executes the sensitive instruction, and triggering the interference source to generate an interference signal. In the process of self-learning, if the operating status signal of the chip is not received within the waiting period, it is considered that the chip is operating abnormally under the interference signal, and an abnormal confirmation signal is sent to the chip; after receiving the abnormal confirmation signal, the chip resets the erroneous sensitive instruction to continue the self-learning process of interference delay. When the number of synchronous interference instructions received reaches the preset number, and the interference delay after self-learning is not less than the execution cycle, the test result of the chip is generated according to the number of abnormalities under all interference delays. This application does not need to use an oscilloscope or manually modify the delay parameters. Through online learning of the occurrence time of interference signals, sensitive instructions and chip abnormalities, the interference signal generation time is adaptively adjusted to achieve synchronization with sensitive instructions, further improving the automation efficiency of chip reliability problem detection under interference environment, reducing the difficulty of operation, and saving manpower and time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0042] Figure 1 A specific flow chart of a chip reliability test interference synchronization method based on self-learning provided in an embodiment of the present application;

[0043] Figure 2A schematic diagram of an interference delay and an execution cycle of a sensitive instruction provided by another embodiment of the present application;

[0044] Figure 3 A schematic diagram of a chip reliability test interference synchronization device based on self-learning provided in another embodiment of the present application;

[0045] Figure 4 A schematic diagram of an electronic device for implementing a chip reliability test interference synchronization method based on self-learning is provided as another embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0048] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0049] It should be noted that the concepts such as "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0050] It should be noted that the modifications of "one" and "plurality" mentioned in the present application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0051] The embodiment of the present application provides a chip reliability test interference synchronization method based on self-learning, such as Figure 1 As shown, the specific steps include:

[0052] S101, receiving a synchronous interference instruction from a chip.

[0053] The chip executes sensitive instructions according to the execution cycle and outputs synchronization interference instructions before executing the sensitive instructions. The chip can be, but is not limited to, a microcontroller unit (MCU), which is not limited here.

[0054] It is understandable that the execution cycles of different sensitive instructions may be different, and the execution cycle may be adjusted according to the type of sensitive instructions, which is not limited here.

[0055] It should be noted that sensitive instructions include but are not limited to the stacking and popping operations of the interruption site by periodic clock interrupts, which are not limited here. The execution cycle is pre-set by technicians, experts, etc., which is also not limited here.

[0056] In the specific implementation process of the present application, key sensitive instructions, pre-designated sensitive instructions, etc. can also be selected as target sensitive instructions, and synchronous interference instructions are only output before the target sensitive instructions to achieve the purpose of focusing on the target sensitive instructions.

[0057] S102: Set a first interference delay and trigger an interference source to generate an interference signal.

[0058] At the beginning of the test, the first interference delay can be set to 0, or can be set to other values ​​according to actual conditions, which is not limited here.

[0059] In the specific implementation process of the present application, after the interference source is triggered to generate an interference signal, the operating status signal sent by the receiving chip is continuously waited for. Specifically, it can be implemented using but not limited to the general GIPO interface, which is not limited here.

[0060] It is understandable that if the chip can operate normally in an interference environment (the interference signal generated by the interference source interferes with the chip), the chip can send the operating status signal according to a preset sending period (for example, 0.5ms), otherwise the operating status signal cannot be sent.

[0061] S103: If the chip operation status signal is not received within the waiting period, the number of abnormalities under the current first interference delay is recorded, and an abnormality confirmation signal is sent to the chip.

[0062] Among them, after receiving the abnormal confirmation signal, the chip resets the erroneous sensitive instructions, continues to execute the sensitive instructions according to the execution cycle, and outputs the synchronous interference instructions before executing the sensitive instructions.

[0063] It should be noted that the waiting period is pre-set and changed by technicians, experts, etc. and is not limited here.

[0064] Specifically, if the chip operating status signal is not received during the waiting period, it is confirmed that the chip has an abnormality in the interference environment, and the number of abnormalities under the current first interference delay is recorded. For example: if the current first interference delay is t1, the number of abnormalities of t1 is increased by 1, and an abnormality confirmation signal is sent to the chip.

[0065] S104: If a chip operation status signal is received during the waiting period, it is determined whether the number of received synchronization interference instructions reaches a preset number.

[0066] The preset number of times is set and changed in advance by technicians, experts, etc., including but not limited to 100,000 times, etc., and is not limited here.

[0067] Specifically, if it is determined that the number of received synchronization interference instructions does not reach the preset number, step S105 is executed; if it is determined that the number of received synchronization interference instructions reaches the preset number, step S106 is executed.

[0068] S105: Reset the waiting period.

[0069] S106: Increase the first interference delay by a preset step length to obtain a second interference delay.

[0070] Among them, the preset step size is set and changed in advance by technicians, experts, etc. and is not limited here.

[0071] In the specific implementation process of this application, the preset step size is generally selected to be less than half of the chip single instruction cycle. The single instruction cycle of the MCU-level main control chip is generally 10-100ns, that is, 5ns can be selected, and there is no limitation here.

[0072] S107: Determine whether the second interference delay is less than the execution period.

[0073] In the specific implementation process of the present application, during the self-learning process of the interference delay, it increases with a preset step size to select a better interference delay, but the increase of the interference delay has a fixed limit, such as Figure 2 As shown in Figure 2, when the interference delay increases to the execution cycle T of the sensitive instruction, it stops increasing. If it continues to increase, it will be repeated in the next sensitive instruction, which has no practical significance. When , the preset step size is stopped (t0 is the initial interference delay at the beginning of the test, is the total delay after each step increase during the learning process, that is, the second interference delay).

[0074] Specifically, if the second interference delay is less than the execution period, step S108 is executed; if the second interference delay is not less than the execution period, step S109 is executed.

[0075] S108: Use the second interference delay as a new first interference delay.

[0076] S109: Generate a chip test result according to the number of abnormalities under all first interference delays.

[0077] In the specific implementation process of the present application, the test results of the chip can be generated according to the number of exceptions under the first interference delay. If the number of exceptions under all first interference delays is 0, a normal test result of the chip is generated; if the number of exceptions under any first interference delay is not 0, an abnormal test result of the chip is generated, or if the number of exceptions under all first interference delays is lower than the abnormal number threshold, a normal test result of the chip is generated; if the number of exceptions under any first interference delay is not lower than the abnormal number threshold, an abnormal test result of the chip is generated.

[0078] It should be noted that the abnormal number threshold is set and changed in advance by technicians, experts, etc. and is not limited here.

[0079] It can be understood that the above is only an example of an implementation method for generating chip test results based on the number of abnormalities under all first interference delays. The abnormal frequency under all first interference delays and a preset frequency threshold can also be used to generate chip test results.

[0080] The abnormal frequency under the first interference delay can be obtained by, but is not limited to, calculating the quotient of the number of abnormalities under the first interference delay and the number of synchronization interference instructions under the first interference delay as the abnormal frequency under the first interference delay, which is not limited here.

[0081] It should be noted that the preset frequency threshold is set and changed in advance by technicians, experts, etc. and is not limited here.

[0082] Specifically, if the abnormal frequencies under all first interference delays are lower than the preset frequency threshold, a normal chip test result is generated; if the abnormal frequencies under any first interference delay are not lower than the preset frequency threshold, an abnormal chip test result is generated.

[0083] Optionally, in another embodiment of the present application, an implementation of a chip reliability test interference synchronization method based on self-learning further includes:

[0084] If the test result of the chip indicates that the chip is abnormal, a normal distribution curve is generated according to the number of abnormalities corresponding to the chip under each first interference delay.

[0085] Specifically, for each first interference delay, an abnormal frequency is generated according to the number of abnormalities corresponding to the chip under each first interference delay, and a result that conforms to the normal distribution is fitted according to the abnormal frequency corresponding to the chip under each first interference delay to obtain a normal distribution curve.

[0086] In the specific implementation process of the present application, the normal distribution curve can be saved in the synchronous interference device. When other chips in the same batch or abnormal chips are subsequently tested, the normal distribution curve can be directly used for testing, which is not limited here.

[0087] Optionally, in another embodiment of the present application, an implementation of a chip reliability test interference synchronization method based on self-learning further includes:

[0088] When a target chip is tested, a target interference delay in a normal distribution curve is selected as a first interference delay, and then the steps of setting the first interference delay and triggering an interference source to generate an interference signal are started for testing.

[0089] The target chips include, but are not limited to, chips from the same batch as the tested chips, chips that have abnormalities and require analysis of the causes of the abnormalities, etc., and are not limited here.

[0090] In the specific implementation process of the present application, the target interference delay may be but is not limited to N interference delays near the center point of the normal distribution curve, where N is a positive integer and is pre-set by technicians, experts, etc. and is not limited here.

[0091] By using the normal distribution curve, the reliability of the chip in an interference environment can be quickly tested, and the problem points of the abnormal chip can be quickly located.

[0092] It can be seen from the above scheme that the present application provides a chip reliability test interference synchronization method based on self-learning, by performing self-learning interference delay after receiving the synchronous interference instruction output before the chip executes the sensitive instruction, and triggering the interference source to generate an interference signal. In the process of self-learning, if the operating status signal of the chip is not received within the waiting period, it is considered that the chip is operating abnormally under the interference signal, and an abnormal confirmation signal is sent to the chip; after receiving the abnormal confirmation signal, the chip resets the erroneous sensitive instruction to continue the self-learning process of interference delay. When the number of synchronous interference instructions received reaches the preset number, and the interference delay after self-learning is not less than the execution cycle, the test result of the chip is generated according to the number of abnormalities under all interference delays. This application does not need to use an oscilloscope or manually modify the delay parameters. Through online learning of the occurrence time of interference signals, sensitive instructions and chip abnormalities, the interference signal generation time is adaptively adjusted to achieve synchronization with sensitive instructions, further improving the automation efficiency of chip reliability problem detection under interference environment, reducing the difficulty of operation, and saving manpower and time costs.

[0093] The embodiment of the present application provides a chip reliability test interference synchronization device based on self-learning, such as Figure 3 As shown, specifically including:

[0094] The receiving unit 301 is used to receive a synchronous interference instruction from a chip.

[0095] The chip executes sensitive instructions according to the execution cycle and outputs synchronous interference instructions before executing the sensitive instructions.

[0096] The trigger unit 302 is used to set a first interference delay and trigger the interference source to generate an interference signal.

[0097] The sending unit 303 is used to record the number of abnormalities under the current first interference delay if the chip operation status signal is not received within the waiting period, and send an abnormality confirmation signal to the chip.

[0098] Among them, after receiving the abnormal confirmation signal, the chip resets the erroneous sensitive instructions, continues to execute the sensitive instructions according to the execution cycle, and outputs the synchronous interference instructions before executing the sensitive instructions.

[0099] The first activation unit 304 is used to reset the waiting period and activate the receiving unit to execute the step of receiving the chip's synchronous interference instruction if the chip's operating status signal is received within the waiting period and the number of received synchronous interference instructions does not reach a preset number.

[0100] The first generating unit 305 is configured to increase the first interference delay by a preset step length to obtain a second interference delay if the number of received synchronization interference instructions reaches a preset number.

[0101] The second activation unit 306 is used to use the second interference delay as a new first interference delay if the second interference delay is smaller than the execution period, activate the trigger unit to execute the step of setting the first interference delay, and trigger the interference source to generate an interference signal.

[0102] The second generating unit 307 is configured to generate a test result of the chip according to the number of exceptions under all first interference delays if the second interference delay is not less than the execution period.

[0103] For the specific working process of the units disclosed in the above embodiments of the present application, please refer to the corresponding method embodiments, such as Figure 1 As shown, no further description is given here.

[0104] Optionally, in another embodiment of the present application, an implementation of the second generating unit 307 includes:

[0105] The second generating subunit is used to generate a normal test result of the chip if the number of abnormalities under all first interference delays is 0.

[0106] The second generating subunit is further configured to generate a chip abnormality test result if the number of abnormalities under any first interference delay is not 0.

[0107] The specific working process of the units disclosed in the above embodiments of the present application can be found in the corresponding method embodiments, which will not be repeated here.

[0108] Optionally, in another embodiment of the present application, an implementation of a chip reliability test interference synchronization device based on self-learning includes:

[0109] The third generating unit is configured to generate a normal distribution curve according to the number of abnormalities corresponding to each first interference delay of the chip if the test result of the chip indicates that the chip is abnormal.

[0110] The specific working process of the units disclosed in the above embodiments of the present application can be found in the corresponding method embodiments, which will not be repeated here.

[0111] Optionally, in another embodiment of the present application, an implementation of a chip reliability test interference synchronization device based on self-learning includes:

[0112] The selection unit is used to select the target interference delay in the normal distribution curve as the first interference delay when a target chip is tested, execute the step of setting the first interference delay, and trigger the interference source to generate an interference signal.

[0113] The specific working process of the units disclosed in the above embodiments of the present application can be found in the corresponding method embodiments, which will not be repeated here.

[0114] It can be seen from the above scheme that the present application provides a chip reliability test interference synchronization device based on self-learning, by performing self-learning interference delay after receiving the synchronous interference instruction output before the chip executes the sensitive instruction, and triggering the interference source to generate an interference signal. In the process of self-learning, if the operating status signal of the chip is not received within the waiting period, it is considered that the chip is operating abnormally under the interference signal, and an abnormal confirmation signal is sent to the chip; after receiving the abnormal confirmation signal, the chip resets the erroneous sensitive instruction to continue the self-learning process of interference delay. When the number of synchronous interference instructions received reaches the preset number, and the interference delay after self-learning is not less than the execution cycle, the test result of the chip is generated according to the number of abnormalities under all interference delays. This application does not need to use an oscilloscope or manually modify the delay parameters. Through online learning of the occurrence time of interference signals, sensitive instructions and chip abnormalities, the interference signal generation time is adaptively adjusted to achieve synchronization with sensitive instructions, further improving the automation efficiency of chip reliability problem detection under interference environment, reducing the difficulty of operation, and saving manpower and time costs.

[0115] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0116] Another embodiment of the present application provides an electronic device, such as Figure 4 As shown, including:

[0117] One or more processors 401 .

[0118] The storage device 402 stores one or more programs.

[0119] When the one or more programs are executed by the one or more processors 401, the one or more processors 401 implement the chip reliability test interference synchronization method based on self-learning as described in any one of the above embodiments.

[0120] Another embodiment of the present application provides a computer storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the chip reliability test interference synchronization method based on self-learning as described in any one of the above embodiments is implemented.

[0121] In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0122] It should be noted that the computer-readable medium mentioned above in the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0123] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0124] Another embodiment of the present application provides a computer program product. When the computer program product is executed, it is used to execute the above-mentioned chip reliability test interference synchronization method based on self-learning.

[0125] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processing device, the above-mentioned functions defined in the method of the embodiment of the present application are executed.

[0126] Although the subject matter has been described in language specific to structural features and / or method logic actions, it should be understood that the subject matter defined in this application is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing this application.

[0127] Although several specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present application. Certain features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0128] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of application involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above application concept. For example, the above features are replaced with (but not limited to) technical features with similar functions applied in the present application.

Claims

1. A chip reliability test interference synchronization method based on self-learning, characterized in that: include: Receiving a synchronous interference instruction from a chip; wherein the chip executes the sensitive instruction according to an execution cycle and outputs the synchronous interference instruction before executing the sensitive instruction; Setting the first interference delay and triggering the interference source to generate an interference signal; If the operating status signal of the chip is not received within the waiting period, the number of abnormalities under the current first interference delay is recorded, and an abnormality confirmation signal is sent to the chip; wherein, after receiving the abnormality confirmation signal, the chip resets the erroneous sensitive instruction, continues to execute the sensitive instruction according to the execution cycle, and outputs a synchronous interference instruction before executing the sensitive instruction; If the operating status signal of the chip is received during the waiting period, and the number of received synchronization interference instructions does not reach the preset number, the waiting period is reset, and the step of executing the synchronization interference instruction of the receiving chip is returned; If the number of received synchronization interference instructions reaches a preset number, the first interference delay is increased by a preset step length to obtain a second interference delay; If the second interference delay is less than the execution period, the second interference delay is used as the new first interference delay, and the process returns to the step of setting the first interference delay and triggering the interference source to generate an interference signal; If the second interference delay is not less than the execution period, a test result of the chip is generated according to the number of exceptions under all first interference delays.

2. The chip reliability test interference synchronization method based on self-learning according to claim 1 is characterized in that: If the second interference delay is not less than the execution period, generating a test result of the chip according to the number of exceptions under all first interference delays, including: If the number of abnormalities under all first interference delays is 0, a normal test result of the chip is generated; If the number of abnormalities under any first interference delay is not 0, a test result of chip abnormality is generated.

3. The chip reliability test interference synchronization method based on self-learning according to claim 1 is characterized in that: If the second interference delay is not less than the execution period, after generating the test result of the chip according to the number of exceptions under all the first interference delays, the method further includes: If the test result of the chip indicates that the chip is abnormal, a normal distribution curve is generated according to the number of abnormalities corresponding to the chip under each first interference delay.

4. The chip reliability test interference synchronization method based on self-learning according to claim 3 is characterized in that: If the test result of the chip indicates that the chip is abnormal, after generating a normal distribution curve according to the number of abnormalities corresponding to the chip under each first interference delay, the method further includes: When a target chip is tested, the target interference delay in the normal distribution curve is selected as the first interference delay, and the steps of setting the first interference delay and triggering the interference source to generate an interference signal are performed.

5. A chip reliability test interference synchronization device based on self-learning, characterized in that: include: A receiving unit, used to receive a synchronous interference instruction from a chip; wherein the chip executes sensitive instructions according to an execution cycle and outputs the synchronous interference instruction before executing the sensitive instruction; A trigger unit, used to set a first interference delay and trigger an interference source to generate an interference signal; A sending unit, configured to record the number of abnormalities under the current first interference delay if the operating status signal of the chip is not received within the waiting period, and send an abnormality confirmation signal to the chip; wherein, after receiving the abnormality confirmation signal, the chip resets the erroneous sensitive instruction, continues to execute the sensitive instruction according to the execution cycle, and outputs a synchronous interference instruction before executing the sensitive instruction; A first activation unit, configured to reset the waiting period and activate the receiving unit to execute the step of receiving the synchronous interference instruction of the chip if the operating status signal of the chip is received within the waiting period and the number of received synchronous interference instructions does not reach a preset number; A first generating unit, configured to increase the first interference delay by a preset step length to obtain a second interference delay if the number of received synchronization interference instructions reaches a preset number; A second activation unit, configured to use the second interference delay as a new first interference delay if the second interference delay is less than an execution period, activate the trigger unit to execute the step of setting the first interference delay, and trigger the interference source to generate an interference signal; The second generating unit is used to generate the test result of the chip according to the number of exceptions under all the first interference delays if the second interference delay is not less than the execution period.

6. The chip reliability test interference synchronization device based on self-learning according to claim 5, characterized in that: The second generating unit comprises: A second generating subunit is used to generate a normal test result of the chip if the number of abnormalities under all first interference delays is 0; The second generating subunit is further configured to generate a chip abnormality test result if the number of abnormalities under any first interference delay is not 0.

7. The chip reliability test interference synchronization device based on self-learning according to claim 5, characterized in that: Also includes: The third generating unit is configured to generate a normal distribution curve according to the number of abnormalities corresponding to the chip under each first interference delay if the test result of the chip indicates that the chip is abnormal.

8. The chip reliability test interference synchronization device based on self-learning according to claim 7, characterized in that: Also includes: The selection unit is used to select the target interference delay in the normal distribution curve as the first interference delay when a target chip is tested, execute the step of setting the first interference delay, and trigger the interference source to generate an interference signal.

9. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the chip reliability test interference synchronization method based on self-learning as described in any one of claims 1 to 4.

10. A computer storage medium, characterized in that: A computer program is stored thereon, wherein when the computer program is executed by a processor, the chip reliability test interference synchronization method based on self-learning as claimed in any one of claims 1 to 4 is implemented.

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