A method, device, electronic device, and storage medium for processing process abnormality

Abstract

The present disclosure provides a method for handling process exceptions. After determining that there is an abnormal thread in the target process, a stack capture operation is performed on the abnormal thread to obtain thread stack information corresponding to the abnormal thread; a first processing thread is called to perform address resolution on the thread stack information to obtain address information of the function stored in the memory; a second processing thread is called to perform cross-process resolution on the address information of the function stored in the memory to obtain attribute information of the function and a hierarchical relationship of function calls; the attribute information of the function and the hierarchical relationship of function calls are sent to a server so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls. Through the stack capture operation at the lightweight thread level, the interference to other parts of the system is reduced, and the stability and reliability of the system are improved. The state of the abnormal thread is accurately captured without significantly affecting the system performance, thereby providing information for subsequent fault diagnosis and repair.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing, and in particular to a process exception handling method, device, electronic device, and storage medium. Background Art

[0002] Existing systems often handle process exceptions by recording data, collecting logs, and collecting thread stack information. However, traditional exception handling methods require pausing the process, including all threads, when performing thread stack capture, which can severely impact system performance. Especially in complex multi-threaded systems, globally pausing threads can degrade overall system functionality. Summary of the Invention

[0003] The present disclosure provides a method and device for handling process exceptions, an electronic device, a storage medium, and a chip to solve problems in related technologies and avoid degradation of overall system functionality caused by globally pausing threads.

[0004] A first embodiment of the present disclosure provides a method for handling process abnormalities, the method comprising:

[0005] After determining that an abnormal thread exists in the target process, performing a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread;

[0006] Calling a first processing thread to perform address resolution on the thread stack information to obtain address information of functions stored in a memory, wherein the thread stack information includes call records of all functions;

[0007] Calling a second processing thread to perform cross-process analysis on the address information of the function stored in the memory to obtain attribute information of the function and a function call hierarchy relationship;

[0008] The attribute information of the function and the hierarchical relationship of function calls are sent to the server so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls.

[0009] In some embodiments of the present disclosure, calling the second processing thread to perform cross-process parsing on the address information of the function stored in the memory to obtain the attribute information of the function and the function call hierarchy relationship includes:

[0010] Read the symbol table of the shared object files corresponding to all processes;

[0011] The second processing thread is called to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and a function call hierarchy relationship.

[0012] In some embodiments of the present disclosure, the calling of the second processing thread to parse all symbol tables and address information of the function stored in the memory to obtain attribute information of the function and a function call hierarchy relationship includes:

[0013] The second processing thread calls a preset function address resolution tool;

[0014] The preset function address parsing tool is used to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

[0015] In some embodiments of the present disclosure, the method further includes:

[0016] Independent memory spaces of preset sizes are allocated to the first processing thread and the second processing thread respectively.

[0017] In some embodiments of the present disclosure, after determining that an abnormal thread exists in a target process, before performing a stack capture operation on the abnormal thread and obtaining thread stack information corresponding to the abnormal thread, the method further includes:

[0018] Control and start a monitoring node, which is used to monitor the heartbeat data packets sent to each thread in the target process:

[0019] Monitor whether there is an abnormal thread that times out in response to the heartbeat data packet;

[0020] If so, the identification information of the abnormal thread is stored in a preset storage queue.

[0021] In some embodiments of the present disclosure, executing a stack capture operation on the abnormal thread includes:

[0022] When it is detected that the preset storage queue is in a non-empty state, reading identification information of the abnormal thread from the preset storage queue;

[0023] A stack capture operation is performed on the abnormal thread corresponding to the identification information.

[0024] In some embodiments of the present disclosure, before executing the stack capture operation on the abnormal thread, the method further includes:

[0025] Determine the current process state of the target process, and determine whether the current process state is in a stack capture state, a sampling collection state, or a transfer state;

[0026] The executing of the stack capture operation on the abnormal thread includes:

[0027] If the current state does not include a stack capture state, a collection and sampling state, or a transfer state, a stack capture operation is performed on the abnormal thread.

[0028] A second embodiment of the present disclosure provides a device for processing process abnormalities, the device comprising:

[0029] An execution unit, configured to, after determining that an abnormal thread exists in a target process, execute a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread;

[0030] An address resolution unit, configured to call a first processing thread to perform address resolution on the thread stack information to obtain address information of functions stored in a memory, wherein the thread stack information includes call records of all functions;

[0031] a process parsing unit, configured to call a second processing thread to perform cross-process parsing on the address information of the function stored in the memory, and obtain attribute information of the function and a function call hierarchy relationship;

[0032] The positioning unit is used to send the attribute information of the function and the function call hierarchy relationship to the server, so that the server can locate the abnormal code according to the attribute information of the function and the function call hierarchy relationship.

[0033] In some embodiments of the present disclosure, the process parsing unit further includes:

[0034] The reading module is used to read the symbol table of the shared object files corresponding to all processes;

[0035] The parsing module is used to call the second processing thread to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchical relationships.

[0036] In some embodiments of the present disclosure, the parsing module is further configured to:

[0037] The second processing thread calls a preset function address resolution tool;

[0038] The preset function address parsing tool is used to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

[0039] In some embodiments of the present disclosure, the apparatus further comprises:

[0040] An allocation unit allocates independent memory spaces of preset sizes to the first processing thread and the second processing thread respectively.

[0041] In some embodiments of the present disclosure, the apparatus further comprises:

[0042] The control unit is configured to, after the execution unit determines that there is an abnormal thread in the target process, execute a stack capture operation on the abnormal thread, and before obtaining thread stack information corresponding to the abnormal thread, control the startup of a monitoring node, wherein the monitoring node is configured to monitor heartbeat data packets sent to each thread in the target process:

[0043] A monitoring unit, configured to monitor whether there is an abnormal thread that times out in responding to the heartbeat data packet;

[0044] The storage unit is configured to store identification information of the abnormal thread in a preset storage queue when there is an abnormal thread that times out in responding to the heartbeat data packet.

[0045] In some embodiments of the present disclosure, the execution unit includes:

[0046] A reading module, configured to read the identification information of the abnormal thread from the preset storage queue when detecting that the preset storage queue is in a non-empty state;

[0047] The stack capture module is used to perform a stack capture operation on the abnormal thread corresponding to the identification information.

[0048] In some embodiments of the present disclosure, the device further comprises:

[0049] a determination unit configured to determine, before the execution unit executes the stack capture operation on the abnormal thread, the current process state of the target process and determine whether the current process state is in a stack capture state, a sampling state, or a transfer state;

[0050] The execution unit is further configured to:

[0051] When the current state does not include a stack capture state, a collection and sampling state, or a transfer state, a stack capture operation is performed on the abnormal thread.

[0052] The third aspect embodiment of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method described in the first aspect embodiment of the present disclosure.

[0053] The fourth aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the method described in the first aspect embodiment of the present disclosure.

[0054] The fifth aspect embodiment of the present disclosure proposes a chip, which includes one or more interfaces and one or more processors; the interface is used to receive signals from the memory of the electronic device and send signals to the processor, the signals including computer instructions stored in the memory, and when the processor executes the computer instructions, the electronic device executes the method described in the first aspect embodiment of the present disclosure.

[0055] In summary, according to the method for handling process exceptions proposed in the present disclosure, the method includes, after determining that there is an abnormal thread in the target process, executing a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread; calling a first processing thread to perform address resolution on the thread stack information to obtain address information of the function stored in the memory, wherein the thread stack information contains call records of all functions; calling a second processing thread to perform cross-process resolution on the address information of the function stored in the memory to obtain attribute information of the function and a hierarchical relationship of function calls; sending the attribute information of the function and the hierarchical relationship of function calls to a server so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls. The solution disclosed in the present disclosure reduces interference to other parts of the system and improves the stability and reliability of the system through a lightweight thread-level stack capture operation. It accurately captures the status of the abnormal thread without significantly affecting the system performance, thereby providing information for subsequent fault diagnosis and repair.

[0056] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute an improper limitation of the present disclosure.

[0058] Figure 1 A flowchart of a method for handling process abnormalities provided by an embodiment of the present disclosure;

[0059] Figure 2 A flowchart of another method for handling process abnormalities provided by an embodiment of the present disclosure;

[0060] Figure 3 A flowchart of another method for handling process abnormalities provided by an embodiment of the present disclosure;

[0061] Figure 4 A flowchart of another method for handling process abnormalities provided by an embodiment of the present disclosure;

[0062] Figure 5A flowchart of another method for handling process abnormalities provided by an embodiment of the present disclosure;

[0063] Figure 6 A schematic diagram of the structure of a device for handling process anomalies provided by an embodiment of the present disclosure;

[0064] Figure 7 A schematic diagram of the structure of another device for handling process abnormalities provided by an embodiment of the present disclosure;

[0065] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure;

[0066] Figure 9 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0068] The embodiments of the present disclosure are not exhaustive and are merely illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present disclosure. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementation methods in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined. For example, some or all steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0069] In each embodiment of the present disclosure, unless otherwise specified or provided for by logic, the terms and / or descriptions between the embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form a new embodiment based on their inherent logical relationships.

[0070] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0071] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular, such as "a", "an", "the", "above", "said", "the", "the", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun following the article may be understood as a singular expression or a plural expression.

[0072] In some embodiments, terms such as "in response to...", "in response to determining...", "in the case of...", "at the time of...", "when...", "if...", "if...", etc. can be used interchangeably.

[0073] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", and "above" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.

[0074] The prefixes such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different description objects and do not constitute any restrictions on the position, order, priority, quantity or content of the description objects. For the statement of the description objects, please refer to the description in the context of the claims or embodiments, and no unnecessary restrictions should be constituted due to the use of prefixes.

[0075] In the embodiments of the present disclosure, “plurality” refers to two or more.

[0076] In the embodiments of the present disclosure, terms such as “import”, “input”, and “read in” can be used interchangeably.

[0077] In some embodiments, devices, etc. can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", and "subject" can be used interchangeably.

[0078] In some embodiments, the terms "terminal", "terminal device", "user equipment (UE)", "user terminal", "mobile station (MS)", "mobile terminal (MT)", subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handset, user agent, mobile client, client, etc. can be used interchangeably.

[0079] Figure 1 This is a flowchart of a method for handling process anomalies provided by an embodiment of the present disclosure. This method can be applied to application scenarios such as smart terminals, for example, by a terminal with integrated process anomaly handling function or a process anomaly processor in the terminal, or by other devices suitable for handling process anomalies, and this disclosure is not limited thereto. Figure 1 As shown, the method for handling the process abnormality includes steps 101-104.

[0080] Step 101: After determining that an abnormal thread exists in a target process, a stack capture operation is performed on the abnormal thread to obtain thread stack information corresponding to the abnormal thread.

[0081] In some embodiments, the target process is a specific application or service that needs to be monitored or debugged. A process may typically contain multiple threads, and different threads are used to handle different tasks. In application scenarios, some threads may exhibit abnormal behavior due to various reasons (such as editing errors, resource competition, external input, etc.). Abnormal threads will affect the performance of the process and increase the system's resource consumption.

[0082] By capturing the stack of the abnormal thread, only the thread stack information of the abnormal thread is captured. The thread stack information contains all function calls from the startup of the abnormal thread to the occurrence of the exception, including the return address, local variables and parameters of each function.

[0083] Step 102: Call the first processing thread to perform address resolution on the thread stack information to obtain address information of functions stored in the memory, wherein the thread stack information includes call records of all functions.

[0084] In some embodiments, when address resolution is performed on the thread stack information of the faulty thread based on the first processing thread, all function call records are extracted from the thread stack information and parsed in conjunction with reading the symbol table to determine the specific address of each function in memory. For methods of obtaining address information of functions stored in memory, please refer to any implementation in the prior art, and this embodiment of the present application will not be further described in detail.

[0085] Step 103: Call the second processing thread to perform cross-process analysis on the address information of the function stored in the memory to obtain the attribute information of the function and the function call hierarchy relationship.

[0086] Based on the analysis of the first processing thread, the address information of the function stored in the memory is further parsed across processes to collect the attribute information of each function, such as name, parameter type and return type, and obtain the calling hierarchy relationship between functions to build a clear function call graph, so as to better understand the context of the exception.

[0087] For specific implementation methods, please refer to any implementation method in the prior art, such as GNU Debugger (GDB), Address to Line (addr2line), etc. The embodiments of this application will not be described one by one here.

[0088] The first processing thread and the second processing thread described in the embodiment of the present application are independent of each other, and each thread is allocated an independent memory space. In addition, after the first processing thread obtains a specific parsing result, the second processing thread continues to parse based on the parsing result of the first processing thread. It should be noted that after obtaining the solution result, the first processing thread will continue to execute step 102 instead of waiting for the parsing result of the second processing thread. The two run non-serially, which improves the efficiency of exception handling.

[0089] Step 104: Send the attribute information of the function and the hierarchical relationship of function calls to the server, so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls.

[0090] The function's attribute information and function call hierarchy are sent to the server, allowing the server to locate the abnormal code based on the function's attribute information and function call hierarchy. After receiving the data, the server can parse this information based on pre-designed algorithms and logic, constructing a complete function call graph and attribute database to identify potential abnormal patterns or error paths. For example, it can detect which function call chains lead to performance bottlenecks, or which function parameter combinations frequently cause runtime errors.

[0091] In summary, according to the method for handling process exceptions proposed in the present disclosure, the method includes, after determining that there is an abnormal thread in the target process, executing a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread; calling a first processing thread to perform address resolution on the thread stack information to obtain address information of the function stored in the memory, wherein the thread stack information contains call records of all functions; calling a second processing thread to perform cross-process resolution on the address information of the function stored in the memory to obtain attribute information of the function and a hierarchical relationship of function calls; sending the attribute information of the function and the hierarchical relationship of function calls to a server so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls. The solution disclosed in the present disclosure reduces interference to other parts of the system and improves the stability and reliability of the system through a lightweight thread-level stack capture operation. It accurately captures the status of the abnormal thread without significantly affecting the system performance, thereby providing information for subsequent fault diagnosis and repair.

[0092] In some embodiments, the symbol table of files across different shared objects cannot be directly obtained. Therefore, when performing cross-process parsing, the parsing can be performed according to the following steps. Figure 2 , Figure 2 A flowchart of a method for handling process abnormalities provided in an embodiment of the present disclosure includes:

[0093] Step 201: Read the symbol tables of the shared object files corresponding to all processes.

[0094] In some embodiments, the symbol tables corresponding to all shared object files contain the function's name, address, and other key attribute information. By parsing the symbol table, a detailed mapping relationship between functions in each process can be constructed, providing basic data for subsequent cross-process analysis.

[0095] Step 202: Call the second processing thread to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

[0096] During the parsing process, the second processing thread traverses all collected symbol tables and memory address information, analyzing each function one by one, extracting attribute information such as the function name, parameter list, and return type, and recording the function's address in memory. It then analyzes the calling relationships between functions and constructs a complete function call graph. The function call graph displays direct calling relationships between functions, as well as indirect calling paths and loop call structures.

[0097] Specifically, when the second processing thread is called in step 202 to parse the symbol table and address information, the parsing can be performed based on a preset address parsing tool. Figure 3 , Figure 3 A flowchart of a method for handling process abnormalities provided in an embodiment of the present disclosure includes:

[0098] Step 301: The second processing thread calls a preset function address resolution tool.

[0099] In some embodiments, the preset function address resolution tool may be a database or a system for function address resolution, such as GDB or addr2line. The second processing thread may call the function address resolution tool through a function pointer or interface, and pass the function to be resolved and related data into the function address resolution tool to perform function resolution. The embodiments of the present application do not limit the type or category of the function address resolution tool.

[0100] Step 302: Use the preset function address parsing tool to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

[0101] The preset function address resolution tool first reads the symbol table of the shared object files corresponding to all processes, and uses the symbol table to construct the mapping relationship of the functions in each process; then, the preset function address resolution tool is used to implement cross-process resolution of the address information in the memory. The address information in the memory contains key information such as the actual running address of the function and the calling relationship between functions.

[0102] In some embodiments, after obtaining the function's attribute information and function call hierarchy through a function address resolution tool, a detailed report on the abnormal thread can be generated. Specifically, it can include basic information of the abnormal thread, such as thread ID, status, etc., as well as all functions involved in the abnormal thread and their attribute information, to help developers quickly understand the context in which the exception occurred.

[0103] In some embodiments, before parsing is performed according to the first processing thread and the second processing thread, independent memory spaces of a preset size are allocated to the first processing thread and the second processing thread respectively.

[0104] To ensure data isolation between threads and optimize program performance, when creating the first and second processing threads, each thread is allocated independent memory space. Each thread only accesses the memory area allocated to it. The memory size can be determined based on the actual data processing volume and system computing power requirements. This embodiment of the application does not limit the size of the independent memory space.

[0105] Independent memory spaces ensure data isolation between threads. Modifications to memory data made by different threads during execution do not affect the data of other threads, avoiding I / O blocking (input / output blocking) during stack capture, reducing inter-thread interference and potential concurrency issues. Furthermore, a well-designed locking mechanism and synchronization strategy prevent deadlock during stack capture.

[0106] System monitoring is crucial. The quality of monitoring determines whether abnormalities can be detected and located quickly. Figure 4 , Figure 4 A flowchart of a method for handling process abnormalities provided in an embodiment of the present disclosure includes:

[0107] Step 401: Control and start a monitoring node, wherein the monitoring node is used to monitor heartbeat data packets sent to each thread in the target process.

[0108] Before executing this step, monitoring nodes are pre-deployed in the system, and real-time monitoring of the running status of each thread is achieved based on the data returned by the monitoring nodes. In some embodiments, thread monitoring can also be achieved through heartbeat mechanisms, performance counters, logging, and monitoring agents. Specifically, the embodiments of this application do not limit the monitoring method.

[0109] Step 402: monitor whether there is an abnormal thread that times out in responding to the heartbeat data packet.

[0110] After the monitoring node is started, it receives heartbeat packets from each thread of the target process. These packets contain thread status information, such as whether it is running normally and whether there are any anomalies. The monitoring node monitors these heartbeat packets in real time. If the heartbeat packet response of a thread times out, it indicates that the thread may have an anomaly. In this case, the monitoring node records the information of the abnormal thread for subsequent processing.

[0111] Step 403: If so, the identification information of the abnormal thread is stored in a preset storage queue.

[0112] When a monitoring node detects an abnormal thread, it stores the thread's identification information (e.g., thread ID, status, etc.) in a pre-set storage queue. In some embodiments, the storage queue can be a first-in, first-out queue structure that temporarily stores abnormal thread information. This ensures that the system can process abnormal threads one by one in a certain order during subsequent processing.

[0113] Figure 5 The following further shows a flowchart of a method for handling process abnormalities proposed in the present disclosure. Figure 5 The following steps may be included:

[0114] Step 501: When it is detected that the preset storage queue is in a non-empty state, the identification information of the abnormal thread is read from the preset storage queue.

[0115] To prevent the read operation from failing or returning a specific error value due to lack of data to read when reading data from the preset storage queue, before reading the data, it is first determined whether there is identification information of an abnormal thread that can be read in the preset storage queue.

[0116] Step 502: performing a stack capture operation on the abnormal thread corresponding to the identification information.

[0117] The stack capture operation generally involves obtaining the call stack frame information of the program, including function call order, parameter values, local variables, etc. In some embodiments, the stack capture operation can be performed asynchronously to avoid blocking other threads during execution and interfering with other parts of the system.

[0118] In some embodiments, before executing the stack capture operation on the abnormal thread, it is necessary to determine the current process state of the target process and determine whether the current process state is in the stack capture state, collection state, sampling state, or transfer state;

[0119] In some embodiments, if the current process is locked or waiting for certain resources, the stack grabbing operation may cause speculation or long suspension, and competing with other threads for shared resources during stack grabbing may cause data inconsistency or program crash.

[0120] The captured stack information is reliable only when the process is in a normal state. Before executing a stack capture operation, check the current process status, including whether an active stack capture is in progress, whether HP (heap profiling) is in progress, or whether an MDMP (minidump) has been written, to avoid affecting existing functions.

[0121] If the current state does not include a stack capture state, a collection and sampling state, or a transfer state, a stack capture operation is performed on the abnormal thread.

[0122] When it is determined that the state of the abnormal thread is normal, a stack capture operation may be performed on the abnormal thread to obtain thread stack information of the abnormal thread for subsequent positioning of the abnormal code.

[0123] Corresponding to the above-mentioned process anomaly handling method, the present invention also provides a process anomaly handling device. Since the device embodiment of the present invention corresponds to the above-mentioned method embodiment, details not disclosed in the device embodiment can be referred to the above-mentioned method embodiment and will not be repeated in this invention.

[0124] Figure 6 This is a schematic diagram of the structure of a device for handling process anomalies provided in an embodiment of the present disclosure. The device for handling process anomalies includes:

[0125] The execution unit 61 is configured to, after determining that an abnormal thread exists in the target process, execute a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread;

[0126] An address resolution unit 62 is configured to call a first processing thread to perform address resolution on the thread stack information to obtain address information of functions stored in a memory, wherein the thread stack information includes call records of all functions;

[0127] The process parsing unit 63 is configured to call the second processing thread to perform cross-process parsing on the address information of the function stored in the memory, and obtain attribute information of the function and a function call hierarchy relationship;

[0128] The positioning unit 64 is used to send the attribute information of the function and the function call hierarchy relationship to the server, so that the server can locate the abnormal code according to the attribute information of the function and the function call hierarchy relationship.

[0129] In summary, according to the device for processing process exceptions proposed in the present disclosure, the device includes, after determining that there is an abnormal thread in the target process, executing a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread; calling a first processing thread to perform address resolution on the thread stack information to obtain address information of the function stored in the memory, wherein the thread stack information contains call records of all functions; calling a second processing thread to perform cross-process resolution on the address information of the function stored in the memory to obtain attribute information of the function and a hierarchical relationship of function calls; sending the attribute information of the function and the hierarchical relationship of function calls to the server, so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls. The solution disclosed in the present disclosure reduces interference to other parts of the system and improves the stability and reliability of the system through a lightweight thread-level stack capture operation. It accurately captures the status of the abnormal thread without significantly affecting the system performance, thereby providing information for subsequent fault diagnosis and repair.

[0130] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the process parsing unit 63 also includes:

[0131] Reading module 631, used for reading the symbol table of the shared object files corresponding to all processes respectively;

[0132] The parsing module 632 is used to call the second processing thread to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

[0133] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the parsing module 632 is further used to:

[0134] The second processing thread calls a preset function address resolution tool;

[0135] The preset function address parsing tool is used to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

[0136] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the device also includes:

[0137] The allocating unit 65 allocates independent memory spaces of preset sizes to the first processing thread and the second processing thread respectively.

[0138] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7As shown, the device also includes:

[0139] The control unit 66 is configured to, after the execution unit 61 determines that an abnormal thread exists in the target process, execute a stack capture operation on the abnormal thread, and before obtaining thread stack information corresponding to the abnormal thread, control the startup of a monitoring node, wherein the monitoring node is configured to monitor heartbeat data packets sent to each thread in the target process.

[0140] A monitoring unit 67 is used to monitor whether there is an abnormal thread that times out in responding to the heartbeat data packet;

[0141] The storage unit 68 is configured to store identification information of the abnormal thread in a preset storage queue when there is an abnormal thread that times out in responding to the heartbeat data packet.

[0142] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the execution unit 61 includes:

[0143] The reading module 611 is configured to read the identification information of the abnormal thread from the preset storage queue when detecting that the preset storage queue is not empty;

[0144] The stack capture module 612 is configured to perform a stack capture operation on the abnormal thread corresponding to the identification information.

[0145] Furthermore, in a possible implementation of the embodiment of the present disclosure, as Figure 7 As shown, the device also includes:

[0146] The determining unit 69 is configured to determine the current process state of the target process and determine whether the current process state is in a stack capturing state, a collecting and sampling state, or a transferring state before the executing unit 61 executes the stack capturing operation on the abnormal thread.

[0147] The execution unit 61 is further configured to:

[0148] When the current state does not include a stack capture state, a collection and sampling state, or a transfer state, a stack capture operation is performed on the abnormal thread.

[0149] Since the device provided in the embodiment of the present disclosure corresponds to the methods provided in the above embodiments, the implementation of the method is also applicable to the device provided in this embodiment and will not be described in detail in this embodiment.

[0150] In the embodiments provided above, the methods and devices provided in the embodiments of the present application are introduced. In order to implement the various functions of the methods provided in the embodiments of the present application, the electronic device may include a hardware structure and a software module, and implement the aforementioned functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. One of the aforementioned functions may be executed in the form of a hardware structure, a software module, or a hardware structure plus a software module.

[0151] Figure 8 FIG2 is a block diagram of an electronic device 7000 for implementing the above-described process exception handling method according to an exemplary embodiment. For example, the electronic device 7000 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0152] Reference Figure 8 , the electronic device 7000 may include one or more of the following components: a processing component 7002 , a memory 7004 , a power component 7006 , a multimedia component 7008 , an audio component 7010 , an input / output (I / O) interface 7012 , a sensor component 7014 , and a communication component 7016 .

[0153] The processing component 7002 generally controls the overall operation of the electronic device 7000, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 7002 may include one or more processors 7020 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 7002 may include one or more modules to facilitate interaction between the processing component 7002 and other components. For example, the processing component 7002 may include a multimedia module to facilitate interaction between the multimedia component 7008 and the processing component 7002.

[0154] The memory 7004 is configured to store various types of data to support operations on the electronic device 7000. Examples of such data include instructions for any application or method operating on the electronic device 7000, contact data, phone book data, messages, pictures, videos, etc. The memory 7004 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0155] The power supply component 7006 provides power to the various components of the electronic device 7000. The power supply component 7006 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 7000.

[0156] The multimedia component 7008 includes a screen that provides an output interface between the electronic device 7000 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 7008 includes a front camera and / or a rear camera. When the electronic device 7000 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0157] The audio component 7010 is configured to output and / or input audio signals. For example, the audio component 7010 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 7000 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 7004 or transmitted via the communication component 7016. In some embodiments, the audio component 7010 also includes a speaker for outputting audio signals.

[0158] I / O interface 7012 provides an interface between processing component 7002 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0159] The sensor assembly 7014 includes one or more sensors for providing various aspects of status assessment for the electronic device 7000. For example, the sensor assembly 7014 can detect the open / closed state of the electronic device 7000, the relative positioning of components, such as the display and keypad of the electronic device 7000. The sensor assembly 7014 can also detect changes in the position of the electronic device 7000 or a component of the electronic device 7000, the presence or absence of user contact with the electronic device 7000, the orientation or acceleration / deceleration of the electronic device 7000, and temperature changes of the electronic device 7000. The sensor assembly 7014 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 7014 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 7014 can also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0160] The communication component 7016 is configured to facilitate wired or wireless communication between the electronic device 7000 and other devices. The electronic device 7000 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio) or a combination thereof. In an exemplary embodiment, the communication component 7016 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 7016 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0161] In an exemplary embodiment, the electronic device 7000 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described methods.

[0162] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 7004 including instructions. The instructions can be executed by the processor 7020 of the electronic device 7000 to complete the above method for handling process exceptions. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0163] The embodiments of the present disclosure further provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the method described in the above embodiments of the present disclosure.

[0164] For electronic devices that can be chips or chip systems, see Figure 9 Schematic diagram of the chip structure shown. Figure 9 The chip shown includes a processor 801 and an interface 802. There may be one or more processors 801 and there may be more than one interface 802.

[0165] Optionally, the chip further includes a memory 803, which is used to store necessary computer programs and data.

[0166] Those skilled in the art will also appreciate that the various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the functions for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present application.

[0167] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the numbers used in this manner are interchangeable where appropriate so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure as detailed in the appended claims.

[0168] Throughout this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" indicate that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0169] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0170] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection having one or more wires (control method), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing it in a suitable manner if necessary, and then storing it in a computer memory.

[0171] It should be understood that various parts of the embodiments of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0172] Those skilled in the art will understand that all or part of the steps of the method for implementing the above-mentioned embodiment can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0173] Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing module, each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in either hardware or software functional modules. If the integrated modules are implemented as software functional modules and sold or used as standalone products, they may also be stored in a computer-readable storage medium. The aforementioned storage medium may be a read-only memory, a magnetic disk, or an optical disk, etc.

[0174] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for handling process abnormalities, characterized in that: The method comprises: After determining that an abnormal thread exists in the target process, performing a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread; Calling a first processing thread to perform address resolution on the thread stack information to obtain address information of functions stored in a memory, wherein the thread stack information includes call records of all functions; Invoking a second processing thread to perform cross-process analysis on the address information of the function stored in the memory to obtain attribute information of the function and a function call hierarchy relationship; wherein the first processing thread and the second processing thread are independent of each other, and the second processing thread runs non-serially with the first processing thread based on the analysis result of the first processing thread; The attribute information of the function and the hierarchical relationship of function calls are sent to the server so that the server can locate the abnormal code according to the attribute information of the function and the hierarchical relationship of function calls.

2. The method according to claim 1, characterized in that The calling of the second processing thread to perform cross-process analysis on the address information of the function stored in the memory to obtain the attribute information of the function and the function call hierarchy relationship includes: Read the symbol table of the shared object files corresponding to all processes; The second processing thread is called to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and a function call hierarchy relationship.

3. The method according to claim 2, characterized in that The calling of the second processing thread to parse all symbol tables and address information of the function stored in the memory to obtain attribute information of the function and a function call hierarchy relationship includes: The second processing thread calls a preset function address resolution tool; The preset function address parsing tool is used to parse all symbol tables and address information of the functions stored in the memory to obtain attribute information of the functions and function call hierarchy relationships.

4. The method according to claim 1, wherein The method further comprises: Independent memory spaces of preset sizes are allocated to the first processing thread and the second processing thread respectively.

5. The method according to any one of claims 1 to 4, characterized in that After determining that an abnormal thread exists in the target process, before executing a stack capture operation on the abnormal thread and obtaining thread stack information corresponding to the abnormal thread, the method further includes: Control and start a monitoring node, which is used to monitor the heartbeat data packets sent to each thread in the target process: Monitor whether there is an abnormal thread that times out in response to the heartbeat data packet; If so, the identification information of the abnormal thread is stored in a preset storage queue.

6. The method according to claim 5, characterized in that The executing of the stack capture operation on the abnormal thread includes: When it is detected that the preset storage queue is in a non-empty state, reading identification information of the abnormal thread from the preset storage queue; A stack capture operation is performed on the abnormal thread corresponding to the identification information.

7. The method according to claim 1, characterized in that Before executing the stack capture operation on the abnormal thread, the method further includes: Determine the current process state of the target process, and determine whether the current process state is in a stack capture state, a sampling collection state, or a transfer state; The executing of the stack capture operation on the abnormal thread includes: If the current state does not include a stack capture state, a collection and sampling state, or a transfer state, a stack capture operation is performed on the abnormal thread.

8. A device for processing process abnormalities, characterized in that: The device comprises: An execution unit, configured to, after determining that an abnormal thread exists in a target process, execute a stack capture operation on the abnormal thread to obtain thread stack information corresponding to the abnormal thread; An address resolution unit, configured to call a first processing thread to perform address resolution on the thread stack information to obtain address information of functions stored in a memory, wherein the thread stack information includes call records of all functions; a process parsing unit, configured to call a second processing thread to perform cross-process parsing on the address information of the function stored in the memory, and obtain attribute information of the function and a function call hierarchy relationship; wherein the first processing thread and the second processing thread are independent of each other, and the second processing thread runs non-serially with the first processing thread based on the parsing result of the first processing thread; The positioning unit is used to send the attribute information of the function and the function call hierarchy relationship to the server, so that the server can locate the abnormal code according to the attribute information of the function and the function call hierarchy relationship.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.

11. A chip, characterized in that: The electronic device comprises one or more interfaces and one or more processors; the interface is used to receive a signal from a memory of the electronic device and send the signal to the processor, the signal including a computer instruction stored in the memory, and when the processor executes the computer instruction, the electronic device executes the method according to any one of claims 1 to 7.

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