PCIe system debugging device and method

Abstract

The invention provides a PCIe system debugging device and method. A PCIe system comprises PCIe equipment, a central processing unit and a control service component. The debugging device comprises a plurality of data acquisition points and an operation terminal. The plurality of data acquisition points are respectively arranged at different data stream nodes on a data transmission path between the PCIe equipment and the central processing unit, and each data acquisition point is used for acquiring state information of a data stream at the position of the data acquisition point; the operation terminal is electrically connected with the plurality of data acquisition points and the PCIe equipment, the operation terminal comprises a configuration module and a storage module, the configuration module is used for customizing and configuring an excitation data packet provided for the PCIe equipment, and the storage module is used for acquiring and storing state information fed back by the data acquisition points. According to the PCIe system debugging device provided by the invention, the excitation data packet can be sent in a user-defined manner to simulate various transmission scenes, so that the accuracy, the effectiveness and the flexibility of the debugging process are effectively enhanced, and the active testing capability which a traditional analyzer does not have is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of computer-related system debugging, and in particular to a PCIe system debugging device and method. Background Art

[0002] As a high-speed serial computer expansion bus standard, PCIe (Peripheral Component Interconnect Express) protocol is widely used in modern computer systems to meet the needs of high-bandwidth data transmission. However, with the continuous improvement of computing device performance and the increasing complexity of application scenarios, the requirements for data transmission stability and performance are also increasing. In practical applications, factors such as transmission quality, transmission distance, and transmission environment will affect PCIe data transmission. This impact often leads to transient inconsistencies in the data transmission process, which in turn increases the difficulty of debugging and maintenance.

[0003] Existing debugging tools, such as PCIe protocol analyzers, mainly capture and analyze data packets in the PCIe channel. Although these tools can help engineers understand certain aspects of data transmission, they have several functional limitations. First, these analyzers are usually unable to accurately generate PCIe packet stimuli for testing. This means that engineers are limited by the tool's functionality when they need to simulate specific data flow situations to test system behavior. In addition, traditional debugging methods are relatively simple and passive, mainly relying on the analysis of existing data, lacking flexibility, making it difficult to perform fine debugging and real-time control of specific nodes in the transmission path. Summary of the invention

[0004] The object of the present invention is to provide a PCIe system debugging device and method which can accurately generate PCIe stimulus data packets and has flexible debugging means.

[0005] In order to achieve the above object, the present invention provides a PCIe system debugging device, wherein the PCIe system includes a PCIe device and a central processing unit, and a control service component arranged between the PCIe device and the central processing unit, wherein the control service component is used to control the communication between the PCIe device and the central processing unit;

[0006] The debugging device includes several data collection points and an operation terminal;

[0007] The data collection points are respectively arranged at different data flow nodes on the data transmission path between the PCIe device and the central processor.

[0008] Each of the data collection points is used to obtain status information of the data stream at its location;

[0009] The operation terminal is electrically connected to the data collection points and the PCIe device. The operation terminal includes a configuration module and a storage module. The configuration module is used to customize the stimulus data packet provided to the PCIe device, and the storage module is used to obtain and store the status information fed back by the data collection point.

[0010] Preferably, the configuration module is also used to configure the data collection point to be currently activated, and the data collection point to be currently activated is a part or all of all the set data collection points.

[0011] Preferably, the control service component includes a PCIe controller, a memory management unit, a cache coherence controller and an interrupt controller;

[0012] The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache consistency controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to the cache consistency controller and the central processing unit respectively.

[0013] Preferably, the data transmission path between the PCIe device and the central processor includes an uplink data channel and a downlink data channel, and the data collection point is provided in both the uplink data channel and the downlink data channel;

[0014] The uplink data transmission channel is a data channel through which data flows from the PCIe device to the central processing unit, and the downlink data transmission channel is a data channel through which data flows from the central processing unit to the PCIe device.

[0015] Preferably, the data collection points include a first collection point, a second collection point, a third collection point, a fourth collection point, a fifth collection point and a sixth collection point located in the uplink data channel, and a seventh collection point, an eighth collection point and a ninth collection point located in the downlink data channel;

[0016] The first collection point and the ninth collection point are located between the PCIe device and the PCIe controller;

[0017] The second collection point is located between the PCIe controller and the memory management unit;

[0018] The third collection point is located between the memory management unit and the cache coherence controller;

[0019] The fourth collection point is located between the cache coherence controller and the interrupt controller;

[0020] The fifth acquisition point is located between the interrupt controller and the central processing unit;

[0021] The sixth collection point and the seventh collection point are located between the cache coherence controller and the central processing unit;

[0022] The eighth collection point is located between the cache coherence controller and the PCIe controller.

[0023] The present invention also provides a PCIe system debugging method, wherein the PCIe system includes a PCIe device and a central processor, and a control service component arranged between the PCIe device and the central processor, wherein the control service component is used to control the communication between the PCIe device and the central processor; the debugging method includes:

[0024] Customizing, through an operating terminal, a stimulus data packet that is compatible with the current PCIe device, and sending the stimulus data packet to the PCIe device;

[0025] Collecting and storing state information of data flows at different data flow nodes on a data transmission path between the PCIe device and the central processor to obtain test data;

[0026] When the test data shows that there is an error in the current data transmission between the PCIe device and the central processing unit, the configuration of the PCIe device is adjusted according to the test data, and the test data is obtained again until the current data transmission between the PCIe device and the central processing unit meets expectations.

[0027] Preferably, data collection points are respectively set at different data flow nodes on the data transmission path between the PCIe device and the central processing unit, and the status information at the corresponding position is obtained through the data collection points; the data collection point to be currently started is also configured through the operation terminal, and the data collection point to be currently started is a part or all of all the set data collection points.

[0028] Preferably, the control service component includes a PCIe controller, a memory management unit, a cache coherence controller and an interrupt controller;

[0029] The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache consistency controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to the cache consistency controller and the central processing unit respectively.

[0030] Preferably, the data transmission path between the PCIe device and the central processor includes an uplink data channel and a downlink data channel, and the data collection point is provided in both the uplink data channel and the downlink data channel;

[0031] The uplink data transmission channel is a data channel through which data flows from the PCIe device to the central processing unit, and the downlink data transmission channel is a data channel through which data flows from the central processing unit to the PCIe device.

[0032] Preferably, the data collection points include a first collection point, a second collection point, a third collection point, a fourth collection point, a fifth collection point and a sixth collection point located in the uplink data channel, and a seventh collection point, an eighth collection point and a ninth collection point located in the downlink data channel;

[0033] The first collection point and the ninth collection point are located between the PCIe device and the PCIe controller;

[0034] The second collection point is located between the PCIe controller and the memory management unit;

[0035] The third collection point is located between the memory management unit and the cache coherence controller;

[0036] The fourth collection point is located between the cache coherence controller and the interrupt controller;

[0037] The fifth acquisition point is located between the interrupt controller and the central processing unit;

[0038] The sixth collection point and the seventh collection point are located between the cache coherence controller and the central processing unit;

[0039] The eighth collection point is located between the cache coherence controller and the PCIe controller.

[0040] Compared with the prior art, the PCIe system debugging device provided by the present invention realizes fine control and monitoring of the data transmission process through several data collection points between the PCIe device and the central processor. The configuration module in the operation terminal allows engineers to customize the configuration of stimulus data packets, and can customize the sending of stimulus data packets of different numbers, types and contents to simulate various transmission scenarios, which effectively enhances the accuracy, effectiveness and flexibility of the debugging process, and provides active testing capabilities that traditional analyzers do not have; secondly, the configuration of multi-point data collection can obtain the status information of each data flow node in real time, so that engineers can identify transmission bottlenecks and problem nodes, and quickly diagnose potential connection inconsistencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a principle structure diagram of the PCIe system debugging device in an embodiment of the present invention.

[0042] Figure 2 This is a distribution diagram of data collection points in a PCIe system according to an embodiment of the present invention.

[0043] Figure 3 It is an execution flow chart of the PCIe system debugging device in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0045] This embodiment discloses a PCIe system debugging device, which is used to debug a PCIe system so that data transmission therein meets expectations.

[0046] The PCIe system includes a PCIe device and a central processing unit (CPU), and a control service component arranged between the PCIe device and the CPU, wherein the control service component is used to control the communication between the PCIe device and the CPU.

[0047] The PCIe (Peripheral Component Interconnect Express) device in this embodiment refers to a hardware component connected to a computer motherboard. PCIe is a high-speed serial computer expansion bus standard that can be used to connect various external devices, such as graphics cards, solid-state drives (SSDs), network interface cards, etc. These devices communicate with the CPU through the PCIe bus to achieve high-speed data transmission.

[0048] Then, the goal of the debugging device in this embodiment is to optimize the data transmission related to the PCIe protocol in the PCIe device, especially the data transmission stability, performance and error capture and analysis.

[0049] like Figure 1 and Figure 2 , the debugging device includes several data collection points J and an operation terminal.

[0050] Several data collection points J are respectively set at different data flow nodes on the data transmission path between the PCIe device and the CPU, and each data collection point J is used to obtain the status information of the data flow at its location. Specifically, the status information includes error information output by the function module with data analysis function in the control service component.

[0051] The operation terminal is electrically connected to several data collection points J and PCIe devices. The operation terminal includes a configuration module and a storage module. The configuration module is used to customize the stimulus data packet provided to the PCIe device, and the storage module is used to obtain and store the status information fed back by the data collection point J.

[0052] It should be noted that a number of data collection points J can be constructed by using a data collection card or a data flow analyzer.

[0053] For example, if you need to debug the data transmission of a PCIe device when it sends an MSI-X (Extended Message Signaled Interrupt) packet to the CPU. The goal of debugging is to ensure that the packet can be successfully sent and can correctly trigger the CPU response. Figure 3 , then the debugging workflow is as follows:

[0054] S10: Customize and configure the stimulus data packet that is compatible with the current PCIe device through the operation terminal.

[0055] The data packet includes the following information:

[0056] Packet type: MSI-X;

[0057] Data packet content: including Request ID, Event ID and other information;

[0058] Number of packets: set to 1;

[0059] PCIe function configuration: Enable the MSI-X function and configure the message address and message data.

[0060] S11: Send the stimulus data packet to the PCIe device.

[0061] S12: Collect and store data flow status information at different data flow nodes on the data transmission path between the PCIe device and the CPU to obtain test data. The test data can be stored in the form of a log on the operation terminal.

[0062] S13: Determine whether there is an error in the data transmission between the current PCIe device and the CPU based on the test data. If yes, proceed to S14. If not, it means that the data transmission between the current PCIe device and the CPU is as expected, then proceed to S15.

[0063] S14: Adjust the configuration of the PCIe device according to the test data, and return to step S10.

[0064] S15: End the current debugging.

[0065] On the other hand, the configuration module is also used to configure the data collection point J to be currently started, and the data collection point J to be currently started is a part or all of all the set data collection points J. In this embodiment, the number and objects of the data collection points J to be currently started can be configured as needed to achieve rational use of resources.

[0066] On the other hand, Figure 2 ,The control service components include PCIe controller, memory management unit, cache consistency controller and interrupt controller.

[0067] The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache consistency controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to the cache consistency controller and the CPU respectively.

[0068] PCIe controller: responsible for managing data transmission on the PCIe bus, including sending, receiving, routing and error handling of data packets.

[0069] Memory Management Unit: Responsible for managing the access of PCIe devices to system memory. It can map the physical address of PCIe devices to the virtual address of system memory to enable devices to access memory.

[0070] Cache consistency controller: responsible for ensuring the consistency of cache data shared between different devices. It can prevent conflicts when different devices modify the same data and ensure data consistency.

[0071] Interrupt controller: responsible for managing interrupt signals from PCIe devices. When a PCIe device needs to send a signal to the CPU, it sends an interrupt request through the interrupt controller, thereby notifying the CPU to handle the corresponding event.

[0072] In this regard, the data transmission path between the PCIe device and the CPU includes an uplink data channel and a downlink data channel, and data collection points J are set in both the uplink data channel and the downlink data channel to achieve comprehensive monitoring of the data flow between the PCIe device and the CPU.

[0073] The uplink data transmission channel is a data channel for data to flow from the PCIe device to the CPU, and the downlink data transmission channel is a data channel for data to flow from the CPU to the PCIe device.

[0074] It should also be noted that data collection point J uses the error monitoring functions inside modules such as the PCIe controller, memory management unit, and interrupt controller to form status information, such as the RAS function of the PCIe controller, the error event recording queue of the memory management unit, the PMU function, and the pending and active states of the interrupt controller. The pending state indicates that the interrupt event has occurred but has not been processed; the active state indicates that the interrupt event is being processed.

[0075] Specifically, when data flows to the PCIe controller, the RAS function in the PCIe controller is enabled. The RAS function is an error detection and repair mechanism built into the PCIe bus standard. It can detect hardware failures such as memory errors, data transmission errors, etc., and perform corresponding processing.

[0076] When a PCIe-related error occurs in the PCIe system, such as a data transmission error, link failure, etc., the RAS function will record the error information (such as error type, error location, etc.), which is the status information collected by the data collection point J. By analyzing the error information, the debugger can quickly locate the problem.

[0077] When data flows to the memory management unit, the PMU function is used to monitor performance data, and the RAS functions of the memory management unit, such as the error queue, are enabled to output specific error information.

[0078] The PMU is a functional component used to track and count low-level hardware events in the PCIe system, such as the amount of data transferred, the number of instruction executions, etc.

[0079] When the PCIe system encounters performance problems, such as slow data transmission speed and low system operation efficiency, the debugger can analyze the operation of the PCIe system through the status information output by the PMU function, such as observing the data transmission rate, the frequency of instruction execution, etc., to find out the performance bottleneck and locate the problem.

[0080] When data flows to the interrupt controller, when interrupt-related problems occur in the PCIe system, such as untimely interrupt processing and delayed interrupt response, debuggers can understand the occurrence time and processing status of the interrupt event by observing the pending and active states generated by the interrupt controller, thereby analyzing the cause of the problem.

[0081] On the other hand, the data collection points J include a first collection point J1, a second collection point J2, a third collection point J3, a fourth collection point J4, a fifth collection point J5 and a sixth collection point J6 located in the uplink data channel, and a seventh collection point J7, an eighth collection point J8 and a ninth collection point J9 located in the downlink data channel.

[0082] The first collection point J1 and the ninth collection point J9 are located between the PCIe device and the PCIe controller;

[0083] The second acquisition point J2 is located between the PCIe controller and the memory management unit;

[0084] The third collection point J3 is located between the memory management unit and the cache coherence controller;

[0085] The fourth collection point J4 is located between the cache coherence controller and the interrupt controller;

[0086] The fifth acquisition point J5 is located between the interrupt controller and the central processing unit;

[0087] The sixth collection point J6 and the seventh collection point J7 are located between the cache coherence controller and the central processing unit; the eighth collection point J8 is located between the cache coherence controller and the PCIe controller.

[0088] Table 1

[0089]

[0090]

[0091] During the debugging process, the corresponding data collection point J can be configured and enabled according to the function of the current PCIe device. For example, when debugging the data transmission when the PCIe device sends an MSI-X (Extended Message Signal Interrupt) data packet to the CPU, it is only necessary to enable the first collection point J1, the second collection point J2, the third collection point J3, the fourth collection point J4 and the fifth collection point J5.

[0092] In summary, the PCIe system debugging device disclosed in the above embodiment of the present invention realizes fine control and monitoring of the data transmission process through a number of data collection points J between the PCIe device and the CPU. The configuration module in the operation terminal allows engineers to customize the configuration of stimulus data packets, and can customize the sending of stimulus data packets of different numbers, types and contents to simulate various transmission scenarios, which effectively enhances the accuracy, effectiveness and flexibility of the debugging process, and provides active testing capabilities that traditional analyzers do not have; secondly, the configuration of multi-point data collection can obtain the status information of each data flow node in real time, so that engineers can identify transmission bottlenecks and problem nodes, and quickly diagnose potential connection inconsistencies.

[0093] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A PCIe system debugging device, characterized in that: The PCIe system includes a PCIe device and a central processor, and a control service component arranged between the PCIe device and the central processor, wherein the control service component is used to control the communication between the PCIe device and the central processor; The debugging device includes several data collection points and an operation terminal; The plurality of data collection points are respectively arranged at different data flow nodes on the data transmission path between the PCIe device and the central processor, and each of the data collection points is used to obtain the state information of the data flow at its location; The operation terminal is electrically connected to the plurality of data collection points and the PCIe device, and includes a configuration module and a storage module, wherein the configuration module is used to customize the configuration of the stimulus data packet provided to the PCIe device, and the storage module is used to obtain and store the status information fed back by the data collection point.

2. The PCIe system debugging device according to claim 1, characterized in that: The configuration module is also used to configure the data collection point to be currently started, and the data collection point to be currently started is a part or all of all the set data collection points.

3. The PCIe system debugging device according to claim 1, characterized in that: The control service component includes a PCIe controller, a memory management unit, a cache coherence controller and an interrupt controller; The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache consistency controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to the cache consistency controller and the central processing unit respectively.

4. The PCIe system debugging device according to claim 3, characterized in that: The data transmission path between the PCIe device and the central processor includes an uplink data channel and a downlink data channel, and the data collection point is arranged in both the uplink data channel and the downlink data channel; The uplink data transmission channel is a data channel for data to flow from the PCIe device to the central processing unit, and the downlink data transmission channel is a data channel for data to flow from the central processing unit to the PCIe device.

5. The PCIe system debugging device according to claim 4, characterized in that: The data collection points include a first collection point, a second collection point, a third collection point, a fourth collection point, a fifth collection point and a sixth collection point located in the uplink data channel, and a seventh collection point, an eighth collection point and a ninth collection point located in the downlink data channel; The first collection point and the ninth collection point are located between the PCIe device and the PCIe controller; The second collection point is located between the PCIe controller and the memory management unit; The third collection point is located between the memory management unit and the cache coherence controller; The fourth collection point is located between the cache coherence controller and the interrupt controller; The fifth acquisition point is located between the interrupt controller and the central processing unit; The sixth collection point and the seventh collection point are located between the cache coherence controller and the central processing unit; The eighth collection point is located between the cache coherence controller and the PCIe controller.

6. A PCIe system debugging method, characterized in that: The PCIe system includes a PCIe device and a central processor, and a control service component arranged between the PCIe device and the central processor, wherein the control service component is used to control the communication between the PCIe device and the central processor; The debugging method comprises: Customizing, through an operating terminal, a stimulus data packet that is compatible with the current PCIe device, and sending the stimulus data packet to the PCIe device; Collecting and storing state information of data flows at different data flow nodes on a data transmission path between the PCIe device and the central processor to obtain test data; When the test data shows that there is an error in the current data transmission between the PCIe device and the central processing unit, the configuration of the PCIe device is adjusted according to the test data, and the test data is obtained again until the current data transmission between the PCIe device and the central processing unit meets expectations.

7. The PCIe system debugging method according to claim 6, characterized in that: Data collection points are respectively set at different data flow nodes on the data transmission path between the PCIe device and the central processing unit, and the status information at the corresponding position is obtained through the data collection points; the data collection point to be currently started is also configured through the operation terminal, and the data collection point to be currently started is a part or all of all the set data collection points.

8. The PCIe system debugging method according to claim 7, characterized in that: The control service component includes a PCIe controller, a memory management unit, a cache coherence controller and an interrupt controller; The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache consistency controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to the cache consistency controller and the central processing unit respectively.

9. The PCIe system debugging method according to claim 8, characterized in that: The data transmission path between the PCIe device and the central processor includes an uplink data channel and a downlink data channel, and the data collection point is arranged in both the uplink data channel and the downlink data channel; The uplink data transmission channel is a data channel for data to flow from the PCIe device to the central processing unit, and the downlink data transmission channel is a data channel for data to flow from the central processing unit to the PCIe device.

10. The PCIe system debugging method according to claim 9, characterized in that: The data collection points include a first collection point, a second collection point, a third collection point, a fourth collection point, a fifth collection point and a sixth collection point located in the uplink data channel, and a seventh collection point, an eighth collection point and a ninth collection point located in the downlink data channel; The first collection point and the ninth collection point are located between the PCIe device and the PCIe controller; The second collection point is located between the PCIe controller and the memory management unit; The third collection point is located between the memory management unit and the cache coherence controller; The fourth collection point is located between the cache coherence controller and the interrupt controller; The fifth acquisition point is located between the interrupt controller and the central processing unit; The sixth collection point and the seventh collection point are located between the cache coherence controller and the central processing unit; The eighth collection point is located between the cache coherence controller and the PCIe controller.

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