Memory system

Abstract

The invention relates to the technical field of computers, in particular to a memory system which is characterized in that a memory controller and a physical layer are interconnected through a memory physical interface; the memory controller sends a controller handshake request to a physical layer through a message interface every a first preset number of cycles, and the memory controller realizes data read-write operation through an interface for realizing data read-write; the physical layer obtains delay chain calibration data once every a second preset number of cycles, when a controller handshake request is received, whether delay chain change caused by current temperature voltage drift exceeds a preset delay chain change threshold value or not is judged, and if yes, a confirmation signal is returned to the memory controller through the message interface; and after receiving the confirmation signal, the memory controller controls the starting physical layer to calibrate the delay chain based on the current delay chain calibration data, and in the process of calibrating the delay chain, the operation of an interface for realizing data reading and writing is paused. According to the invention, the memory access efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory system. Background Art

[0002] Memory access efficiency is a key indicator that affects memory system performance. Common methods often use scheduling strategies to reduce the extra overhead between commands, such as the overhead of closing the current row and opening a new row caused by command line breaks, and use an interleave mechanism to increase the chance of overlapping operations, thereby shortening the command interval as much as possible. However, during the operation of the memory system, changes in temperature and voltage will cause certain drifts. The memory system must calibrate these drifts in a timely manner, and these calibration operations will inevitably affect normal read and write accesses, which often become an impact on memory access efficiency that cannot be ignored.

[0003] In the traditional method, the memory controller is generally used to send calibration update requests at a fixed period. However, if the request is sent too frequently, the drift caused by temperature and voltage changes is still within the safe range and there is no need to update. Although the frequent update requests sent by the memory controller will avoid read-write conflicts as much as possible, it will inevitably affect the normal read-write bandwidth. If the memory controller does not send update requests to save bandwidth, then when the drift caused by temperature and voltage exceeds the safe range, it will cause the physical layer (PHY) connecting the memory controller and the storage unit to initiate a forced update request. This forced update must be responded to as quickly as possible and takes longer, which will have a greater impact on access efficiency. It can be seen that how to improve the access efficiency of memory while reducing the impact on the normal read-write bandwidth and ensuring timely updates when necessary has become a technical problem that needs to be solved. Summary of the invention

[0004] The present invention aims to provide a memory system which improves the access efficiency of the memory while reducing the impact on the normal read and write bandwidth and ensuring timely updating when necessary.

[0005] According to a first aspect of the present invention, there is provided a memory system, comprising a memory controller, a physical layer and a storage unit, wherein the memory controller is connected to the storage unit through the physical layer, and the memory controller performs a read and write data operation on the storage unit through the physical layer;

[0006] The memory controller and the physical layer are interconnected via a memory physical interface, wherein the memory physical interface includes a message interface and an interface for implementing reading and writing data;

[0007] The memory controller is used to send a controller handshake request to the physical layer through the message interface at intervals of a first preset number of cycles, the memory controller implements data reading and writing operations through an interface for implementing data reading and writing, and the message interface and the interface for implementing data reading and writing are independent of each other;

[0008] The physical layer acquires delay chain calibration data once every second preset number of cycles, and when receiving a controller handshake request, determines whether a delay chain variation caused by a current temperature voltage drift exceeds a preset delay chain variation threshold, and if so, returns a confirmation signal to the memory controller through a message interface;

[0009] The memory controller is also used to control the physical layer to start calibrating the delay chain based on the current delay chain calibration data after receiving the confirmation signal, and suspend the operation of the interface for implementing the reading and writing of data during the delay chain calibration process.

[0010] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the memory system provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0011] The present invention sends a handshake signal between a memory controller and a physical layer through a message interface, and triggers the update of a delay chain only when the temperature voltage drift exceeds a preset delay chain change threshold. The periodic handshake does not affect data reading and writing, and does not occupy normal reading and writing bandwidth. The present invention reduces the impact on normal reading and writing bandwidth and ensures timely updating when necessary, thereby improving the access efficiency of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of the memory system structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0015] According to a first aspect of the present invention, there is provided a memory system, such as Figure 1 As shown, it includes a memory controller (MC), a physical layer (PHY) and a storage unit. The memory controller is connected to the storage unit through the physical layer, and the memory controller performs read and write data operations on the storage unit through the physical layer. It should be noted that the memory controller receives data read and write instructions from the central processing unit (CPU), generates read and write control instructions based on the data read and write instructions, and performs data read and write operations in the storage unit through the physical layer. The storage unit is a dynamic random access memory (SRAM) or a double data rate synchronous dynamic random access memory (DDR), etc.

[0016] The memory controller and the physical layer are interconnected through a memory physical interface (DDR Physical Interface, referred to as DFI), and the memory physical interface includes a message interface and an interface for reading and writing data; the interface for reading and writing data includes a command interface (Commond Interface), a data interface (Data Interface), a clock interface (Clock Interface) and a response interface (Response Interface), etc. The memory physical interface also includes an update interface (Update Interface).

[0017] The memory controller is used to send a controller handshake request to the physical layer through the message interface every first preset number of cycles. The memory controller implements data reading and writing operations through an interface for implementing data reading and writing. The message interface and the interface for implementing data reading and writing are independent of each other. It should be noted that the memory controller sending a controller handshake request to the physical layer through the message interface will not affect normal data reading and writing operations. And the handshake requests are all actively initiated by the memory controller. Specifically, a periodic counter and a handshake request generator can be set to implement sending a controller handshake request to the physical layer through the message interface every cycle.

[0018] The physical layer obtains the delay chain calibration data once every second preset number of cycles. When receiving a handshake request from the memory controller, it determines whether the delay chain change caused by the current temperature voltage drift exceeds the preset delay chain change threshold. If it exceeds, a confirmation signal (ACK) is returned to the memory controller through the message interface. It should be noted that the first preset number of cycles and the second preset number of cycles can be equal or unequal. As an embodiment, the first preset number of cycles and the second preset number of cycles are both one cycle. The delay chain is a digital delay chain, which can adjust the delay of the data or command signal line. The delay chain is located in the physical layer, and the delay chain is instantiated on the data path and command path of the physical layer.

[0019] The memory controller is also used to control the physical layer to start calibrating the delay chain based on the current delay chain calibration data after receiving the confirmation signal, and suspend the operation of the interface for implementing the read and write data during the delay chain calibration process. It should be noted that if the ACK is not received within the Ack time required by the DFI protocol, it is considered that no update is required, and the system can continue to perform normal read and write operations. If the ACK is received within the ACK time required by the DFI protocol, the memory controller can start the delay chain update operation preparation, and after sending the allowed continuous page-hit commands, send an update request to the physical layer to enable the physical layer to perform a delay chain update operation.

[0020] It should be noted that in the prior art, the memory controller update interface periodically sends update requests to the physical layer and performs update operations. When the update operation is performed, the command interface (Commond Interface), data interface (Data Interface), clock interface (Clock Interface) and response interface (Response Interface) and other interfaces will be occupied, thereby affecting normal read and write operations. If the memory controller does not actively send updates, and only monitors the temperature and voltage drift through the physical layer, the physical layer needs to passively force the update to be initiated, and it is usually initiated after the temperature and voltage drift has reached the maximum value of the delay chain change Max. At this time, the delay chain calibration data currently updated by the physical layer will no longer be accurate. On the one hand, it takes a lot of time for the physical layer to passively initiate the update. On the other hand, the physical layer needs to re-acquire accurate delay chain calibration data, which also takes a lot of time. During this period, read and write operations cannot be performed normally, thereby affecting memory access efficiency.

[0021] However, the present application establishes a periodic handshake with the physical layer through the message interface, which does not affect the normal read and write operations. The delay chain change threshold is R, R = Max-a, where Max is the maximum value of the delay chain change. When the temperature voltage drift exceeds Max, the physical layer will make errors in sampling the data. a is the delay chain change buffer value. Setting a can ensure the safety of the system, so that under normal circumstances, there will be no large-scale temperature voltage drift in the second preset number of cycles. And in the case where the delay chain change caused by the current temperature voltage drift exceeds the preset delay chain change threshold, the memory controller actively initiates the update operation by returning a confirmation signal through the message interface. At this time, the current delay chain calibration data of the physical layer can be directly used.

[0022] As an embodiment, the message interface includes a dfi_ctrlmsg_data data segment and a dfi_ctrlmsg_ack data segment; wherein the dfi_ctrlmsg_data data segment is used to implement the memory controller to send message data to the physical layer, the dfi_ctrlmsg_data data segment includes a reserved item, a reserved item is selected and set to send a handshake request code, the memory controller sends a handshake request code to the physical layer through the reserved item selected in the dfi_ctrlmsg_data data segment, and implements the memory controller to send a handshake request to the physical layer. The dfi_ctrlmsg_ack data segment is used to implement the physical layer to send a confirmation signal to the memory controller. The message interface also includes a dfi_ctrlmsg data segment and a dfi_ctrlmsg_req data segment; wherein the dfi_ctrlmsg data segment is used to implement the memory controller to send a message instruction to the physical layer; the dfi_ctrlmsg_req data segment is used to implement the memory controller to send a request to the physical layer.

[0023] It should be noted that the embodiment of the present invention can directly initiate an update operation by the memory controller based on the confirmation signal received by the memory controller, or can use the update interface and the message interface together to realize the memory controller actively initiating the update operation. As an embodiment, the memory physical interface also includes an update interface, and the system also includes a selection logic unit (MCU). One end of the selection logic unit is connected to the memory controller, and the other end is connected to the message interface and the update interface. The message interface and the update interface are connected to the physical layer. In the initial state, the selection logic selects the message interface. When the memory controller receives the confirmation signal returned by the physical layer, the selection logic selects the update interface. The memory controller starts the physical layer through the update interface to calibrate the delay chain based on the current delay chain calibration data.

[0024] It should be noted that, under normal circumstances, data and commands should be aligned, but as the system runs, temperature and voltage changes will occur, and these changes will affect the movement of carriers at the microscopic level, thereby changing the characteristics of the device (such as switching speed, etc.). Before the delay chain variation maximum value MAX is exceeded, it will not affect the system sampling data, but after the delay chain variation maximum value MAX is exceeded, it will affect the system sampling data. Therefore, it is necessary to calibrate the sampling data in time before the delay chain variation caused by temperature and voltage drift reaches the maximum value MAX. The physical layer periodically obtains the delay chain calibration data so as to quickly and accurately calibrate the sampling data before the delay chain variation caused by temperature and voltage drift reaches the maximum value MAX, so that the data and commands are realigned. As an embodiment, the delay chain calibration data includes data window calibration data and command window calibration data. The delay chain calibration data is stored in a preset storage area. The physical layer obtains the delay chain calibration data once every second preset number of cycles, and overwrites and stores it in the preset storage area.

[0025] The system described in the embodiment of the present invention sends a handshake signal between the memory controller and the physical layer through a message interface, and triggers the update of the delay chain only when the temperature voltage drift exceeds the preset delay chain change threshold. The periodic handshake will not affect data reading and writing, and will not occupy the normal reading and writing bandwidth. The present invention reduces the impact on the normal reading and writing bandwidth and ensures timely updates when necessary, thereby improving the access efficiency of the memory.

[0026] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A memory system, characterized in that: It includes a memory controller, a physical layer and a storage unit, wherein the memory controller is connected to the storage unit through the physical layer, and the memory controller performs read and write data operations on the storage unit through the physical layer; The memory controller and the physical layer are interconnected via a memory physical interface, wherein the memory physical interface includes a message interface and an interface for realizing reading and writing data; The memory controller is used to send a controller handshake request to the physical layer through the message interface at intervals of a first preset number of cycles, the memory controller implements data reading and writing operations through an interface for implementing data reading and writing, and the message interface and the interface for implementing data reading and writing are independent of each other; The physical layer acquires delay chain calibration data once every second preset number of cycles, and when receiving a controller handshake request, determines whether a delay chain variation caused by a current temperature voltage drift exceeds a preset delay chain variation threshold, and if so, returns a confirmation signal to the memory controller through a message interface; The memory controller is also used to control the physical layer to start calibrating the delay chain based on the current delay chain calibration data after receiving the confirmation signal, and suspend the operation of the interface for implementing the reading and writing of data during the delay chain calibration process.

2. The system according to claim 1, characterized in that The message interface includes a dfi_ctrlmsg_data data segment and a dfi_ctrlmsg_ack data segment; The dfi_ctrlmsg_data data segment is used to implement the sending of message data by the memory controller to the physical layer, the dfi_ctrlmsg_data data segment includes a reserved item, a reserved item is selected and set to be used for sending a handshake request code, and the memory controller sends the handshake request code to the physical layer through the reserved item selected in the dfi_ctrlmsg_data data segment; The dfi_ctrlmsg_ack data segment is used to enable the physical layer to send a confirmation signal to the memory controller.

3. The system according to claim 1, characterized in that The memory physical interface also includes an update interface, and the system also includes a selection logic unit, one end of the selection logic unit is connected to the memory controller, and the other end is connected to the message interface and the update interface, and the message interface and the update interface are connected to the physical layer; In the initial state, the selection logic selects the message interface. When the memory controller receives a confirmation signal returned by the physical layer, the selection logic selects the update interface. The memory controller starts the physical layer through the update interface to calibrate the delay chain based on the current delay chain calibration data.

4. The system according to claim 1, characterized in that The delay chain variation threshold is R, R=Max-a, wherein Max is the maximum value of the delay chain variation. When the temperature voltage drift Max is exceeded, the physical layer will make errors in sampling the data, and a is the delay chain variation buffer value.

5. The system according to claim 1, characterized in that The delay chain calibration data includes data window calibration data and command window calibration data. The delay chain calibration data is stored in a preset storage area. The physical layer acquires the delay chain calibration data once every second preset number of cycles, and overwrites and stores the data in a preset storage area.

6. The system according to claim 1, characterized in that The storage unit is a dynamic random access memory.

7. The system according to claim 1, characterized in that The storage unit is a double rate synchronous dynamic random access memory.

8. The system according to claim 1, characterized in that The interface for realizing reading and writing data includes a command interface, a data interface, a clock interface and a response interface.

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