Storage device capable of improving storage capacity through multiple main control chips

Abstract

The embodiment of the invention provides storage equipment for improving storage capacity through multiple main control chips, and relates to the technical field of storage. The storage device comprises a master control component, a slave control component and an inter-chip communication link, each of the master control part and the slave control part comprises a host interface, a host command processing unit, a storage command processing unit, a storage medium management unit and a medium interface controller; the master control part and the slave control part are communicated through an inter-chip communication link; a host interface in the main control component is coupled with a host and receives an IO command sent by the host; the master control component and the slave control component cooperatively process IO commands received by the master control component through a host interface of the master control component through an inter-chip communication link. According to the embodiment of the invention, the master control component and the slave control component cooperatively process the IO command from the host to access the NVM chip, so that the requirements of large-capacity and high-performance storage equipment are met.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a storage device. Background Art

[0002] Figure 1A The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 (hereinafter, the solid-state storage device is referred to as the storage device for short) includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] The above-mentioned NVM chip 105 includes NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc., which are common storage media.

[0004] The above-mentioned interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control part 104 issues a command to the NVM chip 105 in a manner complying with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash package that share a CE (Chip Enable) signal. A NAND flash package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash chip can execute commands and report status independently of each other.

[0008] Figure 1B shows a block diagram of a nonvolatile memory. Figure 2As shown, the non-volatile memory 105 includes one or more logical units (Logic Unit, LUN). The logical unit LUN is the smallest unit in which the NVM chip independently executes commands and reports status. The logical unit may include multiple planes. Multiple planes within a logical unit can access data in parallel. Multiple planes within a logical unit can be accessed in parallel, and multiple logical units within the non-volatile memory can execute commands and report status independently of each other. In the "Open NAND Flash Interface Specification (Revision 5.1)" available from https: / / media-www.micron.com / - / media / client / onfi / specs / onfi_5_1_final_1,d-,0.pdf? la=en&rev=27ed5d740c8543f8bba06dbbd56fe6fe, the meanings of target, logical unit (LUN), and plane are provided, which is part of the prior art.

[0010] Data is usually stored and read on a storage medium in pages. Data is erased in blocks. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (called a physical page) has a fixed size, such as 17664 bytes. A physical page can also have other sizes.

[0011] In the storage device 102, FTL (Flash Translation Layer) is used to maintain the mapping information from the logical address (LBA) to the physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, the address mapping can also be implemented using the intermediate address form. For example, the logical address is mapped to the intermediate address, and then the intermediate address is further mapped to the physical address. The table structure that stores the mapping information from the logical address to the physical address is called the FTL table. The FTL table is an important metadata in the storage device. The data items of the FTL table record the address mapping relationship in the storage device in units of data units.

[0012] The host accesses the storage device with IO commands that follow the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, and erase commands) that follow the interface protocol of the NVM chip based on the media interface commands. The control component also tracks that all media interface commands generated from an IO command have been executed and indicates the processing results of the IO command to the host.

[0013] See also Figure 1C The control component includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a medium interface controller 1044 and a storage medium management unit 1045. The host interface 1041 obtains the IO command provided by the host. The host command processing unit 1042 generates a storage command according to the IO command and provides it to the storage command processing unit 1043. The storage command can access the storage space of the same size, such as 4KB. The data unit corresponding to the data accessed by a storage command recorded in the NVM chip is called a data frame. The physical page records one or more data frames. For example, the size of the physical page is 17664 bytes, and the size of the data frame is 4KB, then one physical page can store 4 data frames.

[0014] The storage medium management unit 1045 maintains the conversion of the logical address to the physical address for each storage command. For example, the storage medium management unit 1045 includes an FTL table (the FTL will be explained below). For a read command, the storage medium management unit 1045 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage medium management unit 1045 allocates an available physical address for it and records the mapping relationship between the logical address (LBA) accessed by it and the allocated physical address. The storage medium management unit 1045 also maintains functions required for managing the NVM chip such as garbage collection and wear leveling.

[0015] The storage command processing unit 1043 operates the medium interface controller 1044 to issue a storage medium access command to the NVM chip 105 according to the physical address provided by the storage medium management unit 1045 .

[0016] For the purpose of clarity, the command sent by the host to the storage device 102 is called an IO command (including, for example, an NVMe read command and an NVMe write command), the command sent by the host command processing unit 1042 to the storage command processing unit 1043 is called a storage command, the command sent by the storage command processing unit 1043 to the medium interface controller 1044 is called a medium interface command, and the command sent by the medium interface controller 1044 to the NVM chip 105 is called a storage medium access command. The storage medium access command complies with the interface protocol of the NVM chip. Summary of the invention

[0017] With the demand for large-capacity storage devices, storage devices with higher performance and larger capacity are needed. The performance of storage devices is limited by the performance of control components. For example, the capacity of storage devices is limited by the number of flash memory channels of the control component. The flash memory channel includes the IO pins required for the control component to connect to the NVM chip. Through IO pin multiplexing, each flash memory channel can usually connect to 2 NVM chips. If more NVM chips need to be set in the storage device, more flash memory channels are required. For example, a single control component includes 8 flash memory channels, and 16T or 32T capacity is managed through 8 flash memory channels. For larger capacities such as 64T and 128T, the control component needs to provide more flash memory channels. Each flash memory channel also includes a LUN controller, and more flash memory channels enable more LUN controllers to access the NVM chip in parallel to improve the performance of the control component. However, for integrated circuit chips, as the number of flash memory channels increases, the manufacturing and testing costs also rise exponentially. The present application hopes to provide a large-capacity and high-performance storage device when the control component provides a limited number of flash memory channels.

[0018] In view of this, an embodiment of the present application provides a storage device including two control components, each of which includes a host interface, a host command processing unit, a storage command processing unit, a storage medium management unit, and a medium interface controller. Optionally, there is an inter-chip communication link between the two control components, and the two control components cooperate to process IO commands sent by the host through the inter-chip communication link to access the NVM chip, thereby meeting the requirements of large-capacity and high-performance storage devices.

[0019] According to a first aspect of an embodiment of the present application, a storage device is provided, including a master control component, a slave control component and an inter-chip communication link; the master control component includes a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit and a first medium interface controller; the slave control component includes a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit and a second medium interface controller; the first host interface is coupled to the host, the inter-chip communication link couples the second storage command processing unit to lead the first host command processing unit, and the master control component and the slave control component collaboratively process IO commands received from the first host interface through the inter-chip communication link.

[0020] Optionally, the main control component receives IO commands sent by the host through the first host interface, and sends the IO commands to the first host command processing unit; the first host command processing unit generates one or more storage commands according to the IO commands, and distributes the one or more storage commands to the first storage command processing unit and the second storage command processing unit.

[0021] Optionally, the first host command processing unit assigns one or more storage commands to the first storage command processing unit and the second storage command processing unit according to logical addresses indicated by the one or more storage commands.

[0022] Optionally, if the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands according to the NVMe write command, and alternately assigns the one or more first storage commands to the first storage command processing unit and the second storage command processing unit.

[0023] Optionally, if the IO command is an NVMe write command, the NVMe write command indicates a logical address range, and the first host command processing unit generates one or more first storage commands according to the logical address range and assigns them to the first storage command processing unit and the second storage command processing unit.

[0024] Optionally, the logical address range includes a first logical address range and a second logical address range, and the first host command processing unit assigns a first storage command whose indicated logical address is within the first logical address range to the first storage command processing unit, and assigns a first storage command whose indicated logical address is within the second logical address range to the second storage command processing unit.

[0025] Optionally, if the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands according to the NVMe write command, and assigns the first storage commands to the first storage command processing unit and the second storage command processing unit according to the parity of the logical addresses indicated by each first storage command.

[0026] Optionally, the first host command processing unit assigns the first storage command with an even logical address to the first storage command processing unit, and assigns the first storage command with an odd logical address to the second storage command processing unit; or, the first host command processing unit assigns the first storage command with an odd logical address to the first storage command processing unit, and assigns the first storage command with an even logical address to the second storage command processing unit.

[0027] Optionally, if the IO command is an NVMe read command, the first host command processing unit generates one or more second storage commands based on the NVMe read command, and assigns each second storage command to the storage command processing unit corresponding to the first storage command corresponding to it, wherein the logical address indicated by the second storage command is the same as the logical address indicated by the first storage command corresponding to it.

[0028] Optionally, the first storage medium management unit includes a first FTL table, which records the physical address corresponding to the logical address indicated by the storage command assigned to the first storage command processing unit; the second storage medium management unit includes a second FTL table, which records the physical address corresponding to the logical address indicated by the storage command assigned to the second storage command processing unit.

[0029] Optionally, if the IO command is an NVMe write command, the first host command processing unit moves the data indicated by the NVMe write command from the host to the cache of the storage device; and in response to the completion of the NVMe write command processing, sends an NVMe write command processing completion message to the host through the first host interface. If the IO command is an NVMe read command, the first host command processing unit moves the data indicated by the NVMe read command from the cache of the storage device to the host; and in response to the completion of the NVMe read command processing, sends an NVMe read command processing completion message to the host through the first host interface.

[0030] Optionally, the second storage command processing unit responds to the completion of processing the storage command sent by the first host command processing unit by feeding back a storage command processing completion message to the first host command processing unit; the first storage command processing unit responds to the completion of processing the storage command sent by the first host command processing unit by feeding back a storage command processing completion message to the first host command processing unit.

[0031] Optionally, the master control component and the slave control component share a cache of the storage device.

[0032] According to a second aspect of an embodiment of the present application, a storage device is provided, comprising a master control component, a slave control component and an inter-chip communication link; the master control component comprises a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit and a first medium interface controller; the slave control component comprises a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit and a second medium interface controller; the master control component and the slave control component communicate via the inter-chip communication link; the first host interface is coupled to the host; the master control component and the slave control component collaboratively process IO commands received from the first host interface via the inter-chip communication link.

[0033] In an optional embodiment, the second host interface, the second host command processing unit, the second storage command processing unit and the second storage medium management unit do not work; the inter-chip communication link couples the second medium interface controller to the main control component as a bus device.

[0034] In an optional embodiment, an inter-chip communication link couples the second media interface controller to the first storage command processing unit in the first control component.

[0035] In an optional embodiment, the main control component receives IO commands sent by the host through the first host interface, and sends the IO commands to the first host command processing unit; the first host command processing unit generates one or more storage commands according to the IO commands, and sends the one or more storage commands to the first storage command processing unit; the first storage command processing unit generates one or more media interface commands according to the one or more storage commands, and distributes the media interface commands to the first media interface controller and the second media interface controller.

[0036] In an optional embodiment, the master control component is connected to the cache of the storage device, and the slave control component is not connected to the cache of the storage device; the second media interface controller accesses the cache of the storage device through an inter-chip communication link to obtain data indicated by the media interface command it receives.

[0037] In an optional embodiment, in response to completing the processing of a received media interface command, the first media interface controller feeds back a media interface command processing completion message to the first storage command processing unit; in response to completing the processing of a received media interface command, the second media interface controller feeds back a media interface command processing completion message to the first storage command processing unit; the first storage command processing unit receives the media interface command processing completion messages fed back by the first and second media interface controllers, generates a storage command processing completion message for the storage command corresponding to it based on the received media interface command processing completion message, and sends it to the first host command processing unit.

[0038] In an optional embodiment, the first storage command processing unit distributes one or more media interface commands to the first media interface controller and the second media interface controller according to physical addresses indicated by the one or more media interface commands.

[0039] In an optional embodiment, the first storage command processing unit determines the logical unit to be accessed according to the physical address indicated by each media interface command, and determines the NVM chip corresponding to the logical unit, and assigns the media interface command to the media interface controller in the control component coupled to the NVM chip.

[0040] In an optional embodiment, if the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands based on the NVMe write command, the first storage command processing unit allocates physical addresses to the logical addresses indicated by the one or more first storage commands based on the page stripe, and generates one or more first media interface commands based on the physical addresses corresponding to the logical addresses indicated by the one or more first storage commands.

[0041] In an alternative embodiment, a page stripe is composed of physical pages from NVM on-chip logic units coupled to the master control component and NVM on-chip logic units coupled to the slave control component.

[0042] In an alternative embodiment, the page stripe is composed of physical pages from logical units on all NVM chips coupled to the master control unit and logical units on all NVM chips coupled to the slave control unit.

[0043] In an alternative embodiment, the page stripe is composed of physical pages from logical units on a portion of the NVM chip coupled to the master control component and logical units on a portion of the NVM chip coupled to the slave control component.

[0044] Optionally, the first storage command processing unit allocates a physical address corresponding to a physical page in the page stripe to a logical address indicated by one or more storage commands.

[0045] Optionally, in response to receiving a first storage command, the first storage command processing unit allocates physical addresses from unallocated physical addresses in the first page stripe to the logical addresses indicated by the first storage command if the physical addresses in the first page stripe have not been fully allocated; and allocates physical addresses from physical addresses in the second page stripe to the logical addresses indicated by the first storage command if the physical addresses in the first page stripe have been fully allocated; the second page stripe and the first page stripe are different page stripes.

[0046] Optionally, the expected number of storage commands corresponding to the first page stripe is determined based on the storage space capacity corresponding to the first page stripe and the storage unit capacity indicated by the logical address; if the number of storage commands that currently allocate physical addresses from the first page stripe is less than the expected number, it indicates that the physical addresses in the first page stripe have not been fully allocated; if the number of storage commands that currently allocate physical addresses from the first page stripe is equal to the expected number, it indicates that the physical addresses in the first page stripe have been fully allocated.

[0047] Optionally, the first storage medium management unit is coupled to an FTL table, and the FTL table records the physical addresses allocated by the first storage command processing unit to the logical addresses indicated by each received storage command.

[0048] Optionally, if the IO command is an NVMe read command, the first host command processing unit generates one or more second storage commands based on the NVMe read command; the first storage command processing unit determines the physical address corresponding to the logical address indicated by the second storage command by querying the FTL table, and generates one or more second media interface commands based on the physical address.

[0049] Optionally, if the IO command is an NVMe write command, the first host command processing unit moves the data indicated by the NVMe write command from the host to the cache of the storage device; and in response to the completion of the NVMe write command processing, sends an NVMe write command processing completion message to the host through the first host interface; if the IO command is an NVMe read command, the first host command processing unit moves the data indicated by the NVMe read command from the cache of the storage device to the host; and in response to the completion of the NVMe read command processing, sends an NVMe read command processing completion message to the host through the first host interface.

[0050] Optionally, the first control component and the second control component have the same circuit structure.

[0051] According to a third aspect of an embodiment of the present application, a storage device is provided, comprising: a first control component and a second control component; the first control component comprises a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit and a first medium interface controller; the second control component comprises a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit and a second medium interface controller; the first control component is coupled to the first host via the first host interface, and the second control component is coupled to the second host via the second host interface.

[0052] Optionally, the first control component receives an IO command sent by the first host through the first host interface, and the second control component receives an IO command sent by the second host through the second host interface. The IO command sent by the first host to the first control component and the IO command sent by the second host to the second control component are different IO commands.

[0053] Optionally, the first control component and the second control component independently process the IO commands received by each.

[0054] Optionally, the storage device further includes: an inter-chip communication link; the first control component and the second component collaboratively process the received IO command via the inter-chip communication link.

[0055] Optionally, the inter-chip communication link includes at least one of the following: a first inter-chip communication link formed by coupling the second storage command processing unit and the first host command processing unit; a second inter-chip communication link formed by coupling the first storage command processing unit and the second host command processing unit; a third inter-chip communication link formed by coupling the second host interface and the first host command processing unit; and a fourth inter-chip communication link formed by coupling the first storage command processing unit and the second media interface controller.

[0056] Optionally, the first control component receives a first IO command sent by the first host through the first host interface, and sends the first IO command to the first host command processing unit; the first host command processing unit generates one or more first storage commands according to the first IO command, and allocates the one or more first storage commands to the first storage command processing unit and to the second storage command processing unit through the first inter-chip communication link.

[0057] Optionally, the first host command processing unit distributes part of the first storage command to the second storage command processing unit through the first inter-chip communication link.

[0058] Optionally, the first host command processing unit assigns one or more first storage commands to the first storage command processing unit and the second storage command processing unit according to logical addresses indicated by the one or more first storage commands.

[0059] Optionally, if the first IO command is an NVMe write command, the first host command processing unit generates one or more second storage commands according to the NVMe write command, and alternately assigns the one or more second storage commands to the first storage command processing unit and the second storage command processing unit.

[0060] Optionally, if the first IO command is an NVMe write command, the NVMe write command indicates a logical address range, and one or more second storage commands generated by the first host command processing unit according to the NVMe write command are assigned to the first storage command processing unit and the second storage command processing unit according to the logical address range.

[0061] Optionally, the logical address range includes a first logical address range and a second logical address range, and the first host command processing unit assigns a second storage command whose indicated logical address is within the first logical address range to the first storage command processing unit, and assigns a second storage command whose indicated logical address is within the second logical address range to the second storage command processing unit.

[0062] Optionally, if the first IO command is an NVMe write command, the first host command processing unit generates one or more second storage commands based on the NVMe write command, and assigns the second storage commands to the first storage command processing unit and the second storage command processing unit based on the parity of the logical addresses indicated by each second storage command.

[0063] Optionally, the first host command processing unit assigns the second storage command with an even logical address to the first storage command processing unit, and assigns the second storage command with an odd logical address to the second storage command processing unit; or, the first host command processing unit assigns the second storage command with an odd logical address to the first storage command processing unit, and assigns the second storage command with an even logical address to the second storage command processing unit.

[0064] Optionally, if the first IO command is an NVMe read command, the first host command processing unit generates one or more third storage commands based on the NVMe read command, and assigns each third storage command to the storage command processing unit corresponding to the corresponding second storage command, wherein the logical address indicated by the third storage command is the same as the logical address indicated by the corresponding second storage command.

[0065] Optionally, the second control component receives a second IO command sent by the second host through the second host interface, and sends the second IO command to the second host command processing unit; the second host command processing unit generates one or more fourth storage commands according to the second IO command, and allocates the one or more fourth storage commands to the first storage command processing unit and to the second storage command processing unit through the second inter-chip communication link.

[0066] Optionally, the second host command processing unit distributes part of the fourth storage command to the first storage command processing unit through the second inter-chip communication link.

[0067] Optionally, the second host interface in the second control component distributes the received one or more third IO commands to the first host command processing unit and distributes them to the second host command processing unit through the third inter-chip communication link.

[0068] Optionally, the second control component distributes part of the third IO commands to the first host command processing unit through a third inter-chip communication link.

[0069] Optionally, the first control component receives a fourth IO command through the first host interface and sends the fourth IO command to the first host command processing unit, the second control component receives a fifth IO command through the second host interface, and sends the fifth IO command to the first host command processing unit through the third inter-chip communication link; the first host command processing unit generates one or more fifth storage commands according to the fourth IO command and generates one or more sixth storage commands according to the fifth IO command, and distributes the one or more fifth storage commands and the one or more sixth storage commands to the first storage command processing unit and to the second storage command processing unit through the first inter-chip communication link.

[0070] Optionally, the first host command processing unit distributes part of the fifth storage command and part of the sixth storage command to the second storage command processing unit through the first inter-chip communication link.

[0071] Optionally, the second host command processing unit in the second control component does not work, and the second control component sends all fifth IO commands received by it to the first host command processing unit through the third inter-chip communication link.

[0072] Optionally, the first storage command processing unit generates one or more media interface commands according to the received seventh storage command, and assigns the one or more media interface commands to the first media interface controller and to the second media interface controller via the fourth inter-chip communication link.

[0073] Optionally, the first storage command processing unit distributes part of the media interface commands to the second media interface controller through a fourth inter-chip communication link.

[0074] Optionally, the first storage command processing unit distributes one or more media interface commands to the first media interface controller and the second media interface controller according to physical addresses indicated by the one or more media interface commands.

[0075] Optionally, the first storage command processing unit determines the logical unit to be accessed according to the physical address indicated by each media interface command, and determines the NVM chip corresponding to the logical unit, and distributes the media interface command to the media interface controller in the control component coupled to the NVM chip.

[0076] Optionally, if the seventh storage command is a storage command corresponding to the NVMe write command, the first storage command processing unit allocates a physical address to the logical address indicated by the seventh storage command according to the page stripe, and generates one or more first media interface commands according to the physical address corresponding to the logical address indicated by the seventh storage command.

[0077] Optionally, the page stripe is composed of physical pages from a NVM on-chip logic unit coupled to the first control component and a NVM on-chip logic unit coupled to the second control component.

[0078] Optionally, the page stripe is composed of physical pages from logical units on all NVM chips coupled to the first control component and logical units on all NVM chips coupled to the second control component.

[0079] Optionally, the page stripe is composed of physical pages from logical units on a portion of the NVM chip coupled to the first control component and logical units on a portion of the NVM chip coupled to the second control component.

[0080] Optionally, the first storage command processing unit allocates a physical address corresponding to a physical page in the page stripe to one or more logical addresses indicated by the sixth storage command.

[0081] Optionally, in response to receiving the new seventh storage command, the first storage command processing unit allocates physical addresses from unallocated physical addresses in the first page stripe to the logical addresses indicated by the new seventh storage command if the physical addresses in the first page stripe have not been allocated; if the physical addresses in the first page stripe have been allocated, allocates physical addresses from physical addresses in the second page stripe to the logical addresses indicated by the new seventh storage command; the second page stripe and the first page stripe are different page stripes.

[0082] Optionally, the expected number of storage commands corresponding to the first page stripe is determined based on the storage space capacity corresponding to the first page stripe and the storage unit capacity indicated by the logical address; if the number of storage commands that currently allocate physical addresses from the first page stripe is less than the expected number, it indicates that the physical addresses in the first page stripe have not been fully allocated; if the number of storage commands that currently allocate physical addresses from the first page stripe is equal to the expected number, it indicates that the physical addresses in the first page stripe have been fully allocated.

[0083] Optionally, if the seventh storage command is a storage command corresponding to the NVMe read command, the first storage command processing unit determines the physical address corresponding to the logical address indicated by the seventh storage command by querying the first FTL table coupled to the first storage medium management unit, and generates one or more second medium interface commands according to the physical address.

[0084] Optionally, the first control component receives the sixth IO command through the first host interface and sends the sixth IO command to the first host command processing unit, the second control component receives the seventh IO command through the second host interface, and sends the seventh IO command to the first host command processing unit through the third inter-chip communication link; the first host command processing unit generates one or more eighth storage commands according to the sixth IO command and one or more ninth storage commands according to the seventh IO command, and sends the one or more eighth storage commands and one or more ninth storage commands to the first storage command processing unit; the first storage command processing unit generates corresponding media interface commands according to the received eighth storage commands and ninth storage commands, and distributes the generated media interface commands to the first media interface controller and to the second media interface controller through the fourth inter-chip communication link.

[0085] Optionally, the second host command processing unit, the second storage command processing unit, and the second storage medium management unit do not work.

[0086] Optionally, the first storage medium management unit is coupled to the first FTL table, the second storage medium management unit is coupled to the second FTL table, and the first FTL table and the second FTL table manage and maintain the logical address space provided by the storage device.

[0087] Optionally, the first control component and the second control component share a first FTL table managed and maintained by the first storage medium management unit; the first FTL table manages and maintains a logical address space provided by the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0089] Figure 1A A block diagram of a solid-state storage device in the prior art is shown;

[0090] Figure 1B A block diagram showing a logic unit in a solid-state storage device;

[0091] Figure 1C A block diagram showing a control component in a solid-state storage device in the prior art;

[0092] Figure 2 A schematic diagram of the structure of a storage device according to an embodiment of the present application is shown;

[0093] Figure 3 A schematic diagram of the structure of the coupling between the control component and the host in the storage device provided by the embodiment of the present application is shown;

[0094] Figure 4 A schematic diagram showing the host command processing unit 1 allocating storage commands according to an embodiment of the present application is shown;

[0095] Figure 5 A schematic diagram showing the host command processing unit 1 allocating storage commands according to another embodiment of the present application is shown;

[0096] Figure 6 A schematic diagram showing the host command processing unit 1 allocating storage commands according to another embodiment of the present application is shown;

[0097] Figure 7 A schematic diagram showing a storage device processing an NVMe read command according to an embodiment of the present application is shown;

[0098] Figure 8 A schematic diagram showing the connection between the control component 3 and the control component 4 in the storage device provided in an embodiment of the present application is shown;

[0099] Fig. 9 A schematic diagram showing a storage device according to an embodiment of the present application allocating physical addresses according to page stripes is shown;

[0100] Fig.10 A schematic diagram of a construction page strip provided in an embodiment of the present application is shown;

[0101] Fig.11 A schematic diagram showing another structure of a page strip provided in an embodiment of the present application is shown;

[0102] Fig.12 A schematic diagram of a storage device processing an NVMe read command provided by an embodiment of the present application is shown;

[0103] Fig.13 A schematic diagram showing the structure of coupling between a control component and a host in a storage device according to another embodiment of the present application is shown;

[0104] Figures 14A-14E A schematic diagram showing the connection between the control component 5 and the control component 6 in the embodiment of the present application is shown;

[0105] Fig.15 A schematic diagram showing the connection between the control component 5 and the control component 6 in the embodiment of the present application is shown;

[0106] Fig.16 A connection diagram of the control component 5 and the control component 6 in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0107] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0108] Figure 2 A schematic diagram of a storage device according to an embodiment of the present application is shown.

[0109] As an example, Figure 2 As shown, the storage device includes a control component 1 and a control component 2.

[0110] The control component 1 includes: a host interface 1, a host command processing unit 1, a storage command processing unit 1, a storage medium management unit 1 and a medium interface controller 1. The control component 1 can be coupled to one or more NVM chips. For example Figure 2 As shown, the control unit 1 is coupled to four NVM chips.

[0111] The control component 2 includes: a host interface 2, a host command processing unit 2, a storage command processing unit 2, a storage medium management unit 2 and a medium interface controller 2. The control component 2 can be coupled to one or more NVM chips, such as Figure 2 As shown, the control component 2 is coupled to four NVM chips. The number of NVM chips coupled to the control component 2 may be equal to or different from the number of NVM chips coupled to the control component 1, and this application does not limit this.

[0112] The storage device processes the IO commands sent by the host through control component 1 and control component 2. For example, control component 1 and control component 2 can both be coupled to the host. Control component 1 and control component 2 can be coupled to the same host or to different hosts. Control component 1 and control component 2 respectively receive IO commands sent from the host coupled thereto, and process the received IO commands. For another example, only one of control component 1 and control component 2 can be coupled to the host to receive IO commands sent by the host. Control component 1 and control component 2 communicate with each other through an inter-chip communication link to collaboratively process the IO commands sent by the host. The inter-chip communication link is, for example, a die to die link (inter-die communication interconnect). Commonly used inter-die interconnects include, for example, communication links based on the UCIe (Universal Chiplet Interconnect Express, https: / / www.uciexpress.org / ) protocol, NVLink (https: / / www.nvidia.cn / data-center / nvlink / ), EMIB (Embedded Multi-die Interconnect Bridge, https: / / ieeexplore.ieee.org / abstract / document / 7545486), etc.

[0113] In the case where one control component in the storage device is coupled to the host and the other control component is not coupled to the host, the control component coupled to the host is referred to as the master control component and the control component not coupled to the host is referred to as the slave control component. In this case, the master control component and the slave control component cooperate to process the IO command sent by the host. For example, the master control component receives the IO command sent by the host and distributes the work of processing the IO command to the master control component and the slave control component, so that the master control component and the slave control component cooperate to process an IO command.

[0114] It should be understood that more control components may be provided in the storage device according to different requirements, and the present application is not limited to the following. Figure 2As shown, two control components are set in the storage device. No matter how many control components are set in the storage device, as long as the solution provided in the embodiment of the present application is implemented by multiple control components cooperating to process IO commands, it is within the protection scope of the embodiment of the present application and is not limited here.

[0115] Figure 3 A schematic diagram of the structure of the coupling between the control component and the host in the storage device provided in an embodiment of the present application is shown.

[0116] As an example, Figure 3 As shown, the control component 1 is coupled to the host through the host interface 1, and the control component 2 is not coupled to the host. Since the control component 2 is not coupled to the host and cannot interact with the host through its host interface 2, the host interface 2 in the control component 2 will not work. In order to enable the control component 1 and the control component 2 to process the IO command in coordination, the control component 2 will participate in part of the work of processing the IO command. For example, the storage command processing unit 2 in the control component 2 is coupled to the host command processing unit 1 in the control component 1, and the control component 2 participates in the processing of some storage commands corresponding to the IO command and the corresponding media interface commands and storage media access commands.

[0117] The control component 1 receives an IO command that complies with the NVMe protocol sent by the host through the host interface 1, and sends the IO command to the host command processing unit 1. The host command processing unit 1 generates one or more storage commands according to the IO command, and distributes the generated one or more storage commands to the storage command processing unit 1 and the storage command processing unit 2, so as to distribute the processing work of the storage command corresponding to the IO command and the subsequent related work to the two control components, and the two control components cooperate to complete the processing of the storage command, the medium interface command and the storage medium access command corresponding to the IO command.

[0118] The storage device of the embodiment of the present application cooperates with two control components to process IO commands that comply with the NVMe protocol to access the NVM chip, thereby achieving large capacity and high performance requirements.

[0119] Figure 3 It can be seen that in the embodiment of the present application, all units in the control component 1 will participate in the work, while only the storage command processing unit, the storage medium management unit, and the medium interface controller will participate in the work in the control component 2. The operations before the storage command are all processed by the control component 1, and the control component 2 does not participate in the operations before the storage command processing, but only participates in the operations from the storage command processing to the access to the NVM chip.

[0120] Optionally, Figure 3There is an inter-chip communication link between the control component 1 and the control component 2 shown, and the control component 1 communicates with the control component 2 through the inter-chip communication link. For example, the host command processing unit 1 in the control component 1 sends a storage command to the storage command processing unit 2 in the control component 2 through the inter-chip communication link.

[0121] In an optional embodiment, the host command processing unit 1 of the main control component generates one or more storage commands according to the logical address range indicated by the IO command, and each logical address corresponds to a storage command. Then, the host command processing unit of the main control component distributes the one or more storage commands corresponding to the IO command to the storage command processing unit 1 in the main control component and the storage command processing unit 2 in the slave control component for processing according to the logical address indicated by the storage command.

[0122] Combine the following Figure 3 , taking the IO command sent by the host as an NVMe write command as an example, the process of the main control component and the slave control component 2 jointly processing the IO command from the host is described.

[0123] Process (1): The host interface 1 of the control component 1 receives the NVMe write command sent by the host, and sends the NVMe write command to the host command processing unit 1.

[0124] Process (2): The host command processing unit 1 parses the received NVMe write command and generates one or more storage commands according to the logical address range indicated by the NVMe write command, and each logical address corresponds to a storage command. For example, the logical address range indicated by the NVMe write command is LBA0-LBA100, and the host command processing unit 1 generates 101 storage commands according to the NVMe write command. The host command processing unit 1 assigns each storage command to the slave storage command processing unit 1 or the storage command processing unit 2 for processing according to the logical address indicated by each storage command.

[0125] Process (3-1): The storage command processing unit 1 parses the received storage command, allocates a physical address to the logical address indicated by the storage command, and generates a media interface command according to the physical address corresponding to the logical address.

[0126] Process (4-1): The storage command processing unit 1 sends a media interface command to the media interface controller 1.

[0127] Process (5-1): The media interface controller 1 generates a corresponding storage medium access command based on the received media interface command, accesses the NVM chip coupled to the control component 1 based on the storage medium access command, and writes data to the NVM chip.

[0128] Process (3-2): The storage command processing unit 2 parses the received storage command, allocates a physical address to the logical address indicated by the storage command, and generates a media interface command for the physical address corresponding to the logical address.

[0129] Process (4-2): The storage command processing unit 2 sends the media interface command to the media interface controller 2.

[0130] Process (5-2): The media interface controller 2 generates a corresponding storage medium access command based on the received media interface command, accesses the NVM chip coupled to the access control component 2 based on the storage medium access command, and writes data to the NVM chip.

[0131] Optionally, in response to completing the processing of the storage command assigned by the host command processing unit 1, the storage command processing unit 1 feeds back a storage command processing completion message to the host command processing unit 1. In response to completing the processing of the storage command assigned by the host command processing unit 1, the storage command processing unit 2 feeds back a storage command processing completion message to the host command processing unit 1.

[0132] The storage medium management unit 1 in the control component 1 manages and maintains the FTL table 1, and the storage medium management unit 2 in the control component 2 manages and maintains the FTL table 2. Optionally, the FTL table 1 and the FTL table 2 record and manage the physical addresses corresponding to different logical addresses. The FTL table 1 records and manages the physical address corresponding to the logical address indicated by the storage command sent by the host command processing unit 1 to the storage command processing unit 1, and the FTL table 2 records and manages the physical address corresponding to the logical address indicated by the storage command sent by the host command processing unit 1 to the storage command processing unit 2. In another optional embodiment, the FTL table 1 and the FTL table 2 can record the physical address corresponding to the same logical address, and both the FTL table 1 and the FTL table 2 record the physical addresses corresponding to all logical addresses indicated by the IO command.

[0133] Optionally, control component 1 and control component 2 share a cache of a storage device, such as DRAM. The host command processing unit 1 of control component 1 generates a DMA command based on the received NVMe write command, and executes an operation of moving the data indicated by the NVMe write command from the host to the storage device cache such as DRAM according to the DMA command. The process of the host command processing unit 1 generating a DMA command and moving data can refer to Chinese patents 202110746142.2 or 202310788448.3, which will not be repeated here. The host command processing unit 1 moves the data indicated by the NVMe write command to DRAM in response to generating one or more storage commands corresponding to the data. The media interface controller 1 and the media interface controller 2 write the data in the DRAM to the NVM chip based on the received media interface command, respectively. In response to the completion of the NVMe write command processing, the host command processing unit 1 sends an NVMe write command processing completion message to the host through the host interface 1.

[0134] Figure 4 A schematic diagram showing the allocation of storage commands by the host command processing unit 1 according to an embodiment of the present application is shown.

[0135] As an example, Figure 4 As shown, the host command processing unit 1 sends storage commands alternately to the storage command processing unit 1 and the storage command processing unit 2. If the logical address range indicated by the NVMe write command is LBA51-LBA71, 21 storage commands are generated according to the NVMe write command, and the host command processing unit 1 allocates the 21 storage commands alternately to the storage command processing unit 1 and the storage command processing unit 2. For example, the allocation starts from the storage command processing unit 1, the storage command indicating LBA51 is allocated to the storage command processing unit 1, the storage command indicating LBA52 is allocated to the storage command processing unit 2, the storage command indicating LBA53 is allocated to the storage command processing unit 1, the storage command indicating LBA54 is allocated to the storage command processing unit 2, and so on, until all storage commands are allocated.

[0136] In response to receiving a storage command sent by the host command processing unit 1, the storage command processing unit 1 and the storage command processing unit 2 allocate a physical address to the logical address indicated by the storage command, and record the allocated physical address in the corresponding FTL table entry. For example, in response to receiving a storage command indicating LBA51, the storage command processing unit 1 determines that it corresponds to entry 0 of the FTL table 1 according to LAB51; allocates a physical address to LBA51, and stores the physical address corresponding to LBA51 in entry 0 of the FTL table 1. In response to receiving a storage command indicating LBA53, the storage command processing unit 1 determines that it corresponds to entry 1 of the FTL table 1 according to LAB53; allocates a physical address to LBA53, and stores the physical address corresponding to LBA53 in entry 1 of the FTL table 1. By analogy, the physical addresses corresponding to the logical addresses indicated by all storage commands assigned to the storage command processing unit 1 by the host command processing unit 1 are recorded in the entries of the FTL table 1, and each entry records the physical address corresponding to a logical address. Similarly, the physical addresses corresponding to the logical addresses indicated by all storage commands assigned by the host command processing unit 1 to the storage command processing unit 2 are recorded in the entries of the FTL table 2, and each entry records the physical address corresponding to a logical address. For example, in response to receiving a storage command indicating LBA52, the storage command processing unit 2 determines that it corresponds to entry 0 of the FTL table 2 according to LAB52; assigns a physical address to LBA52, and stores the physical address corresponding to LBA52 in entry 0 of the FTL table 2. In response to receiving a storage command indicating LBA54, the storage command processing unit 2 determines that it corresponds to entry 1 of the FTL table 2 according to LAB54; assigns a physical address to LBA54, and stores the physical address corresponding to LBA54 in entry 1 of the FTL table 2.

[0137] In an optional embodiment, the host command processing unit 1 continuously sends a specified number of storage commands to the storage command processing unit 1 or the storage command processing unit 2, wherein the sum of the number of storage commands sent to the storage command processing unit 1 and the number of storage commands sent to the storage command processing unit 2 is equal to the number of storage commands corresponding to the NVMe write command. For example, the host command processing unit 1 generates P storage commands according to the NVMe write command, continuously sends Q storage commands to the storage command processing unit 1, and then continuously sends (PQ) storage commands to the storage command processing unit 2, where P is an integer greater than 1, Q is an integer greater than or equal to 1 and Q is less than P. If the NVMe write command corresponds to 100 storage commands, the host command processing unit 1 sends the first 50 generated storage commands to the storage command processing unit 1, and sends the last 50 generated storage commands to the storage command processing unit 2. In another optional embodiment, the host command processing unit 1 allocates storage commands to the storage command processing unit 1 and the storage command processing unit 2 according to the logical address range corresponding to the NVMe write command. If the logical address range indicated by the NVMe write command is LBAn-LBAk, the host command processing unit 1 assigns the storage command with the logical address in [LBAn, LBAm] to the storage command processing unit 1, and assigns the storage command with the logical address in [LBA(m+1), LBAk] to the storage command processing unit 2. Where n, m, and k are all integers, and n <m<k。

[0138] As an example, Figure 5 As shown, the host command processing unit 1 receives the NVMe write command 1, and the logical address range indicated by the NVMe write command 1 is [LBA0, LBA200]. Multiple storage commands are generated according to the NVMe write command 1. For each storage command, if the logical address indicated by the storage command is within [LBA0, LBA100], the storage command is assigned to the storage command processing unit 1, and the physical address assigned to the logical address within [LBA0, LBA100] is recorded in the entry of the FTL table 1. If the logical address indicated by the storage command is within [LBA101, LBA200], the storage command is assigned to the storage command processing unit 2, and the physical address assigned to the logical address within [LBA101, LBA200] is recorded in the entry of the FTL table 2. For example, the host command processing unit 1 assigns the storage command with the logical address LBA45 to the storage command processing unit 1, and assigns the storage command with the logical address LBA170 to the storage command processing unit 2.

[0139] In an optional embodiment, the host command processing unit 1 allocates storage commands to the storage command processing unit 1 and the storage command processing unit 2 according to the parity of the logical address indicated by the storage command. Figure 6As shown, the logical address range indicated by the NVMe write command is LBA40-LBA100, and the host command processing unit 1 assigns the storage command with an even logical address (such as LBA40, LBA42, LBA44, ..., LBA100) to the storage command processing unit 1, and assigns the storage command with an odd logical address (such as LBA41, LBA43, LBA45, ..., LBA99) to the storage command processing unit 2. The physical address assigned to the storage command with an even logical address (such as LBA40, LBA42, LBA44, ..., LBA100) is recorded in the entry of FTL table 1, and the physical address assigned to the storage command with an odd logical address (such as LBA41, LBA43, LBA45, ..., LBA99) is recorded in FTL table 2.

[0140] Optionally, the host command processing unit 1 can also assign storage commands with odd logical addresses (such as LBA41, LBA43, LBA45,..., LBA99) to the storage command processing unit 1, and assign storage commands with even logical addresses (such as LBA40, LBA42, LBA44,..., LBA100) to the storage command processing unit 1.

[0141] The process of the master control unit and the slave control unit cooperating to process the NVMe read command is similar to the process of processing the NVMe write command. Figure 7 Provide explanation.

[0142] like Figure 7 As shown, the process of the master control component and the slave control component jointly processing the NVMe read command includes:

[0143] Process (1-1): The host interface 1 of the control component 1 receives the NVMe read command sent by the host, and sends the NVMe read command to the host command processing unit 1.

[0144] Process (1-2): The host command processing unit 1 parses the received NVMe read command, generates one or more storage commands according to the LBA range indicated by the NVMe read command (the storage command generated according to the NVMe read command is different from the storage command generated according to the NVMe write command), and assigns the one or more storage commands to the storage command processing unit 1 and the storage command processing unit 2.

[0145] Host command processing unit 1 distributes the storage command to storage command processing unit 1 and storage command processing unit 2.

[0146] The strategy of the host command processing unit 1 to allocate storage commands corresponding to NVMe read commands is consistent with the strategy of the host command processing unit 1 to allocate storage commands corresponding to NVMe write commands. For example, the storage commands corresponding to the NVMe write commands and the storage commands corresponding to the NVMe read commands indicating the same logical address should be allocated to the storage command processing unit in the same control component for processing. For example, when the host command processing unit 1 processes the NVMe write command, the storage command corresponding to LBA0 is allocated to the storage command processing unit 1 in the control component 1, and when reading the data corresponding to LBA0, the corresponding storage command is also allocated to the storage command processing unit 1. For another example, when the host command processing unit 1 processes the NVMe write command, the storage command whose indicated logical address is an even number is allocated to the storage command processing unit 1, and the storage command whose indicated logical address is an odd number is allocated to the storage command processing unit 2. Then, when the host command processing unit 1 processes the NVMe read command, the storage command whose indicated logical address is an even number is allocated to the storage command processing unit 1, and the storage command whose indicated logical address is an odd number is allocated to the storage command processing unit 2.

[0147] As an example, in response to completing the processing of the storage command assigned by the host command processing unit 1, the storage command processing unit 1 feeds back a storage command processing completion message to the host command processing unit 1. In response to completing the processing of the storage command assigned by the host command processing unit 1, the storage command processing unit 2 feeds back a storage command processing completion message to the host command processing unit 1.

[0148] Process (1-3): Storage command processing unit 1 generates a media interface command according to the received storage command, and sends the media interface command to media interface controller 1. Storage command processing unit 2 generates a media interface command according to the received storage command, and sends the media interface command to media interface controller 2.

[0149] Process (1-4): The media interface controller 1 accesses the NVM chip coupled to the control component 1 according to the received media interface command, reads the corresponding data from the NVM chip, and stores the read data in the DRAM. The media interface controller 2 accesses the NVM chip coupled to the control component 2 according to the received media interface command, reads the corresponding data from the NVM chip, and stores the read data in the DRAM.

[0150] Process (1-5): The host command processing unit 1 moves the data stored in the DRAM by the media interface controller 1 and the media interface controller 2 to the host. The process of the host command processing unit 1 moving the data stored in the DRAM to the host can be referred to Chinese patents 202110746144.1 to 202310788454.9, which will not be repeated here.

[0151] Process (1-6): In response to the NVMe read command being processed, the host command processing unit 1 sends an NVMe read command processing completion message to the host.

[0152] Figure 8 A schematic diagram of the structure of coupling between a control component and a host in a storage device provided in another embodiment of the present application is shown.

[0153] like Figure 8 As shown, the control component 3 is coupled to the host through the host interface 3, and the control component 4 is not coupled to the host. The control component 3 receives the IO command sent by the host, and the control component 3 and the control component 4 cooperate to process the IO command received by the control component 3 through the inter-chip communication link. The host interface 4, the host command processing unit 4, the storage medium management unit 4, and the storage command processing unit 4 in the control component 4 do not work ( Figure 8 In the figure, the functional units in the control unit that are not working are indicated by shading. In order to process the IO command through the control unit 3 and the control unit 4 in a coordinated manner, in an optional embodiment, the inter-chip communication link couples the media interface controller 4 in the control unit 4 to the control unit 3 as a bus device. The bus is a group of public communication lines that can transmit information between multiple control units. The media interface controller 4 in the control unit 4 is connected to the bus and coupled to the control unit 3 as a bus device.

[0154] In some other optional embodiments, the inter-chip communication link couples the media interface controller 4 to the storage command processing unit 3 in the control component 3, and receives the media interface command sent by the storage command processing unit 3. The control component 4 participates in the processing of some media interface commands corresponding to the IO command and the corresponding storage medium access command.

[0155] The control component 3 receives the IO command sent by the host through the host interface 3, and sends the IO command to the host command processing unit 3. The host command processing unit 3 generates one or more storage commands according to the IO command, and sends the generated one or more storage commands to the storage command processing unit 3. The storage command processing unit 3 generates one or more media interface commands according to the received storage command, and distributes the one or more media interface commands to the media interface controller 3 and the media interface controller 4, so as to distribute the processing of the media interface command corresponding to the IO command to the two control components, and the two control components cooperate to process the IO command from the host. In this embodiment, the operations before the media interface command is processed are all completed by the control component 3, and the control component 4 does not participate in the operations before the media interface command, but only participates in the operation of the media interface command and the operation of accessing the NVM chip.

[0156] The media interface command indicates a physical address, which includes the LUN to be accessed and related information such as the physical block. When the storage command processing unit 3 distributes the media interface command to the media interface controller 3 and the media interface controller 4, the corresponding LUN can be determined according to the physical address indicated by each media interface command, and then the NVM chip where the command is located can be determined according to the LUN. The storage command processing unit 3 distributes each media interface command to the media interface controller of the control component coupled to the corresponding NVM chip according to the NVM chip to be accessed by the media interface command. For example Figure 8 As shown, control component 1 is coupled to NVM0 and NVM1. NVM1 includes LUN0 and LUN1. Control component 2 is coupled to NVM2 and NVM3. NVM2 includes LUN8 and LUN9. If the physical address indicated by media interface command 1 indicates that LUN0 is to be accessed, storage command processing unit 3 sends media interface command 1 to media interface controller 3 in control component 3. If the physical address indicated by media interface command 2 indicates that LUN9 is to be accessed, storage command processing unit 3 sends media interface command 2 to media interface controller 4 in control component 4.

[0157] The media interface controller 3 and the media interface controller 4 respectively generate storage media access commands according to the received media interface commands, and access the coupled NVM chips according to their respective storage media access commands. Optionally, the media interface controller 3 and the media interface controller 4 can process the corresponding media interface commands in parallel without interfering with each other. In response to completing the processing of the received media interface command, the media interface controller 3 feeds back a media interface command processing completion message to the storage command processing unit 1. In response to completing the processing of the received media interface command, the media interface controller 4 feeds back a media interface command processing completion message to the storage command processing unit 1. The storage command processing unit 1 generates a storage command processing completion message based on the media interface command processing completion message, and feeds back the storage command processing completion message to the host command processing unit 1.

[0158] The cache of the storage device, such as DRAM, is coupled to the control component 3, and the control component 4 is not directly connected to the DRAM. When processing the media interface command, the media interface controller 4 accesses the DRAM through the inter-chip communication link to obtain the data that needs to be moved between the DRAM and the NVM chip.

[0159] exist Figure 8In the illustrated embodiment, the storage medium management unit 3 in the control component 3 manages and maintains the FTL table 3, and the FTL table 3 records and manages the physical address corresponding to the logical address indicated by the storage command received by the storage command processing unit 3. Since the storage command processing unit 3 and the storage medium management unit 4 in the control component 4 are not working, the FTL table 3 can record and manage the physical address corresponding to the logical address in the entire logical address space, that is, the FTL table 3 manages the mapping relationship between the logical address and the physical address in the entire logical address space.

[0160] Combine the following Figure 8 , taking the IO command sent by the host as an NVMe write command as an example, the process of control component 3 and control component 4 jointly processing the NVMe write command from the host is described.

[0161] Process (1): The control component 3 receives the NVMe write command sent by the host through the host interface 3, and sends the NVMe write command to the host command processing unit 3.

[0162] Process (2): The host command processing unit 3 parses the received NVMe write command, generates one or more storage commands according to the logical address range indicated by the NVMe write command, and sends the generated one or more storage commands to the storage command processing unit 3.

[0163] Process (3): The storage command processing unit 3 parses the received storage command, allocates a physical address to the logical address indicated by the storage command, and records the physical address allocated to the logical address in the FTL table 3.

[0164] Process (4): The storage command processing unit 3 generates a media interface command according to the physical address corresponding to the logical address. The storage command processing unit 3 distributes the media interface command to the media interface controller 3 or the media interface controller 4 according to the physical address indicated by the media interface command.

[0165] Process (5): The media interface controller 3 generates a corresponding storage medium access command based on the received media interface command, accesses the NVM chip coupled to the access control component 3 based on the storage medium access command, and writes data to the NVM chip. The media interface controller 4 generates a corresponding storage medium access command based on the received media interface command, accesses the NVM chip coupled to the access control component 4 based on the storage medium access command, and writes data to the NVM chip.

[0166] Among them, the host command processing unit 1 moves the data indicated by the NVMe write command from the host to the cache of the storage device such as DRAM. The media interface controller 3 moves the data indicated by the media interface command from the DRAM to the NVM chip coupled to the control component 3 according to the received media interface command. The media interface controller 4 accesses the DRAM through the inter-chip communication link and moves the data indicated by the received media interface command from the DRAM to the NVM chip coupled to the control component 4. In response to the completion of the NVMe write command processing, the host command processing unit 1 feeds back the NVMe write command processing completion message to the host through the host interface 3.

[0167] As an example, Figure 8 In the process (3) shown, the storage command processing unit 3 allocates a physical address to the logical address indicated by the NVMe write command in an alternating manner, such as the storage command processing unit 3 allocates a physical address on the NVM chip coupled to the control component 3 to the logical address indicated by the first storage command, and the storage command processing unit 3 allocates a physical address on the NVM chip coupled to the control component 4 to the logical address indicated by the second storage command, and so on.

[0168] As another example, the storage command processing unit 3 assigns a corresponding physical address to the logical address according to the parity of the logical address, such as assigning a physical address on the NVM chip coupled to the control component 3 to an odd-numbered logical address, and assigning a physical address on the NVM chip coupled to the control component 4 to an even-numbered logical address, and so on.

[0169] As another example, the storage command processing unit 3 can also allocate physical addresses to the logical addresses indicated by the NVMe write command in a page striping manner, and allocate the physical address corresponding to a physical page in the page stripe to the logical address indicated by one or more storage commands. When allocating physical addresses according to page stripes, if a page stripe is not fully allocated, the physical addresses of the physical pages of other page stripes will not be allocated to the logical address indicated by the received storage command. For example, the storage space size of each page stripe is equal to the storage space size represented by the LBA indicated by 100 storage commands, and each page stripe corresponds to 100 storage commands. If the number of storage commands that the storage command processing unit 3 uses to allocate physical addresses from a page stripe, such as page stripe 0, to the logical addresses indicated by the received storage commands is less than 100, then page stripe 0 has not been fully allocated. If the storage command processing unit 3 receives another storage command, such as storage command 5, it will still allocate the physical addresses corresponding to the unallocated physical pages in page stripe 0 to the logical addresses indicated by storage command 5. If the number of storage commands that allocate physical addresses from page stripe 0 to the logical addresses indicated by the received storage commands is equal to 100, then page stripe 0 has been fully allocated. If the storage command processing unit 3 receives another storage command, such as storage command 6, it will allocate physical addresses from a new page stripe, such as page stripe 2, to the logical addresses indicated by storage command 6.

[0170] Fig. 9 A schematic diagram of allocating physical addresses according to page stripes provided by the present application is shown.

[0171] As an example, Fig. 9 As shown, the NVM chip coupled to the control component in the storage device includes LUN0 to LUN15. The page stripe is composed of physical pages from LUN0 to LUN15. For example, page stripe 0 includes 15 physical pages (P0-0, P0-1, P0-2...P0-14, P0-15) from LUN0 to LUN15; wherein P0-0, P0-1, P0-2...P0-14 are used to store user data, and P0-15 is used to store check data; if the size of each physical page in the page stripe is equal to the storage unit size represented by the LBA indicated by a storage command, such as Fig. 9 The page stripe 0 and page stripe 2 shown correspond to 15 storage commands. For example, the physical addresses corresponding to the physical pages P0-0, P0-1, P0-2, ..., P0-14 in page stripe 0 will be respectively allocated to the logical addresses indicated by the 15 storage commands. Figure 8As shown in the figure, the storage command processing unit 3 allocates physical addresses for the received storage commands starting from page stripe 0. In response to receiving the first storage command (such as storage command 1 indicating LBA1), the physical address of physical page P0-0 in page stripe 0 is allocated to LBA1; in response to receiving the second storage command (such as storage command 2 indicating LBA3), the physical address of physical page P1-0 in page stripe 0 is allocated to LBA3; in response to receiving the third storage command (such as storage command 3 indicating LBA10), the physical address of physical page P2-0 in page stripe 0 is allocated to LBA10; and so on. When the storage command processing unit 3 receives the fifteenth storage command (such as storage command 15 indicating LBA2), the physical address of physical page P14-0 in page stripe 0 is allocated to LBA2, and at this time, page stripe 0 is completely allocated. When the storage command processing unit 3 receives the sixteenth storage command (such as storage command 16 indicating LBAm), it needs to allocate a physical address to LBAm from other page stripes, such as allocating the physical address of physical page P2-0 in page stripe 2 to LBAm, and so on.

[0172] Continue to see Figure 8 The storage command processing unit 3 allocates a physical address to the logical address indicated by the storage command according to the page stripe, and needs to construct a page stripe from the physical pages of the LUN on the NVM chips coupled to the two control components, and the page stripe spans the NVM chips coupled to the two control components. For example, the constructed page stripe includes both the physical pages of the LUN on the NVM chip coupled to the control component 3 and the physical pages of the LUN on the NVM chip coupled to the control component 4.

[0173] Fig.10 The structure of the page strip provided by the embodiment of the present application is shown. Fig.10 As shown, the control component 3 couples NVM0 and NVM1, and the control component 4 couples NVM2 and NVM3; wherein NVM0 includes logical units LUN0 and LUN1, NVM1 includes logical units LUN2 and LUN3, NVM2 includes logical units LUN4 and LUN5, and NVM4 includes logical units LUN6 and LUN7. Fig.10In the embodiment, page stripes are constructed by physical pages of LUNs on some NVM chips coupled to control component 3 and physical pages of LUNs on some NVM chips coupled to control component 4. For example, page stripe 0 includes physical pages (P0-0, P0-1) from NVM0 coupled to control component 3 and physical pages (P0-4, P0-5) of LUNs on NVM2 coupled to control component 4. Page stripe 1 includes physical pages (P0-2, P0-3) from NVM1 coupled to control component 3 and physical pages (P0-6, P0-7) from NVM3 coupled to control component 4. Page stripe 2 includes physical pages (P1-0, P1-1) from NVM0 coupled to control component 3 and physical pages (P1-4, P1-5) of NVM2 coupled to control component 4. Page stripe 3 includes physical pages (P1-2, P1-3) of NVM1 from coupling control unit 3 and physical pages (P1-6, P1-7) of NVM3 from coupling control unit 4. In page stripe 0, P0-0, P0-1, P0-4 are used to store user data, and P0-5 is used to store verification data. In page stripe 1, P0-2, P0-3, P0-6 are used to store user data, and P0-7 is used to store verification data. In page stripe 2, P1-0, P1-1, P1-4 are used to store user data, and P1-5 is used to store verification data. In page stripe 3, P1-2, P1-3, P1-6 are used to store user data, and P1-7 is used to store verification data. If the size of each physical page in the page stripe is equal to the storage unit size represented by the LBA indicated by a storage command, such as Fig.10 The page stripes 0-3 shown correspond to 3 storage commands. For example, the physical addresses corresponding to the physical pages P0-0, P0-1, and P0-4 in page stripe 0 will be respectively assigned to the logical addresses indicated by the 3 storage commands. For example, the host command processing unit 3 receives NVMe write command 1 and NVMe write command 2 successively. The logical address range indicated by NVMe write command 1 is LBA20-LBA24, and the logical address range indicated by NVMe write command 2 is LBA30-LBA36. The host command processing unit 3 generates 5 storage commands (such as storage command A1, storage command A2, storage command A3, storage command A4, and storage command A5) according to NVMe write command 1, and generates 7 storage commands (such as storage command B1, storage command B2, storage command B3, storage command B4, storage command B5, storage command B6, and storage command B7) according to NVMe write command 2. The storage command processing unit 3 assigns physical addresses to the received storage commands starting from page stripe 0. The storage command processing unit 3 allocates a physical address to the logical address indicated by each storage command, for example, in the following manner:

[0174] Assign the physical address of the physical page P0-0 in the page stripe 0 to the LBA20 indicated by the storage command A1; assign the physical address of the physical page P0-1 in the page stripe 0 to the LBA21 indicated by the storage command A2; assign the physical address of the physical page P0-4 in the page stripe 0 to the LBA22 indicated by the storage command A3; assign the physical address of the physical page P0-2 in the page stripe 1 to the LBA23 indicated by the storage command A4; assign the physical address of the physical page P0-3 in the page stripe 1 to the LBA24 indicated by the storage command A5; assign the physical address of the physical page P0-6 in the page stripe 1 to the LBA30 indicated by the storage command B1; The physical address of physical page P1-0 in page stripe 2 is allocated to LBA31 indicated by storage command B2; the physical address of physical page P1-1 in page stripe 2 is allocated to LBA32 indicated by storage command B3; the physical address of physical page P1-4 in page stripe 2 is allocated to LBA33 indicated by storage command B4; the physical address of physical page P1-2 in page stripe 3 is allocated to LBA34 indicated by storage command B5; the physical address of physical page P1-3 in page stripe 3 is allocated to LBA35 indicated by storage command B6; and the physical address of physical page P1-6 in page stripe 3 is allocated to LBA36 indicated by storage command B7.

[0175] The storage command processing unit 3 allocates physical addresses to multiple storage commands corresponding to the NVMe write command 1 and the NVMe write command 2 from the page stripes 0-3, that is, allocates physical addresses to multiple storage commands corresponding to the NVMe write command 1 and the NVMe write command 2 from the physical pages of the LUN on the NVM0 chip of the coupling control component 3 and the physical pages of the LUN on the NVM2 chip of the coupling control component 4, thereby allocating the multiple media interface commands corresponding to the NVMe write command 1 and the NVMe write command 2 to the media interface controller 3 in the control component 3 and the media interface controller in the control component 4, and writing the data indicated by the NVMe write command 1 and the NVMe write command 2 to the NVM0 chip coupled to the control component 3 and the NVM2 chip coupled to the control component 4.

[0176] Fig.11 Another method of constructing a stripe provided by an embodiment of the present application is shown. Fig.11 As shown, the NVM chip coupled to the control component 3 and the control component 4 is Fig.10 Similar, I will not go into details here. Fig.11In the embodiment, the page stripes are constructed by the physical pages of the LUNs on all the NVM chips coupled to the control component 3 and the physical pages of the LUNs on all the NVM chips coupled to the control component 4. For example, the page stripe 0 includes the physical pages (P0-0, P0-1, P0-2, P0-3) of the LUNs on the NVM0-NVM1 chips coupled to the control component 3 and the physical pages (P0-4, P0-5, P0-6, P0-7) of the LUNs on the NVM2-NVM3 chips coupled to the control component 4, and the page stripe 2 includes the physical pages (P2-0, P2-1, P2-2, P2-3) of the LUNs on the NVM0-NVM1 chips coupled to the control component 3 and the physical pages (P2-4, P2-5, P2-6, P2-7) of the LUNs on the NVM2-NVM3 chips coupled to the control component 4. For example, the host command processing unit 3 receives NVMe write command 3, NVMe write command 4 and NVMe write command 5 successively, the logical address range indicated by NVMe write command 3 is LBA40-LBA44, the logical address range indicated by NVMe write command 4 is LBA50-LBA56, and the logical address range indicated by NVMe write command 5 is LBA60-LBA61. The host command processing unit 3 generates 5 storage commands (such as storage command C1, storage command C2, storage command C3, storage command C4 and storage command C5) according to NVMe write command 3, generates 7 storage commands (such as storage command D1, storage command D2, storage command D3, storage command D4, storage command D5, storage command D6 and storage command D7) according to NVMe write command 4, and generates 2 storage commands (such as storage command E1 and storage command E7) according to NVMe write command 5. The storage command processing unit 3 allocates physical addresses to the logical addresses indicated by each storage command, for example, in the following manner:

[0177] The physical address of the physical page P0-0 in the page stripe 0 is allocated to the LBA40 indicated by the storage command C1; the physical address of the physical page P0-1 in the page stripe 0 is allocated to the LBA41 indicated by the storage command C2; the physical address of the physical page P0-2 in the page stripe 0 is allocated to the LBA42 indicated by the storage command C3; the physical address of the physical page P0-3 in the page stripe 0 is allocated to the LBA43 indicated by the storage command C4; the physical address of the physical page P0-4 in the page stripe 0 is allocated to the LBA44 indicated by the storage command C5; the physical address of the physical page P0-5 in the page stripe 0 is allocated to the LBA50 indicated by the storage command D1; the physical address of the physical page P0-6 in the page stripe 0 is allocated to the LBA51 indicated by the storage command D2; The physical address of physical page P2-0 in page stripe 2 is allocated to LBA52 indicated by storage command D3; the physical address of physical page P2-1 in page stripe 2 is allocated to LBA53 indicated by storage command D4; the physical address of physical page P2-2 in page stripe 2 is allocated to LBA54 indicated by storage command D5; the physical address of physical page P2-3 in page stripe 2 is allocated to LBA55 indicated by storage command D6; the physical address of physical page P2-4 in page stripe 2 is allocated to LBA56 indicated by storage command D7; the physical address of physical page P2-5 in page stripe 2 is allocated to LBA60 indicated by storage command E1; the physical address of physical page P2-6 in page stripe 2 is allocated to LBA61 indicated by storage command E2.

[0178] The storage command processing unit 3 allocates physical addresses for multiple storage commands corresponding to NVMe write command 3, NVMe write command 4 and NVMe write command 5 from page stripe 0 and page stripe 2, that is, allocates physical addresses for multiple storage commands corresponding to NVMe write command 3, NVMe write command 4 and NVMe write command 5 from the physical pages of the LUN of all NVM chips coupled to the control component 3 and all NVM chips coupled to the control component, thereby allocating multiple media interface commands corresponding to NVMe write command 3, NVMe write command 4 and NVMe write command 5 to the media interface controller 3 in the control component 3 and the media interface controller in the control component 4, and then writing the data indicated by NVMe write command 3, NVMe write command 4 and NVMe write command 5 to the NVM0 chip, NVM1 chip coupled to the control component 3 and the NVM2 chip, NVM4 chip coupled to the control component 4.

[0179] Depend on Fig.10 and Fig.11It can be seen that by constructing page stripes across the physical pages of the LUN on the NVM chip coupled to the control component 3 and the NVM chip coupled to the control component 4, the storage command processing unit 3 can allocate physical addresses for the logical addresses indicated by multiple storage commands received, for example, from one or more NVMe commands from the page stripes of the LUN on the NVM chip coupled to the control component 3 and the NVM chip coupled to the control component 4, so that the generated media interface commands are distributed to the media interface controller 3 in the control component 3 and the media interface controller 4 in the control component 4, thereby enabling the processing work for one or more NVMe commands to be distributed to the control component 3 and the control component 4 to achieve load balancing.

[0180] The process of the control components 3 and 4 cooperating to process the NVMe read command is similar to the process of processing the NVMe write command. Fig.12 As shown, the process of the control component 3 and the control component 4 cooperating to process the NVMe read command includes:

[0181] Process (1): The host interface 3 of the control component 3 receives the NVMe read command sent by the host, and sends the NVMe read command to the host command processing unit 3.

[0182] Process (2): The host command processing unit 3 parses the received NVMe read command, generates one or more storage commands according to the logical address range indicated by the NVMe read command, and sends the generated one or more storage commands to the storage command processing unit 3.

[0183] Process (3): The storage command processing unit 3 receives the storage command and queries the FTL table (such as Fig.12 The FTL table 3 shown in the figure determines the physical address corresponding to the logical address indicated by the storage command, and generates a media interface command according to the physical address. The storage command processing unit 3 distributes the media interface command to the media interface controller 3 or the media interface controller 4 according to the physical address indicated by the media interface command.

[0184] The storage command processing unit 3 determines the LUN corresponding to the physical address according to the physical address indicated by the media interface command, determines the NVM chip where the LUN is located, and then determines the media interface controller coupled to the NVM chip. The storage command processing unit 3 assigns the media interface commands corresponding to the NVMe write command indicating the same physical address and the media interface commands corresponding to the NVMe read command to the media interface controller of the same control component for processing. For example, when processing the NVMe write command, the storage command processing unit 3 assigns the media interface command with the physical address of PPA0 to the media interface controller 3 in the control component 3, and when reading the data corresponding to PPA0, it also assigns its corresponding media interface command to the media interface controller 4.

[0185] Process (4): The media interface controller 3 generates a corresponding storage medium access command based on the received media interface command, accesses the NVM chip coupled to the access control component 3 based on the storage medium access command, reads the corresponding data from the NVM chip, and then stores the read data in the DRAM. The media interface controller 4 generates a corresponding storage medium access command based on the received media interface command, accesses the NVM chip coupled to the access control component 4 based on the storage medium access command, reads the corresponding data from the NVM chip, and then stores the read data in the DRAM through the inter-chip communication link.

[0186] Process (5): The host command processing unit 3 moves the data stored in the DRAM by the media interface controller 3 and the media interface controller 4 to the host.

[0187] The host command processing unit 3 moves the data indicated by the NVMe read command from the cache of the storage device to the host, and in response to the completion of the NVMe read command processing, feeds back an NVMe read command processing completion message to the host through the host interface 3.

[0188] Figure 3-Figure 12 In the embodiment shown, only one control component (such as control component 1 or control component 3) is coupled to the host, and the other control components (such as control component 2 or control component 4) are not coupled to the host. In other optional embodiments, both control components are coupled to the host. The two control components can be coupled to the same host or to different hosts. Fig.13 As shown, the storage device includes a control component 5 and a control component 6. The control component 5 is coupled to the host 1 and receives IO commands (for example, including NVMe write commands and NVMe read commands) from the host 1. The control component 6 is coupled to the host 2 and receives IO commands (for example, including NVMe write commands and NVMe read commands) from the host 2. The IO command sent by the host 1 to the control component 5 and the IO command sent by the host 2 to the control component 6 are different IO commands. The control component 5 and the control component 6 independently process the IO commands received by each, or they can collaboratively process the received IO commands. The host 1 and the host 2 can be the same host or different hosts.

[0189] Optionally, there is no inter-chip communication link between the control component 5 and the control component 6. The control component 5 and the control component 6 independently process the IO commands received by each. For example, the control component 5 is coupled to the host 1 through the host interface 5, receives the IO commands sent by the host 1, and sends them to the host command processing unit 5. The host command processing unit 5 generates one or more storage commands according to the received IO commands, and sends the generated storage commands to the storage command processing unit 5. The storage command processing unit 5 generates one or more media interface commands according to the received storage commands, and sends the generated media interface commands to the media interface controller 5. The media interface controller 5 accesses the NVM chip coupled to the control component 5 according to the received media interface commands. The control component 6 is coupled to the host 2 through the host interface 6, receives the IO commands sent by the host 2, and sends them to the host command processing unit 6. The host command processing unit 6 generates one or more storage commands according to the received IO commands, and sends the generated storage commands to the storage command processing unit 6. The storage command processing unit 6 generates one or more media interface commands according to the received storage commands, and sends the generated media interface commands to the media interface controller 6. The media interface controller 6 accesses the NVM chip coupled to the control component 6 according to the received media interface command.

[0190] As an example, when there is no communication link between the control component 5 and the control component 6, and the control component 5 and the control component 6 work independently of each other, if the host 1 sends the NVMe write command 1 to the control component 5 through the host interface 5, the data indicated by the NVMe write command 1 is stored in the NVM chip coupled to the control component 5. When the host 1 wants to read the data indicated by the NVMe write command 1 from the NVM chip, the NVMe read command 1 corresponding to the NVMe write command 1 is sent to the control component 5 through the host interface 5, and the control component 5 processes the NVMe read command 1 and reads the data from the NVM chip coupled to the control component 5. When the host 1 sends the NVMe read command 1 corresponding to the NVMe write command 1 to the control component 6 through the host interface 6, the control component 6 feeds back information that the data reading failed to the host.

[0191] Optionally, the storage medium management unit 5 manages and maintains an FTL table 5, and the FTL table 5 records and manages a physical address corresponding to a logical address indicated by a storage command sent from the host command processing unit 5 to the storage command processing unit 5. The storage medium management unit 6 manages and maintains an FTL table 6, and the FTL table 6 records and manages a physical address corresponding to a logical address indicated by a storage command sent from the host command processing unit 6 to the storage command processing unit 6.

[0192] In the case where host 1 and host 2 are the same host, host 1 (or host 2) can send IO commands to control component 5 and control component 6 alternately, for example, host 1 (or host 2) sends M IO commands to control component 5 through host interface 5, and then sends N IO commands to control component 6 through host interface 6. Wherein, M and N are integers greater than or equal to 1. Optionally, host 1 (or host 2) does not send the same IO command to both control component 5 and control component 6. Still optionally, both FTL table 5 and FTL table 6 manage and maintain the physical addresses corresponding to the logical addresses in the entire logical address space, wherein the entire logical address space includes the logical address space corresponding to all NVM chips coupled by control component 5 and control component 6. Thus, host 1 (or host 2) can access data stored in any physical address managed by the FTL table through host interface 5 or host interface 6.

[0193] In some optional embodiments, there is an inter-chip communication link between the control component 5 and the control component 6, and the control component 5 and the control component 6 can collaboratively process the received IO commands through the inter-chip communication link. All functional units in the control component 5 participate in the work of processing IO commands. The functional units in the control component 6 can all participate in the work of processing IO commands, or can partially participate in the work of processing IO commands, for example, the host command processing unit in the control component 6 does not work, and other functional units work.

[0194] Optionally, the inter-chip communication link between the control component 5 and the control component 6 includes one or more of the following:

[0195] (1) Inter-chip communication link 1 formed by coupling storage command processing unit 6 and host command processing unit 5;

[0196] (2) an inter-chip communication link 2 formed by coupling the storage command processing unit 5 and the host command processing unit 6;

[0197] (3) an inter-chip communication link 3 formed by coupling the host interface 6 and the host command processing unit 5;

[0198] (4) The inter-chip communication link 4 formed by coupling the storage command processing unit 5 and the media interface controller 6.

[0199] Alternatively, if Fig.14AAs shown, the host command processing unit 5 in the control component 5 is coupled with the storage command processing unit 6 in the control component 6, and there is an inter-chip communication link 1 between the control component 5 and the control component 6. The control component 5 receives the IO command sent by the host 1 through the host interface 5, and sends the IO command to the host command processing unit 5. The host command processing unit 5 generates multiple storage commands according to the IO command, and the host command processing unit 5 can send the multiple storage commands corresponding to the IO command to the storage command unit 5 and / or the storage command processing unit 6. For example, the host command processing unit 5 can assign all the storage commands corresponding to the IO command to the storage command processing unit 5; or the host command processing unit 5 can assign all the storage commands corresponding to the IO command to the storage command processing unit 6; or, the host command processing unit 5 assigns a part of the storage commands corresponding to the IO command to the storage command processing unit 5, and assigns another part of the storage commands to the storage command processing unit 6 through the inter-chip communication link 1.

[0200] like Fig. 14B As shown, the host command processing unit 6 in the control component 6 is coupled to the storage command processing unit 5 in the control component 5, and there is an inter-chip communication link 2 between the control component 5 and the control component 6. The control component 6 receives the IO command sent by the host 2 through the host interface 6, and sends the IO command to the host command processing unit 6. The host command processing unit 6 generates a plurality of storage commands according to the IO command, and the host command processing unit 6 can send the plurality of storage commands corresponding to the IO command to the storage command unit 5 and / or the storage command processing unit 6. For example, the host command processing unit 6 can assign all the storage commands corresponding to the IO command to the storage command processing unit 5; or the host command processing unit 6 can assign all the storage commands corresponding to the IO command to the storage command processing unit 6; or, the host command processing unit 6 assigns a part of the storage commands corresponding to the IO command to the storage command processing unit 5, and assigns another part of the storage commands to the storage command processing unit 6 through the communication link between the host command processing unit 6 and the storage processing unit 6.

[0201] like Fig. 14CAs shown, the host command processing unit 5 in the control component 5 is coupled with the storage command processing unit 6 in the control component 6, and the host command processing unit 6 in the control component 6 is coupled with the storage command processing unit 5 in the control component 5, and there are both an inter-chip communication link 1 and an inter-chip communication link 2 between the control component 5 and the control component 6. The storage command processing unit 6 in the control component 6 is coupled with the host command processing unit 5 in the control component 5, and the storage command processing unit 6 can receive a storage command sent by the host command processing unit 5. The storage command processing unit 5 is coupled with the host command processing unit 6, and the storage command processing unit 5 can receive a storage command sent by the host command processing unit 6. For example, the control component 5 receives an IO command 1 through the host interface 5, and sends the IO command 1 to the host command processing unit 5. The host command processing unit 5 generates a plurality of storage commands according to the IO command 1, allocates a part of the storage commands to the storage command processing unit 5, and allocates another part of the storage commands to the storage command processing unit 6 through the inter-chip communication link 1. The control component 6 receives an IO command 2 through the host interface 6, and sends the IO command 2 to the host command processing unit 6. The host command processing unit 6 generates multiple storage commands according to the IO command 2, and allocates a part of the storage commands to the storage command processing unit 5, and allocates another part of the storage commands to the storage command processing unit 6 through the inter-chip communication link 2. Among them, the host command processing unit 5 and the host command processing unit 6 can allocate the generated storage commands to the storage command processing unit 5 and the storage command processing unit 6 according to the logical address indicated by the storage command. For example, Fig.14A , Fig. 14B as well as Fig. 14C The host command processing unit 5 and the host command processing unit 6 distribute the storage command corresponding to the received IO command to the storage command processing units (storage command processing unit 5 and storage command processing unit 6) in the two control components for collaborative processing. The distribution method can be referred to Figure 3-Figure 7 The embodiments shown will not be described in detail here.

[0202] Optionally, the host command processing unit 5 may also assign all storage commands generated according to the IO command 1 to the storage command processing unit 5 or the storage command processing unit 6. The host command processing unit 6 may also assign all storage commands generated according to the IO command 2 to the storage command processing unit 5 or the storage command processing unit 6. The host command processing unit 5 may assign all the multiple storage commands generated according to the IO command 1 to the storage command processing unit 6, so that the control component 6 accesses the NVM according to the IO command received by the control component 5. Thus, in the event that the storage command processing unit 5 and / or the media interface controller 5 in the control component 5 fail, the IO commands sent by the host may be processed by the storage command processing unit 6 and the media interface controller 6 in the control component 6. Similarly, the host command processing unit 6 may assign all the multiple storage commands generated according to the IO command 2 to the storage command processing unit 5, so that the control component 5 accesses the NVM according to the IO command received by the control component 6.

[0203] like Fig.14D As shown, the host interface 6 in the control component 6 is coupled to the host command processing unit 5 in the control component 5, and there is an inter-chip communication link 3 between the control component 5 and the control component 6. The control component 6 can independently process the IO commands sent by the host 2, and can also distribute all or part of the IO commands sent by the host 2 to the control component 5 through the inter-chip communication link 3.

[0204] like Fig.14E As shown, the storage command processing unit 5 in the control component 5 is coupled to the media interface controller 6 in the control component 6, and there is an inter-chip communication link 4 between the control component 5 and the control component 6. The storage command processing unit 5 can distribute the generated media interface command to the media interface controller 6 through the inter-chip communication link 4.

[0205] In some other optional embodiments, when there is an inter-chip communication link between the control component 5 and the control component 6, all functional units in the control component 5 participate in the work of processing the IO command. Some functional units in the control component 6 participate in the work of processing the IO command, and some functional units do not work. Fig.15 As shown, the host command processing unit 6 in the control component 6 does not work. Fig.16 As shown, the host command processing unit 6, the storage command processing unit 6 and the storage medium management unit 6 in the control component 6 are not working.

[0206] exist Fig.15In the illustrated embodiment, the host interface 6 and the storage command processing unit 6 in the control component 6 are coupled to the host command processing unit 5 in the control component 5, and there are both an inter-chip communication link 1 and an inter-chip communication link 3 between the control component 5 and the control component 6. The IO commands (including NVMe write commands and NVMe read commands) received by the control component 5 through the host interface 5 and the IO commands (including NVMe write commands and NVMe read commands) received by the control component 6 through the host interface 6 are sent to the host command processing unit 5. The host command processing unit 5 generates one or more storage commands based on the received IO commands, and assigns the one or more storage commands to the storage command processing unit 5 and / or the storage command processing unit 6. For example, the strategy for the host command processing unit 5 to assign storage commands to the storage command processing unit 5 and the storage command processing unit 6 can refer to Figure 3-Figure 7 In the case where the host 1 and the host 2 are the same host, for example, the control component 5 and the control component 6 are coupled to the host 1, since the host interface 5 and the host interface 6 are coupled to the host 1, the processing completion message corresponding to the IO command received through the host interface 5 can be fed back to the host 1 through the host interface 5, and can also be fed back to the host 1 through the host interface 6, and the processing completion message corresponding to the IO command received through the host interface 6 can be fed back to the host through the host interface 6, and can also be fed back to the host through the host interface 5.

[0207] exist Fig.16 In the illustrated embodiment, the host interface 6 in the control component 6 is coupled to the host command processing unit 5 in the control component 5, the media interface controller 6 is coupled to the storage command processing unit 5, and there are both an inter-chip communication link 3 and an inter-chip communication link 4 between the control component 5 and the control component 6. The IO commands (including NVMe write commands and NVMe read commands) received by the control component 5 through the host interface 5 and the IO commands (including NVMe write commands and NVMe read commands) received by the control component 6 through the host interface 6 are all sent to the host command processing unit 5. The host command processing unit 5 generates one or more storage commands based on the received IO commands, and sends the generated storage commands to the storage command processing unit 5. The storage command processing unit 5 generates one or more media interface commands based on the received storage commands, and distributes the generated media interface commands to the media interface controller 5 and the media interface controller 6. Among them, the storage command processing unit 5 can distribute the media interface commands to the media interface controller 5 and the media interface controller 6 according to the physical address indicated by the media interface command. For example, the strategy for the storage command processing unit 5 to distribute the media interface commands according to the physical address indicated by the media interface command can refer to Figure 8-Figure 12 , this application will not be elaborated here.

[0208] Depend on Figure 2-Figure 16As can be seen from the illustrated embodiments, the storage device provided in the embodiments of the present application combines two or more control components to collaboratively process IO commands from a host, thereby providing a large-capacity and high-performance storage device while providing a limited number of flash memory channels provided by the control components.

[0209] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A storage device, characterized in that: including a master control component, a slave control component and an inter-chip communication link; The main control component includes a first host interface, a first host command processing unit, a first storage command processing unit, a first storage medium management unit and a first medium interface controller; The slave control component includes a second host interface, a second host command processing unit, a second storage command processing unit, a second storage medium management unit and a second medium interface controller; The master control component and the slave control component communicate via the inter-chip communication link; The first host interface is coupled to a host; the master control component and the slave control component collaboratively process IO commands received from the first host interface through the inter-chip communication link.

2. The storage device according to claim 1, characterized in that The inter-chip communication link couples the second media interface controller to the first storage command processing unit in the first control component.

3. The storage device according to claim 1 or 2, characterized in that: The main control component receives an IO command sent by the host through the first host interface, and sends the IO command to the first host command processing unit; The first host command processing unit generates one or more storage commands according to the IO command, and sends the one or more storage commands to the first storage command processing unit; The first storage command processing unit generates one or more media interface commands according to the one or more storage commands, and distributes the media interface commands to the first media interface controller and the second media interface controller.

4. The storage device according to claim 3, characterized in that: If the IO command is an NVMe write command, the first host command processing unit generates one or more first storage commands according to the NVMe write command, the first storage command processing unit allocates physical addresses to the logical addresses indicated by the one or more first storage commands according to the page stripe, and generates one or more first media interface commands according to the physical addresses corresponding to the logical addresses indicated by the one or more first storage commands.

5. The storage device according to claim 4, characterized in that: The page stripe is composed of physical pages from logical units on all NVM chips coupled to the master control unit and logical units on all NVM chips coupled to the slave control unit.

6. The storage device according to claim 4, characterized in that: The page stripe is composed of physical pages from logic units on a portion of the NVM chip coupled to the master control unit and logic units on a portion of the NVM chip coupled to the slave control unit.

7. The storage device according to any one of claims 4 to 6, characterized in that: In response to receiving a first storage command, the first storage command processing unit allocates a physical address for a logical address indicated by the first storage command from unallocated physical addresses in the first page stripe if the physical addresses in the first page stripe have not been fully allocated; If the physical addresses in the first page stripe are all allocated, a physical address is allocated from the physical addresses in the second page stripe to the logical address indicated by the first storage command; the second page stripe and the first page stripe are different page stripes.

8. The storage device according to claim 7, characterized in that: Determining the expected number of storage commands corresponding to the first page stripe according to the storage space capacity corresponding to the first page stripe and the storage unit capacity indicated by the logical address; If the number of storage commands currently allocating physical addresses from the first page stripe is less than the expected number, it indicates that the physical addresses in the first page stripe have not been fully allocated; If the number of storage commands that currently allocate physical addresses from the first page stripe is equal to the expected number, it indicates that all physical addresses in the first page stripe are allocated.

9. The storage device according to any one of claims 3 to 8, characterized in that: If the IO command is an NVMe read command, the first host command processing unit generates one or more second storage commands according to the NVMe read command; the first storage command processing unit determines the physical address corresponding to the logical address indicated by the second storage command by querying the FTL table, and generates one or more second media interface commands according to the physical address.

10. The storage device according to any one of claims 1 to 9, characterized in that: If the IO command is an NVMe write command, the first host command processing unit moves the data indicated by the NVMe write command from the host to the cache of the storage device; And in response to the NVMe write command processing being completed, sending an NVMe write command processing completion message to the host through the first host interface; If the IO command is an NVMe read command, the first host command processing unit moves the data indicated by the NVMe read command from the cache of the storage device to the host; And in response to the NVMe read command processing being completed, an NVMe read command processing completion message is sent to the host through the first host interface.

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