Apparatus and method for verifying performance of combined virtual component

Abstract

An apparatus and method for verifying performance of a combined virtual component is disclosed. An apparatus for verifying performance of a combined virtual component according to an exemplary embodiment of the present disclosure includes a memory and a processor connected to the memory, where the processor determines a degree of completion of a combined model by comparing complex mode indicator function (CMIF) data of the combined model with a preset criterion, the combined model is formed by virtually combining a plurality of components. The apparatus and method for verifying performance of a combined virtual component according to the present disclosure may verify in advance a degree of completion of a combined model created by virtually combining two or more vehicle components.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to an apparatus and method for verifying the performance of a combined virtual component, and more particularly, to an apparatus and method for verifying the performance of a combined virtual component, which is capable of pre-verifying the degree of completeness of a combined model created by virtually combining two or more vehicle components. Background Art

[0002] In general, dynamic sub-structuring (DS) and frequency response function (FRF)-based sub-structuring (FBS) are techniques used to predict noise and vibration problems that may occur when combining dynamic systems. DS and FBS can virtually assemble constituent elements provided in different physical locations. Of course, if two or more components can be easily and physically (virtually) assembled, this technique is not needed. This technique is mainly used in cases where components are not easy to combine.

[0003] However, even in the case where a combination model is configured, there is no standard, tool, or system to intuitively determine the accuracy of the combination model for each frequency, combination position, or degree of freedom.

[0004] As a current method for determining the accuracy and completeness of a virtual component combination model, there is a method of plotting the difference between noise prediction values ​​and vibration prediction values ​​of the virtual combination model and actual noise values ​​and actual vibration values ​​of an actually combined finished product in a graph and visually identifying the graph.

[0005] However, in the related art, the method of determining the completion of a virtual component combination model has the disadvantage that in order to obtain comparative data for verifying the completion, two or more types of components need to be actually combined, many sensors, measuring instruments, evaluation equipment, etc. required for evaluating the completion need to be prepared, and direct evaluation requires time and labor.

[0006] The background technology of the present disclosure is disclosed in the Korean patent application No. 10-1965649 (published on April 10, 2019, and the invention name is "Method for analyzing torsion of a vehicle body component module"). Summary of the invention

[0007] Various embodiments relate to an apparatus and method for verifying performance of combining virtual components, which can pre-verify the degree of completion of a combined model created by virtually combining two or more vehicle components.

[0008] In one embodiment, an apparatus for verifying the performance of a combined virtual component includes: a memory; and a processor connected to the memory, wherein the processor determines the completeness of the combined model by comparing complex mode indicator function (CMIF) data of the combined model with a preset guideline, wherein the combined model is formed by virtually combining multiple components.

[0009] According to the present disclosure, the processor may create a combined model by using at least one of FRF-based sub-structuring (FBS), dynamic sub-structuring (DS), and blocked force.

[0010] According to the present disclosure, the processor can compare the CMIF data of the combined model with the criteria and determine whether the CMIF data of the combined model meets the completion determination condition. When the completion determination condition is met, the processor can determine that the combined model has reached the completion degree, and when the completion determination condition is not met, the processor can determine that the combined model has not reached the completion degree.

[0011] According to the present disclosure, the criterion may include a CMIF upper limit value and a CMIF lower limit value for each frequency set by a user, and the completion determination condition may include: a first condition, wherein the peak value of the CMIF data of the combined model exists in a range equal to or greater than the CMIF upper limit value of each frequency; and a second condition, wherein the CMIF data of the combined model does not exist in a range equal to or less than the CMIF lower limit value of each frequency, when the CMIF data of the combined model satisfies the first and second conditions, the processor may determine that the combined model has reached the completion, and when the CMIF data of the combined model does not satisfy at least one of the first condition and the second condition, the processor may determine that the combined model has not reached the completion.

[0012] According to the present disclosure, the criterion may include the CMIF first mode result of the actual combined component and the CMIF final mode result of the actual combined component, and the completion determination condition may include: a first condition, in which the peak value of the CMIF data of the combined model appears in a range equal to or greater than the CMIF first mode result of the actual combined component; and a second condition, in which the CMIF data of the combined model does not exist in a range equal to or less than the CMIF final mode result of the actual combined component. When the CMIF data of the combined model satisfies the first condition and the second condition, the processor may determine that the combined model has reached the completion, and when the CMIF data of the combined model does not satisfy at least one of the first condition and the second condition, the processor may determine that the combined model has not reached the completion.

[0013] According to the present disclosure, the processor may calculate a correlation by comparing the FRF response magnitude of each degree of freedom of each combined part of the combined model with a criterion, and create a performance verification graph by using the correlation.

[0014] According to the present disclosure, the performance verification graph may indicate the degree of correlation for each frequency, each combination point, and each of the six degrees of freedom, and the degree of correlation may be indicated by a value and a color.

[0015] In another embodiment, a method for verifying the performance of a combined virtual component includes: obtaining, by a processor, complex modal indicator function (CMIF) data of a combined model created by virtually combining multiple components; and determining, by the processor, the completeness of the combined model by comparing the CMIF data with preset criteria.

[0016] According to the present disclosure, when determining the completion of a combination model, the processor may compare the CMIF data of the combination model with the criteria and determine whether the CMIF data of the combination model satisfies a completion determination condition. When the completion determination condition is met, the processor may determine that the combination model has reached the completion, and when the completion determination condition is not met, the processor may determine that the combination model has not reached the completion.

[0017] According to the present disclosure, the method may further include: after determining the degree of completion of the combined model, calculating, by the processor, a correlation by comparing the FRF response amplitude of each degree of freedom of each combined part of the combined model with a criterion, and creating a performance verification graph by using the correlation.

[0018] According to the present disclosure, the degree of completion of a combined model created by virtually combining two or more vehicle components can be verified in advance.

[0019] Furthermore, for each frequency band, each combination point position, and each degree of freedom (6-DoF), the present disclosure provides a portion where the degree of completion of the combination model is reduced and thus requires improvement, thereby easily identifying improvement points.

[0020] Furthermore, according to the present disclosure, by combining virtual components using DS, FBS, etc., subjective judgment of engineers is not involved, so that everyone does not have deviations.

[0021] Furthermore, according to the present disclosure, the degree of completeness of the combined model is determined by comparing the CMIF data of the combined model with criteria, thereby reducing the amount of time required to analyze the combined model.

[0022] Furthermore, according to the present disclosure, an apparatus for verifying the performance of a combined virtual component is used in the form of a toolbox, so that the degree of completion of a combined model can be easily checked.

[0023] Meanwhile, the effects of the present disclosure are not limited to the above-mentioned effects, and various effects may be included within a range that is obvious to those skilled in the art according to the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram schematically illustrating an apparatus for verifying performance of a combined virtual component according to an embodiment of the present disclosure.

[0025] Figure 2A and 2B is an exemplary diagram for explaining a method of determining a degree of completion of a combined model by using a criterion set by a user according to an embodiment of the present disclosure.

[0026] Figure 3A and 3B is an exemplary diagram for explaining a method of determining a degree of completion of a combination model by using evaluation result data generated by actual component combination according to an embodiment of the present disclosure.

[0027] Figure 4A and 4B is an example diagram for explaining a performance verification diagram according to an embodiment of the present disclosure.

[0028] Figure 5 is a flowchart for explaining a method of verifying performance of a combined virtual component according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The components described in the example embodiments may be implemented by hardware components including, for example, at least one digital signal processor (DSP), a processor, a controller, an application-specific integrated circuit (ASIC), a programmable logic element such as a field-programmable gate array (FPGA), other electronic devices, or a combination thereof. At least some of the functions or processes described in the example embodiments may be implemented by software, and the software may be recorded on a recording medium. The components, functions, and processes described in the example embodiments may be implemented by a combination of hardware and software.

[0030] The method according to the example embodiment may be implemented as a program executable by a computer, and may be implemented as various recording media such as a magnetic storage medium, an optical reading medium, and a digital storage medium.

[0031] The various techniques described herein may be implemented as digital electronic circuits, or as computer hardware, firmware, software, or a combination thereof. These techniques may be implemented as a computer program product, i.e., a computer program tangibly contained in an information carrier, for example, a computer program contained in a machine-readable storage device (e.g., a computer-readable medium), or a computer program contained in a propagation signal, which is used for processing by the operation of a data processing device (e.g., a programmable processor, a computer, or multiple computers), or for controlling the operation of a data processing device. The computer program may be written in any form of programming language, including a compiled language or an interpreted language, and may be deployed in any form including: a stand-alone program or module, a component, a subroutine, or other units suitable for a computing environment. The computer program may be deployed to execute on one or more computers at one location, or distributed at multiple locations and interconnected by a communication network.

[0032] For example, processors suitable for executing computer programs include general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The elements of a computer may include at least one processor that executes instructions and one or more storage devices that store instructions and data. Generally speaking, a computer will also include or be connected to receive data from one or more mass storage devices, transfer data to one or more mass storage devices, or perform these two operations on one or more mass storage devices to store data, such as magnetic disks, magneto-optical disks, or optical disks. Examples of information carriers suitable for containing computer program instructions and data include semiconductor storage devices, for example, magnetic media such as hard disks, floppy disks and magnetic tapes; optical media such as compact disk read only memory (CD-ROM), digital video disk (DVD), etc.; and magneto-optical media such as optical floppy disks, read only memory (ROM), random access memory (RAM), flash memory, erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM) and any other known computer readable medium. The processor and memory may be supplemented by or integrated into special purpose logic circuitry.

[0033] The processor can run an operating system (OS) and one or more software applications running on the OS. The processor device can also access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, the description of the processor device is used as a singular; however, those skilled in the art will appreciate that the processor device may include multiple processing elements and / or multiple types of processing elements. For example, the processor device may include multiple processors or a processor and a controller. In addition, different processing configurations are possible, such as parallel processors.

[0034] Additionally, non-transitory computer readable media may be any available media that can be accessed by a computer and may include computer storage media and transmission media.

[0035] This specification includes many details of specific embodiments, but it should be understood that these details do not limit any invention or the content claimed in the specification, but rather describe the features of specific example embodiments. Features described in the specification in the context of various exemplary embodiments can be implemented as a combination in a single exemplary embodiment. Conversely, various features described in the specification in the context of a single exemplary embodiment can be implemented in multiple exemplary embodiments individually or in appropriate sub-combinations. In addition, these features can operate in a specific combination and can initially be described as required in the combination, but in some cases, one or more features can be excluded from the required combination, and the required combination can be changed to a sub-combination or a modification of the sub-combination.

[0036] Similarly, even if operations are described in a particular order in the accompanying drawings, it should not be understood that the operations need to be performed in a particular order or sequence to obtain the desired results, or that all operations need to be performed. In certain circumstances, multitasking and parallel processing may be advantageous. In addition, it should not be understood that the various device components in the above exemplary embodiments need to be separated in all exemplary embodiments, and it should be understood that the above program components and devices can be combined into a single software product, or can be packaged in multiple software products.

[0037] It should be understood that the exemplary embodiments disclosed herein are merely illustrative and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of the technical solutions and their equivalents.

[0038] Hereinafter, with reference to the accompanying drawings, embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0039] In the following description of the embodiments of the present disclosure, detailed descriptions of known functions and configurations incorporated herein will be omitted when the subject matter of the present disclosure may become rather unclear. Parts of the drawings that are not related to the description of the present disclosure are omitted, and the same parts are represented by similar reference numerals.

[0040] In the present disclosure, components that are distinguished from each other are intended to clearly illustrate each feature. However, this does not necessarily mean that the components are separated. That is, multiple components can be integrated into one hardware or software unit, or a single component can be distributed into multiple hardware or software units. Therefore, unless otherwise stated, such integrated or distributed embodiments are also included in the scope of the present disclosure.

[0041] In the present disclosure, the components described in various embodiments are not necessarily necessary components, and some may be optional components. Therefore, embodiments consisting of a subset of the components described in one embodiment are also included in the scope of the present disclosure. In addition, embodiments including other components in addition to the components described in various embodiments are also included in the scope of the present disclosure.

[0042] Hereinafter, with reference to the accompanying drawings, embodiments of the present disclosure will be described in detail so that those skilled in the art can easily implement the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0043] In the following description of the embodiments of the present disclosure, detailed descriptions of known functions and configurations incorporated herein will be omitted when the subject matter of the present disclosure may become rather unclear. Parts of the drawings that are not related to the description of the present disclosure are omitted, and the same parts are represented by similar reference numerals.

[0044] In the present disclosure, when a component is referred to as being "linked," "coupled," or "connected" to another component, it should be understood that not only a direct connection relationship but also an indirect connection relationship through an intermediate component may be included. In addition, when a component is referred to as "including" or "having" another component, it may mean that the other component is also included, rather than excluded, unless there is a clear description to the contrary.

[0045] In the present disclosure, the terms first, second, etc. are used only for the purpose of distinguishing one component from another component, and do not limit the order or importance of the components, etc., unless otherwise explicitly stated. Therefore, within the scope of the present disclosure, a first component in one exemplary embodiment may be referred to as a second component in another embodiment, and similarly, a second component in one exemplary embodiment may be referred to as a first component.

[0046] In the present disclosure, components that are distinguished from each other are intended to clearly illustrate each feature. However, this does not necessarily mean that the components are separated. That is, multiple components can be integrated into one hardware or software unit, or a single component can be distributed into multiple hardware or software units. Therefore, unless otherwise stated, such integrated or distributed embodiments are also included in the scope of the present disclosure.

[0047] In the present disclosure, the components described in various embodiments are not necessarily necessary components, and some may be optional components. Therefore, an embodiment consisting of a subset of the components described in one embodiment is also included in the scope of the present disclosure. In addition, in addition to the components described in various embodiments, exemplary embodiments including other components are also included in the scope of the present disclosure.

[0048] Hereinafter, an apparatus and method for verifying the performance of a combined virtual component will be described with reference to the accompanying drawings through various exemplary embodiments. In this document, for the sake of clarity and convenience of description, the thickness of the lines shown in the accompanying drawings, the size of the constituent elements, etc. may be exaggerated. In addition, the terms used below are defined in consideration of their functions in the present disclosure and may vary according to the intention of the user or operator or common practice. Therefore, these terms should be defined based on the entire contents of this specification.

[0049] For example, the configuration described in this specification may be implemented as a method or process, a device, a software program, a data stream or a signal. Even if a single form of implementation is described (e.g., only a method is described), the described features may also be implemented in other forms (e.g., a device or program). The device may be implemented as suitable hardware, software, firmware, etc. For example, the method may be implemented by a device such as a processor, which generally refers to a processing device including a computer, a microprocessor, an integrated circuit, a programmable logic device, etc. Processors also include communication devices such as computers, cellular phones, portable / personal information terminals (personal digital assistants (PDAs)) and other devices that facilitate information communication with end users.

[0050] Figure 1 is a block diagram schematically illustrating an apparatus for verifying the performance of a combined virtual component according to an embodiment of the present disclosure, Figure 2A and 2B is an exemplary diagram for explaining a method of determining a degree of completion of a combined model by using a criterion set by a user according to an embodiment of the present disclosure, Figure 3A and 3B is an exemplary diagram for explaining a method of determining the degree of completion of a combination model by using evaluation result data generated by actual component combination according to an embodiment of the present disclosure, Figure 4A and 4B is an example diagram for explaining a performance verification diagram according to an embodiment of the present disclosure.

[0051] refer to Figure 1 According to an embodiment of the present disclosure, the apparatus 100 for verifying the performance of a combined virtual component includes a memory 110 , an input module 120 , an output module 130 , and a processor 140 .

[0052] The memory 110 is configured to store data related to the operation of the device 100 for verifying the performance of the combined virtual component. In this case, a known storage medium can be used as the memory 110. For example, any one or more known storage media, such as ROM, PROM, EPROM, EEPROM and RAM, can be used. Specifically, the memory 110 can store a program (application or applet) that can create a combined model by virtually combining multiple components, a program (application or applet) that can determine the degree of completion of the combined model by using the CMIF data of the combined model, and a program (application or applet) that can create a performance verification diagram related to the combined part of the combined model. If necessary, the processor 140 can select multiple stored information.

[0053] The input module 120 may receive input for controlling the device 100 to verify the performance of the combined virtual component. The input module 120 may detect a criterion input for determining the degree of completion of the combined model. For example, the input module 120 may receive a CMIF upper limit value and a CMIF lower limit value regarding frequency and six degrees of freedom.

[0054] The output module 130 is configured to display various information related to the operation of the apparatus 100 for verifying the performance of a combined virtual component. Specifically, when executing the virtual component combination performance verification program (application), the output module 130 can display a performance verification graph and whether the completion of the combination model is achieved.

[0055] The output module 130 may also operate as the input module 120 for receiving information from a user. For example, the output module 130 may be configured as any of various types of devices such as a touch screen, a display, a holographic device, and a projector.

[0056] The processor 140 may be configured to control the overall operation of the apparatus 100 for verifying the performance of a combined virtual component, and configured to be an integrated circuit, a system on a chip, or a mobile AP.

[0057] The processor 140 may control the overall operating state of the apparatus 100 for verifying the performance of the combined virtual component. The processor 140 may refer to a data processing device embedded in hardware and having, for example, a circuit that is physically constructed to execute functions represented by codes or instructions included in a program. Examples of data processing devices embedded in hardware may include processing devices such as a microprocessor, a central processing unit (CPU), a processor core, a multiprocessor, an application-specific integrated circuit (ASIC), or a field programmable gate array (FPGA), but the scope of the present disclosure is not limited thereto.

[0058] The processor 140 may determine the degree of completion of the combined model by comparing complex modal indicator function (CMIF) data of the combined model created by virtually combining a plurality of components with a preset criterion, and create a performance verification graph as the degree of completion of the combined model.

[0059] Hereinafter, the operation of the processor 140 will be described in detail.

[0060] The processor 140 may create a combined model by virtually combining a plurality of components. In this case, the processor 140 may create a combined model by virtually combining a plurality of components using FRF-based substructuring (FBS), dynamic substructuring (DS), blocking forces, etc. In this case, FBS may be a technique for combining a plurality of components in the frequency domain by ensuring an FRE matrix of a point at which the components of each unit are intended to be combined. DS may be a technique for modeling the dynamics of a machine system by constituent elements or underlying structures. Blocking forces may be a technique for converting vibrations in operation generated from a source into forces at a combination point.

[0061] When creating the combined model, the processor 140 may obtain complex mode indicator function (CMIF) data of the combined model. The CMIF data may be data created based on a singular value decomposition (SVD) of an FRF function so as to identify all modes of the combined model. That is, the CMIF data may be a graph that identifies the magnitude of the frequencies of all modes of the combined model and lists the modes sequentially starting from the mode with the greatest influence.

[0062] When the CMIF data of the combination model is obtained, the processor 140 can compare the CMIF data of the combination model with the preset criteria and determine the completion of the combination model. In this case, the criteria may include the CMIF upper limit value and the CMIF lower limit value of each frequency set by the user. In addition, the criteria may be the evaluation result data (CMIF data) of the actual combination component. The completion of the combination model shows how the components are combined. The completion may be achieved when the components are combined well, and the completion may not be achieved when the components are not combined correctly.

[0063] The processor 140 may compare the CMIF data of the combined model with the criteria and determine whether the CMIF data of the combined model satisfies the completion determination condition. In this case, the completion determination condition may include: a first condition in which the peak value of the CMIF data of the combined model appears within a range equal to or greater than the CMIF upper limit value of each frequency set by the user (or the CMIF first mode result of the actual combined component); and a second condition in which the CMIF data of the combined model does not exist within a range equal to or less than the CMIF lower limit value of each frequency set by the user (or the CMIF final mode result of the actual combined component).

[0064] Therefore, when the CMIF data of the combined model can satisfy the first and second conditions, the processor 140 can determine that the combined model has reached the completion degree. In addition, when the CMIF data of the combined model does not satisfy the first condition or the second condition, the processor 140 can determine that the combined model has not reached the completion degree.

[0065] For example, a method of determining the degree of completion of a combined model by using a criterion set by a user will be described with reference to FIG. 2 .

[0066] Figure 2A The completion degree of the combined model is shown. In this case, the peak of the CMIF graph of the combined model formed by virtually combining component A and component B exists in a range equal to or greater than the CMIF upper limit value of each frequency, and the CMIF data of the CMIF graph of the combined model formed by virtually combining component A and component B does not exist in a range equal to or less than the CMIF lower limit value of each frequency. Therefore, the processor 140 can determine that the combined model formed by virtually combining component A and component B has reached the completion degree.

[0067] Figure 2BIt is explained that the completion of the combined model has not been achieved. In this case, the peak of the CMIF graph of the combined model formed by virtually combining component A and component B does not exist in a range equal to or greater than the CMIF upper limit value of each frequency, and the CMIF data of the CMIF graph of the combined model formed by virtually combining component A and component B exists in a range equal to or less than the CMIF lower limit value of each frequency. Therefore, the processor 140 can determine that the combined model formed by virtually combining component A and component B has not reached the completion.

[0068] Next, a method of determining the degree of completion of a combination model in a case where evaluation result data generated by actual component combination is set as a criterion will be described with reference to FIG. 3 . Figure 3A It is shown that the completion of the combined model has been achieved. In this case, the peak of the CMIF graph of the combined model formed by virtually combining component A and component B appears in a range equal to or greater than the CMIF first mode result of the actual combined component, and the CMIF data of the CMIF graph of the combined model formed by virtually combining component A and component B does not appear in a range equal to or less than the CMIF final mode result of the actual combined component. Therefore, the processor 140 can determine that the combined model formed by virtually combining component A and component B has reached the completion.

[0069] Figure 3B It is shown that the degree of completion of the combined model has not been reached. In this case, the peak of the CMIF graph of the combined model formed by virtually combining component A and component B does not exist in a range equal to or greater than the CMIF first mode result of the actual combined components, and the CMIF data of the CMIF graph of the combined model formed by virtually combining component A and component B exists in a range equal to or less than the CMIF final mode result of the actual combined components. Therefore, the processor 140 can determine that the combined model formed by virtually combining component A and component B has not reached the degree of completion.

[0070] When determining whether the degree of completion of the combined model is reached, the processor 140 can calculate the correlation by comparing the FRF response amplitude of each degree of freedom of each combined part of the combined model with the criterion, and create a performance verification diagram by using the correlation. In this case, the processor 140 can calculate the difference between the CMIF upper limit value set to the criterion (or the CMIF first mode result of the actual combined component) and the FRF response amplitude of each degree of freedom of each combined part, and calculate the correlation based on the calculated difference. Thereafter, the processor 140 can create a performance verification diagram indicating the correlation for each frequency, each combination point, and each of the six degrees of freedom, and output the correlation through the output module 130. In this case, the processor 140 can change the color according to the correlation. Therefore, the processor 140 can display the correlation by the color and value in the performance verification diagram.

[0071] For example, as shown in FIG. 4 , processor 140 may create a performance verification graph.

[0072] Figure 4A A performance verification diagram is shown when the completion of the combination model is reached. The performance verification diagram may indicate the correlation according to the six degrees of freedom at combination point 1, combination point 2, combination point 3, and combination point 4 within the frequency range (250 to 800). In this case, the correlation is indicated by similar colors, which may indicate that combination point 1, combination point 2, combination point 3, and combination point 4 are well combined within the frequency range (250 to 800).

[0073] Figure 4B A performance verification diagram is shown in which the completion of the combination model is not achieved. The performance verification diagram may indicate correlation according to six degrees of freedom at combination point 1, combination point 2, combination point 3, and combination point 4 within the frequency range (250 to 800). In this case, the correlation in region A is indicated by a darker color than the correlation color of other regions, and region A may indicate that combination point 1, combination point 2, combination point 3, and combination point 4 are not well combined within the frequency range (250 to 800).

[0074] The processor 140 may compare the FRF response magnitude for each degree of freedom with the reference FRF data and output a correlation, thereby providing the combined portion that needs improvement for each frequency band, each combination point location, and each degree of freedom (6-DoF).

[0075] All or at least a portion of the configuration of the apparatus 100 for verifying the performance of the combined virtual component configured as described above may be implemented in the form of a hardware module or a software module, or in the form of a combination of a hardware module and a software module. In this case, the software module may be understood as an instruction executed by the processor 140, which performs calculations in the apparatus 100 to verify the performance of the combined virtual component. The instruction may be in a form installed in the memory 110 of the apparatus 100, and is used to verify the performance of the combined virtual component.

[0076] Figure 5 is a flowchart for explaining a method of verifying performance of a combined virtual component according to an embodiment of the present disclosure.

[0077] Reference Figure 5 , the processor 140 creates a combined model by virtually combining the plurality of components (S502). In this case, the processor 140 may create a combined model by virtually combining the plurality of components using FRF-based substructuring (FBS), dynamic substructuring (DS), blocking forces, and the like.

[0078] When executing step S502, the processor 140 acquires CMIF data of the combined model (S504). The CMIF data may be data created based on singular value decomposition (SVD) of the FRF function in order to identify all modes of the combined model.

[0079] When executing step S504, the processor 140 compares the CMIF data of the combined model with the preset criteria (S506), and determines whether the CMIF data of the combined model satisfies the completion determination condition (S508). In this case, the completion determination condition may include: a first condition, in which the peak value of the CMIF data of the combined model appears in a range equal to or greater than the CMIF upper limit value of each frequency set by the user (or the CMIF first mode result of the actual combined component); and a second condition, in which the CMIF data of the combined model does not exist in a range equal to or less than the CMIF lower limit value of each frequency set by the user (or the CMIF final mode result of the actual combined component).

[0080] Therefore, when the CMIF data of the combined model can satisfy the first and second conditions, the processor 140 can determine that the combined model has reached the completion degree. In addition, when the CMIF data of the combined model does not satisfy the first condition or the second condition, the processor 140 can determine that the combined model has not reached the completion degree.

[0081] When the determination result in step S508 indicates that the CMIF data of the combined model satisfies the degree of completion determination condition, the processor 140 determines that the combined model has reached the degree of completion (S510).

[0082] When step S510 is executed, the processor 140 calculates the correlation by comparing the FRF response amplitude of each degree of freedom of each combined part of the combined model with the criterion (S512), and creates a performance verification diagram (S514) by using the calculated correlation. In this case, the processor 140 can calculate the correlation based on the difference between the CMIF upper limit value of each frequency set as the criterion (or the CMIF first mode result of the actual combined component) and the FRF response amplitude of each degree of freedom of each combined part. Thereafter, the processor 140 can create a performance verification diagram indicating the correlation of each frequency, each combination point, and each degree of freedom in the six degrees of freedom, and output the created performance verification diagram through the output module 130. In this case, the processor 140 can change the color according to the correlation. Therefore, the processor 140 can display the correlation through the color and value in the performance verification diagram.

[0083] When the determination result in step S508 indicates that the CMIF data of the combined model does not satisfy the degree of completion determination condition, the processor 140 determines that the combined model does not reach the degree of completion S516, and executes step S512.

[0084] As described above, according to the present disclosure, the degree of completion of a combined model created by virtually combining two or more vehicle components can be verified in advance.

[0085] Furthermore, for each frequency band, each combination point position, and each degree of freedom (6-DoF), the present disclosure provides a portion where the degree of completion of the combination model is reduced and thus requires improvement, thereby easily identifying improvement points.

[0086] Furthermore, according to the present disclosure, since virtual components are combined by using DS, FBS, etc., subjective judgment of engineers is not involved, so that deviation does not occur for each person.

[0087] Furthermore, according to the present disclosure, the completion of the combined model is determined by comparing the CMIF data of the combined model with the criteria, thereby reducing the time required to analyze the combined model.

[0088] Furthermore, according to the present disclosure, an apparatus for verifying the performance of a combined virtual component is used in the form of a toolbox, so that the degree of completion of a combined model can be easily checked.

Claims

1. A device for verifying the performance of a combined virtual component, the device comprising: Memory; as well as a processor, connected to the memory, The processor determines the degree of completion of the combined model by comparing complex modal indication function CMIF data of the combined model with a preset criterion, wherein the combined model is formed by virtually combining a plurality of components.

2. The device according to claim 1, wherein: The processor creates the combined model by using at least one of a sub-structuring FBS based on a frequency response function FRF, a dynamic sub-structuring DS, and a blocking force.

3. The device according to claim 1, wherein: The processor compares the CMIF data of the combined model with the criteria and determines whether the CMIF data of the combined model satisfies a completion determination condition. When the completion determination condition is satisfied, the processor determines that the combined model has reached completion, and when the completion determination condition is not satisfied, the processor determines that the combined model has not reached completion.

4. The apparatus according to claim 3, wherein the criteria include a CMIF upper limit value and a CMIF lower limit value for each frequency set by a user, in, The completion determination conditions include: a first condition in which a peak value of the CMIF data of the combined model exists within a range equal to or greater than a CMIF upper limit value of each frequency; and a second condition in which the CMIF data of the combined model does not exist within a range equal to or less than a CMIF lower limit value of each frequency, and When the CMIF data of the combined model satisfies the first condition and the second condition, the processor determines that the combined model has reached the degree of completion, and when the CMIF data of the combined model does not satisfy at least one of the first condition and the second condition, the processor determines that the combined model has not reached the degree of completion.

5. The device according to claim 3, wherein: The criteria include a CMIF first mode result of the actual combined component, and a CMIF final mode result of the actual combined component, wherein the completion determination conditions include: a first condition, wherein the peak value of the CMIF data of the combination model appears in a range equal to or greater than the CMIF first mode result of the actual combination component; and a second condition, wherein the CMIF data of the combination model does not exist in a range equal to or less than the CMIF final mode result of the actual combination component, and When the CMIF data of the combined model satisfies the first condition and the second condition, the processor determines that the combined model has reached the degree of completion, and when the CMIF data of the combined model does not satisfy at least one of the first condition and the second condition, the processor determines that the combined model has not reached the degree of completion.

6. The device according to claim 1, wherein: The processor calculates a correlation by comparing the FRF response magnitude of each degree of freedom of each combined part of the combined model with the criterion, and creates a performance verification graph by using the correlation. 7 . The apparatus of claim 6 , wherein the performance verification graph indicates a correlation for each frequency, each combination point, and each of six degrees of freedom, and the correlation is indicated by a value and a color.

8. A method for verifying the performance of a combined virtual component, the method comprising: Acquiring, by a processor, complex mode indicator function (CMIF) data of a combined model created by virtually combining a plurality of components; as well as The processor determines the completeness of the combined model by comparing the CMIF data with preset criteria.

9. The method according to claim 8, wherein: When determining the completion of the combined model, the processor compares the CMIF data of the combined model with the criteria and determines whether the CMIF data of the combined model satisfies a completion determination condition. When the completion determination condition is met, the processor determines that the combined model has reached the completion, and when the completion determination condition is not met, the processor determines that the combined model has not reached the completion.

10. The method according to claim 8, further comprising: After determining the completeness of the combined model, the processor calculates the correlation by comparing the frequency response function (FRF) response amplitude of each degree of freedom of each combined part of the combined model with the criterion, and creates a performance verification diagram by using the correlation.

Images