An electrostatic protection simulation method and system for a three-dimensional chip

Abstract

The application relates to the technical field of electrostatic protection simulation, and particularly discloses a three-dimensional chip electrostatic protection simulation method and system, which comprises the following steps: step S1: collecting relevant data of previous electrostatic protection simulation, including simulation condition parameters, simulation results and hardware parameters of a three-dimensional chip in each simulation; step S2: obtaining the hardware parameters of a three-dimensional chip that needs to be simulated at present, comparing the hardware parameters with the hardware parameters in historical data, calculating the similarity, and selecting historical chip data with high similarity to the hardware parameters of the current chip; step S3: screening the simulation conditions and results of chips similar to the hardware parameters of the current chip from the historical data, calculating the pass rates under the similar conditions, and identifying simulation conditions with pass rates lower than a specific threshold as simulation conditions that need to be considered; and step S4: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters, so as to evaluate the performance and reliability of the three-dimensional chip under similar conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electrostatic protection simulation, and particularly relates to a three-dimensional chip electrostatic protection simulation method and system. BACKGROUND

[0002] The electrostatic protection of a three-dimensional chip refers to the electrostatic discharge phenomenon, that is, during the manufacturing, transportation and use of an integrated circuit chip, the external environment or internal structure of the chip will accumulate a certain amount of electric charge, and these accumulated electric charge will enter the integrated circuit internally through the pins of the chip in an instant.

[0003] The electrostatic protection simulation of a three-dimensional chip is a method of using computer simulation technology to analyze and verify the behavior and performance of an integrated circuit under electrostatic discharge (ESD) conditions; using SPICE and ESD device behavior models, it allows comprehensive, quantitative and dynamic verification of ESD protection circuit design based entirely on ESD discharge functions at the chip level.

[0004] In the prior art, with the continuous progress of three-dimensional chip technology, its scale and complexity are continuously increasing; this growth not only brings higher performance and more functions, but also causes the simulation calculation amount to increase exponentially; the complex structure, diverse material properties and complex charge accumulation and release mechanism of a three-dimensional chip all put forward very high requirements for simulation accuracy; however, high-precision simulation often means huge calculation cost and time consumption, which has become an important bottleneck restricting the research and application of three-dimensional chips. SUMMARY

[0005] The purpose of the present application is to provide a three-dimensional chip electrostatic protection simulation method and system to solve the above technical problems.

[0006] The purpose of the present application can be achieved by the following technical solutions:

[0007] A three-dimensional chip electrostatic protection simulation method, comprising the following steps:

[0008] Step S1: obtaining historical simulation data of electrostatic protection simulation, the historical simulation data including simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip of each electrostatic protection simulation; the simulation condition parameters including discharge voltage and discharge current, the simulation results including pass and fail, and the hardware parameters including size and electrostatic sensitivity of packaging material;

[0009] Step S2: obtaining the hardware parameters of the current three-dimensional chip when performing electrostatic protection simulation on the current three-dimensional chip, denoted as current hardware parameters; denoting the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and denoting the hardware parameters of the historical three-dimensional chip as historical hardware parameters;

[0010] obtaining a similarity between the current hardware parameter and the historical hardware parameter wherein Hpi i represents an i-th current hardware parameter of a current three-dimensional chip, Hpi i represents an i-th historical hardware parameter of a historical three-dimensional chip; a historical three-dimensional chip with the similarity greater than or equal to a preset similarity threshold is selected and recorded as a similar three-dimensional chip;

[0011] Step S3: all similar three-dimensional chips and corresponding simulation condition parameters and simulation results thereof are selected from the historical simulation data and recorded as similar simulation condition parameters and similar simulation results; a pass rate of each similar simulation condition parameter is obtained wherein m is a number of times that a similar simulation result corresponding to the similar simulation condition parameter is passed, and N is a total number of the similar simulation results; a similar simulation condition parameter with a pass rate lower than a preset pass rate threshold is selected and recorded as a key simulation condition parameter;

[0012] Step S4: electrostatic protection simulation is performed on the current three-dimensional chip according to the key simulation condition parameter.

[0013] As a further scheme of the present application: if the i-th historical hardware parameter does not exist on the historical three-dimensional chip, Hpi i is directly recorded as 0; if the i-th current hardware parameter does not exist on the current three-dimensional chip, Hpi i is directly recorded as 0.

[0014] As a further scheme of the present application: if the similarity of the historical three-dimensional chip is less than the preset similarity threshold, the historical three-dimensional chip is not similar to the current three-dimensional chip.

[0015] As a further scheme of the present application: if the pass rate of the similar simulation condition parameter is greater than or equal to the preset pass rate threshold, the similar simulation condition parameter is a non-key simulation condition parameter.

[0016] As a further scheme of the present application: the pass rate threshold is set in a range of [60%, 100%].

[0017] As a further scheme of the present application: the process of performing electrostatic protection simulation on the current three-dimensional chip includes:

[0018] The current three-dimensional chip is sequentially subjected to electrostatic protection simulation according to each key simulation condition parameter; if the simulation result obtained under electrostatic protection simulation of each key simulation condition parameter is all passed, the electrostatic protection of the current three-dimensional chip is normal; if the simulation result obtained under electrostatic protection simulation of any one key simulation condition parameter is not passed, the electrostatic protection of the current three-dimensional chip is abnormal.

[0019] As a further scheme of the present application: an electrostatic protection simulation system of a three-dimensional chip, comprising:

[0020] A data acquisition module: obtaining historical simulation data of electrostatic protection simulation, wherein the historical simulation data comprises simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip in each electrostatic protection simulation; the simulation condition parameters comprise discharge voltage and discharge current, the simulation results comprise pass and fail, and the hardware parameters comprise size and electrostatic sensitivity of packaging material;

[0021] A chip screening module: obtaining hardware parameters of a current three-dimensional chip, denoted as current hardware parameters, when performing electrostatic protection simulation on the current three-dimensional chip; recording the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and recording the hardware parameters of the historical three-dimensional chip as historical hardware parameters;

[0022] Obtaining similarity between the current hardware parameters and the historical hardware parameters Wherein Hpi i represents the i-th current hardware parameter of the current three-dimensional chip, Hpi i represents the i-th historical hardware parameter of the historical three-dimensional chip; selecting the historical three-dimensional chip with a similarity greater than or equal to a preset similarity threshold value, denoted as a similar three-dimensional chip;

[0023] A parameter screening module: selecting all similar three-dimensional chips in the historical simulation data, and corresponding simulation condition parameters and simulation results thereof, and recording the similar simulation condition parameters and the similar simulation results; obtaining a pass rate of each similar simulation condition parameter Wherein m is the number of times that the similar simulation result corresponding to the similar simulation condition parameter is passed, and N is the total number of the similar simulation results; selecting the similar simulation condition parameter with a pass rate lower than a preset pass rate threshold value, denoted as a key simulation condition parameter;

[0024] A simulation module: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameter.

[0025] The present application has the following beneficial effects:

[0026] The application can predict and evaluate the performance of the current three-dimensional chip in electrostatic protection based on past experience by using historical simulation data. This method can significantly improve the accuracy of simulation, as it uses actual historical data rather than relying solely on theoretical models or assumptions. Through analysis and screening of historical data, the scheme can identify the simulation conditions that have the greatest impact on the current chip, thereby avoiding comprehensive simulation of all possible simulation conditions, saving a large amount of computing resources and time, and greatly improving the simulation efficiency. This method provides a systematic way to select key simulation condition parameters, helping engineers and decision-makers better understand which factors are most likely to affect chip performance, thereby making more scientific and reasonable design and improvement decisions. Through effective electrostatic protection simulation, potential electrostatic problems can be foreseen and solved before product release, reducing product failure rate, improving user satisfaction and market competitiveness. BRIEF DESCRIPTION OF DRAWINGS

[0027] The application will be further described below with reference to the accompanying drawings.

[0028] Figure 1 is a flowchart of a three-dimensional chip electrostatic protection simulation method of the application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the application.

[0030] Please refer to Figure 1 The application is a three-dimensional chip electrostatic protection simulation method, which includes the following steps:

[0031] Step S1: Obtain historical simulation data for electrostatic protection simulation, wherein the historical simulation data includes simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip in each electrostatic protection simulation; the simulation condition parameters include discharge voltage and discharge current, the simulation results include pass and fail, and the hardware parameters include size and electrostatic sensitivity of packaging material;

[0032] It should be noted that the data records of multiple electrostatic protection simulations are collected. These records should include the specific conditions, results and related three-dimensional chip hardware parameters of each simulation. Ensure the accuracy and integrity of the data for subsequent analysis and use. The discharge voltage is the discharge voltage value used in each simulation record, usually in volts (V), the discharge current is the discharge current value used in each simulation record, usually in amperes (A), and other possible simulation condition parameters, such as temperature, humidity and other environmental factors, should also be recorded. The simulation results are the results of each simulation, that is, whether the electrostatic protection test is passed, usually represented by "pass" or "fail". The size of the three-dimensional chip is the physical size of the recorded three-dimensional chip, including length, width, height, etc.; the electrostatic sensitivity of the packaging material is the electrostatic sensitivity level of the chip packaging material recorded, which helps to evaluate the performance of the chip in different electrostatic environments, and the hardware parameters also include the structure of the chip, the type of material, etc.

[0033] Step S2: When simulating the electrostatic protection of the current three-dimensional chip, obtain the hardware parameters of the current three-dimensional chip, denoted as current hardware parameters; record the three-dimensional chips in the historical simulation data as historical three-dimensional chips, and record the hardware parameters of the historical three-dimensional chips as historical hardware parameters;

[0034] Obtain the similarity between the current hardware parameters and the historical hardware parameters Wherein Hpi i represents the i-th current hardware parameter of the current three-dimensional chip, Hpi i represents the i-th historical hardware parameter of the historical three-dimensional chip; select the historical three-dimensional chips with a similarity greater than or equal to a preset similarity threshold, denoted as similar three-dimensional chips;

[0035] It can be understood that the three-dimensional chips in the historical simulation data are marked as historical three-dimensional chips, and this step is to distinguish the chips currently being simulated from the chips that have been simulated in the history; At the same time, the hardware parameters of the historical three-dimensional chips are also marked accordingly for subsequent comparison and analysis; The formula for calculating the similarity measures the similarity between the two parameter vectors by calculating the sum of the absolute values of the differences between them; The smaller the difference, the more similar the two parameters. According to the calculated similarity value, select those historical three-dimensional chips with a similarity greater than or equal to a preset similarity threshold with the current three-dimensional chip. These selected historical three-dimensional chips are considered to be similar enough in hardware characteristics to the current chip, so their simulation results have reference value for the current chip.

[0036] As a preferred embodiment of the present application, if the i-th historical hardware parameter does not exist on the historical three-dimensional chip, directly record Hpi i= 0; if the i-th current hardware parameter does not exist on the current three-dimensional chip, Hp is directly recorded as 0 i = 0;

[0037] It is worth noting that in the field of computer science and algorithms, it is often necessary to process and compare hardware parameters of multiple three-dimensional chips. However, due to various reasons (such as different models, different batches, etc.), certain hardware parameters may not exist on all three-dimensional chips.

[0038] It can be understood that when the i-th historical hardware parameter does not exist on the historical three-dimensional chip, the hardware parameter is directly recorded as 0; the purpose of this is to avoid errors in algorithms or programs due to the absence of a certain parameter. This ensures the consistency and comparability of data when comparing current hardware parameters with historical hardware parameters, even if some parameters are missing.

[0039] As a preferred embodiment of the present application, if the similarity of the historical three-dimensional chip is less than a preset similarity threshold, the historical three-dimensional chip is not similar to the current three-dimensional chip;

[0040] It is worth noting that the setting of the similarity threshold needs to be adjusted according to the specific application scenario and requirements. If the threshold is too high, it may lead to some chips that are actually similar being misjudged as not similar; if the threshold is too low, it may lead to some chips that are not similar being misjudged as similar.

[0041] Step S3: Select all similar three-dimensional chips from the historical simulation data, as well as their corresponding simulation condition parameters and simulation results, and record them as similar simulation condition parameters and similar simulation results; obtain the pass rate of each similar simulation condition parameter where m is the number of times the similar simulation result corresponding to the similar simulation condition parameter is passed, and N is the total number of similar simulation results; select the similar simulation condition parameters with a pass rate lower than a preset pass rate threshold, and record them as key simulation condition parameters;

[0042] It can be understood that the above steps aim to filter similar three-dimensional chips from historical simulation data and calculate the pass rate of their simulation condition parameters, in order to determine the simulation condition parameters that need to be focused on. After calculating the pass rate of all similar simulation condition parameters, select the simulation condition parameters with a pass rate lower than a preset pass rate threshold, and record these parameters as key simulation condition parameters. These parameters may be the key points that need special attention or optimization in future simulation experiments.

[0043] As a preferred embodiment of the present application, if the pass rate of the similar simulation condition parameter is greater than or equal to a preset pass rate threshold, the similar simulation condition parameter is a non-key simulation condition parameter;

[0044] It can be understood that in the simulation data analysis or optimization process, it is often necessary to evaluate the effects of different simulation condition parameters to determine which parameters have a greater impact on the simulation results, and thus need special attention or optimization. By comparing the pass rate of similar simulation condition parameters with a preset pass rate threshold, it is determined whether these hardware parameters are key simulation condition parameters. This determination is based on a simple comparison logic: if the pass rate is high enough (i.e., greater than or equal to the threshold), it is considered that the parameter has a relatively small impact on the simulation results, and thus is not a key simulation condition parameter; on the contrary, if the pass rate is lower than the threshold, it is likely that the parameter has an important impact on the simulation results and needs to be focused on and optimized.

[0045] As a preferred embodiment of the present application, the pass rate threshold is set in the range of [60%, 100%];

[0046] It is worth noting that the preset pass rate threshold needs to be reasonably set according to specific application scenarios and needs. If the threshold is too high, some actually important parameters may be misjudged as non-key; if the threshold is too low, it may increase unnecessary attention. Setting such a threshold range helps to balance sensitivity and specificity. If the threshold is too high (close to 100%), it may cause too many simulation conditions to be misjudged as needing attention; if the threshold is too low, it may not effectively screen out simulation conditions that really need attention. The range of [60%, 100%] provides a relatively loose standard, allowing for some degree of fluctuation, while ensuring that only when the pass rate is significantly lower than the general level, it is considered as a key problem.

[0047] Step S4: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters;

[0048] As a preferred embodiment of the present application, the process of performing electrostatic protection simulation on the current three-dimensional chip includes:

[0049] In turn, according to each key simulation condition parameter, the current three-dimensional chip is subjected to electrostatic protection simulation, and if the simulation results obtained under the electrostatic protection simulation of each key simulation condition parameter are all passed, the electrostatic protection of the current three-dimensional chip is normal; if the simulation result obtained under the electrostatic protection simulation of any one key simulation condition parameter is not passed, the electrostatic protection of the current three-dimensional chip is abnormal;

[0050] It can be understood that if the simulation results obtained under the electrostatic protection simulation of all key simulation condition parameters are all passed, it is considered that the electrostatic protection of the current three-dimensional chip is normal. If the simulation result obtained under the electrostatic protection simulation of any one key simulation condition parameter is not passed, it is considered that the electrostatic protection of the current three-dimensional chip is abnormal.

[0051] An electrostatic protection simulation system of a three-dimensional chip, comprising:

[0052] A data collection module: obtaining historical simulation data of electrostatic protection simulation, wherein the historical simulation data comprises simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of the three-dimensional chip in each electrostatic protection simulation; the simulation condition parameters comprise discharge voltage and discharge current, the simulation results comprise pass and fail, and the hardware parameters comprise size and electrostatic sensitivity of packaging material;

[0053] A chip screening module: obtaining hardware parameters of a current three-dimensional chip, denoted as current hardware parameters, when performing electrostatic protection simulation on the current three-dimensional chip; recording the three-dimensional chip in the historical simulation data as a historical three-dimensional chip, and recording the hardware parameters of the historical three-dimensional chip as historical hardware parameters;

[0054] Obtaining similarity between the current hardware parameters and the historical hardware parameters Wherein Hpi i denotes the i-th current hardware parameter of the current three-dimensional chip, Hpi i denotes the i-th historical hardware parameter of the historical three-dimensional chip; selecting the historical three-dimensional chip with similarity greater than or equal to a preset similarity threshold value, denoted as a similar three-dimensional chip;

[0055] A parameter screening module: selecting all similar three-dimensional chips in the historical simulation data, and corresponding simulation condition parameters and simulation results thereof, and recording the similar simulation condition parameters and the similar simulation results; obtaining pass rate of each similar simulation condition parameter Wherein m is the number of times that the similar simulation result corresponding to the similar simulation condition parameter is passed, and N is the total number of the similar simulation results; selecting the similar simulation condition parameter with pass rate lower than a preset pass rate threshold value, denoted as a key simulation condition parameter;

[0056] A simulation module: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameter.

[0057] The above has described one embodiment of the present application in detail, but the content is only the preferred embodiment of the present application, and cannot be considered as limiting the implementation range of the present application. Any equivalent change and improvement made according to the application scope of the present application should still belong to the patent coverage range of the present application.

Claims

1. A method of electrostatic discharge protection simulation of a three-dimensional chip, characterized by, The method comprises the following steps: Step S1: obtaining historical simulation data of electrostatic protection simulation, wherein the historical simulation data comprises simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of a three-dimensional chip in each electrostatic protection simulation; the simulation condition parameters comprise discharge voltage and discharge current, the simulation results comprise pass and fail, and the hardware parameters comprise size and electrostatic sensitivity of packaging material; Step S2: obtaining hardware parameters of a current three-dimensional chip, denoted as current hardware parameters, when performing electrostatic protection simulation on the current three-dimensional chip; a three-dimensional chip in the historical simulation data is denoted as a historical three-dimensional chip, and hardware parameters of the historical three-dimensional chip are denoted as historical hardware parameters; acquiring a similarity between the current hardware parameter and a historical hardware parameter wherein Hpi i represents an i-th current hardware parameter of a current three-dimensional chip, Hpi i represents an i-th historical hardware parameter of a historical three-dimensional chip; and selecting a historical three-dimensional chip with a similarity greater than or equal to a preset similarity threshold value as a similar three-dimensional chip Step S3: selecting all similar three-dimensional chips in the historical simulation data, and corresponding simulation condition parameters and simulation results, and recording as similar simulation condition parameters and similar simulation results; obtaining the pass rate of each similar simulation condition parameter wherein m is the number of times that the similar simulation result corresponding to the similar simulation condition parameter is passed, and N is the total number of similar simulation results; selecting the similar simulation condition parameter with a pass rate lower than a preset pass rate threshold, and recording as a key simulation condition parameter; Step S4: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters; In step S2, if the i-th historical hardware parameter is present on the historical three-dimensional chip, then Hp i = 0; if the i-th current hardware parameter is present on the current three-dimensional chip, then Hp i = 0.

2. The electrostatic discharge protection simulation method for a three-dimensional chip according to claim 1, wherein In step S2, if the similarity of the historical three-dimensional chip is less than a preset similarity threshold, the historical three-dimensional chip is not similar to the current three-dimensional chip.

3. The electrostatic discharge protection simulation method for a three-dimensional chip of claim 1, wherein, In step S3, if the pass rate of the similar simulation condition parameter is greater than or equal to a preset pass rate threshold, the similar simulation condition parameter is a non-key simulation condition parameter.

4. The electrostatic discharge protection simulation method for a three-dimensional chip of claim 1, wherein, In step S3, the pass rate threshold is set in the range of [60%, 100%].

5. The electrostatic discharge protection simulation method for a three-dimensional chip of claim 1, wherein, In step S4, the process of performing electrostatic protection simulation on the current three-dimensional chip comprises: sequentially performing electrostatic protection simulation on the current three-dimensional chip according to each key simulation condition parameter; if the simulation results obtained under electrostatic protection simulation of each key simulation condition parameter are all pass, the electrostatic protection of the current three-dimensional chip is normal; if the simulation result obtained under electrostatic protection simulation of any one key simulation condition parameter is fail, the electrostatic protection of the current three-dimensional chip is abnormal.

6. An electrostatic discharge simulation system for a three-dimensional chip, the system comprising: The method comprises: a data collection module: obtaining historical simulation data of electrostatic protection simulation, wherein the historical simulation data comprises simulation condition parameters and simulation results of each electrostatic protection simulation, and hardware parameters of a three-dimensional chip in each electrostatic protection simulation; the simulation condition parameters comprise discharge voltage and discharge current, the simulation results comprise pass and fail, and the hardware parameters comprise size and electrostatic sensitivity of packaging material; a chip screening module: obtaining hardware parameters of a current three-dimensional chip, denoted as current hardware parameters, when performing electrostatic protection simulation on the current three-dimensional chip; a three-dimensional chip in the historical simulation data is denoted as a historical three-dimensional chip, and hardware parameters of the historical three-dimensional chip are denoted as historical hardware parameters; acquiring a similarity between the current hardware parameter and a historical hardware parameter wherein Hpi i represents an i-th current hardware parameter of a current three-dimensional chip, Hpi i represents an i-th historical hardware parameter of a historical three-dimensional chip; and selecting a historical three-dimensional chip with a similarity greater than or equal to a preset similarity threshold value as a similar three-dimensional chip The parameter screening module selects all similar three-dimensional chips and corresponding simulation condition parameters and simulation results from the historical simulation data, and records the similar simulation condition parameters and the similar simulation results; obtains a pass rate of each similar simulation condition parameter wherein m is the number of times that the similar simulation result corresponding to the similar simulation condition parameter is passed, and N is the total number of the similar simulation results; the similar simulation condition parameter with a pass rate lower than a preset pass rate threshold is selected and recorded as a key simulation condition parameter; a simulation module: performing electrostatic protection simulation on the current three-dimensional chip according to the key simulation condition parameters; and Hp = 0 if the ith historical hardware parameter exists on the historical 3D chip i Hp = 0 if the ith current hardware parameter exists on the current 3D chip i Hp = 0 if the ith historical hardware parameter exists on the historical 3D chip i Hp = 0 if the ith current hardware parameter exists on the current 3D chip i Hp = 0 if the ith historical hardware parameter exists on the historical 3D chip i Hp = 0 if the ith current hardware parameter exists on the current

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