CNN acceleration method and system based on Winograd algorithm

Abstract

The invention provides a CNN acceleration method, system and device based on a Winograd algorithm and a medium, and the method comprises the steps: training a CNN network, obtaining a trained model parameter, carrying out the fixed-point processing of the trained model parameter, and storing the model parameter in a DDR3; reading a convolution kernel from the DDR3, and converting the convolution kernel into a convolution kernel matrix in a Winograd domain by using the transformation matrix; reading input feature mapping from the DDR3, and converting the input feature mapping into an input feature mapping matrix of a Winograd domain by using the input transformation matrix; distributing the convolution kernel matrix and the input feature mapping matrix to each processing unit of a systolic array for point product operation to generate an intermediate output matrix; and collecting an intermediate output matrix, and performing inverse transformation on the intermediate output matrix by using a predefined output transformation matrix to generate an output matrix, so as to solve the problems of low calculation efficiency, large operand and low network performance and accuracy when the CNN is realized.

Description

Technical Field

[0001] The present invention relates to the field of FPGA hardware acceleration technology, and in particular to a CNN acceleration method, system, device and medium based on a Winograd algorithm. Background Art

[0002] Deep convolutional neural networks (CNNs) have been highly favored in the research field due to their excellent accuracy in a variety of cognitive tasks. However, traditional acceleration platforms, such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units), have limited the performance of CNNs in practical applications due to their low throughput and high energy consumption. Compared with application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) offer higher flexibility and programmability, providing a more universal solution for hardware acceleration of CNNs, thus showing unique advantages in this field.

[0003] One of the main challenges in implementing CNN on FPGA is the high consumption of Digital Signal Processor (DSP) resources. The convolution operation in CNN mainly consists of multiplication-accumulation units, and these multipliers are usually implemented by DSP on FPGA. Therefore, when implementing CNN on hardware platform, these resources must be reasonably allocated and utilized to ensure the performance and efficiency of the network.

[0004] To address this challenge, existing research has reduced the number of multiplication and accumulation operations by optimizing the network structure and algorithm of CNN, thereby reducing the demand for DSP resources. For example, depthwise separable convolution reduces the number of multiplication operations by decomposing the convolution operation into depthwise convolution and pointwise convolution. However, this approach may weaken the learning ability and expression ability of the network. In addition, binary convolution reduces multiplication operations by quantizing weight parameters into binary values, but this may sacrifice a certain degree of accuracy. Sparse convolution and low-precision calculations can also reduce the number of multiplication operations, but may affect the performance and accuracy of the network. Compared with these methods, the two-dimensional Winograd algorithm significantly reduces the number of multiplication operations by converting convolution operations into more efficient matrix multiplication operations, thereby reducing the demand for DSP resources while maintaining the performance and accuracy of the network. The Winograd algorithm has significant advantages in improving the computational efficiency of CNN, and is particularly suitable for implementing efficient CNN in resource-constrained environments such as FPGAs.

[0005] Therefore, a CNN acceleration method based on the Winograd algorithm is proposed to solve the problems of low computational efficiency, large amount of calculation, and low network performance and accuracy when implementing CNN. Summary of the invention

[0006] In order to overcome the problems existing in the related art, the present disclosure provides a CNN acceleration method, system, device and medium based on the Winograd algorithm to solve the technical problems of low computational efficiency, large amount of calculation and low network performance and accuracy when implementing CNN in the related art.

[0007] One or more embodiments of this specification provide a CNN acceleration method based on the Winograd algorithm, including the following steps:

[0008] Train the CNN network, obtain the trained model parameters, perform fixed-point processing on the model parameters and save them in DDR3;

[0009] Read the convolution kernel from DDR3 and convert it into a convolution kernel in the Winograd domain using the predefined Winograd transformation matrix;

[0010] Read the input feature map from DDR3 and convert it into the input feature map of Winograd domain using the predefined input transformation matrix;

[0011] Distributing the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to each processing unit of the systolic array to perform a dot multiplication operation of the matrices to generate an intermediate output matrix;

[0012] The intermediate output matrices are collected, and the intermediate output matrices are inversely transformed using a predefined output transformation matrix to generate an output matrix.

[0013] Preferably, the step of reading the convolution kernel from DDR3 and converting the convolution kernel into a convolution kernel in the Winograd domain using a predefined Winograd transformation matrix specifically includes the following steps:

[0014] Read a 3*3 convolution kernel matrix from DDR3, use the predefined Winograd transformation matrix to perform column transformation and row transformation on the convolution kernel matrix in turn to obtain the convolution kernel matrix in the Winograd domain, and write the convolution kernel matrix in the Winograd domain into the weight buffer.

[0015] Preferably, the step of reading the input feature map from DDR3 and converting the input feature map into an input feature map in the Winograd domain using a predefined input transformation matrix specifically includes the following steps:

[0016] Read a 4*4 input feature mapping matrix from DDR3, use a predefined input transformation matrix to perform column transformation and row transformation on the input feature mapping matrix in sequence to obtain an input feature mapping matrix in the Winograd domain, and write the input feature mapping matrix in the Winograd domain into the input buffer area.

[0017] Preferably, the step of distributing the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to the respective processing units of the systolic array to perform the matrix dot multiplication operation further includes the following steps:

[0018] The corresponding positions of the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain are transferred to the next processing unit in the corresponding direction after point multiplication in each processing unit.

[0019] Preferably, the method further comprises the following steps:

[0020] It is determined whether the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain have been completely read, and whether there is flowing matrix data in each processing unit.

[0021] One or more embodiments of this specification provide a CNN acceleration system based on the Winograd algorithm, including a preprocessing module, a convolution kernel module, an input feature module, a dot product module and an inverse transformation module;

[0022] The preprocessing module is used to train the CNN network, obtain the trained model parameters, and perform fixed-point processing on the model parameters and save them in DDR3;

[0023] The convolution kernel module is used to read the convolution kernel from DDR3 and convert the convolution kernel into a convolution kernel in the Winograd domain using a predefined Winograd transformation matrix;

[0024] The input feature module is used to read the input feature map from DDR3 and convert the input feature map into an input feature map of Winograd domain using a predefined input transformation matrix;

[0025] The dot product module is used to distribute the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to each processing unit of the systolic array to perform a dot product operation of the matrix to generate an intermediate output matrix;

[0026] The inverse transformation module is used to collect the intermediate output matrix, and use a predefined output transformation matrix to perform an inverse transformation on the intermediate output matrix to generate an output matrix.

[0027] Preferably, the convolution kernel module is specifically configured as follows:

[0028] Read a 3*3 convolution kernel matrix from DDR3, use the predefined Winograd transformation matrix to perform column transformation and row transformation on the convolution kernel matrix in turn to obtain the convolution kernel matrix in the Winograd domain, and write the convolution kernel matrix in the Winograd domain into the weight buffer.

[0029] Preferably, the input feature module is specifically configured as follows:

[0030] Read a 4*4 input feature mapping matrix from DDR3, use a predefined input transformation matrix to perform column transformation and row transformation on the input feature mapping matrix in sequence to obtain an input feature mapping matrix in the Winograd domain, and write the input feature mapping matrix in the Winograd domain into the input buffer area.

[0031] One or more embodiments of the present specification provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the CNN acceleration method based on the Winograd algorithm as described above when executing the computer program.

[0032] One or more embodiments of the present specification provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the CNN acceleration method based on the Winograd algorithm are implemented as described above.

[0033] The present invention provides a CNN acceleration method, system, device and medium based on Winograd algorithm, which has the advantages of obtaining trained model parameters by training CNN network, and storing the model parameters in DDR3 after fixed-point processing, thereby reducing data storage requirements and improving computing efficiency; reading convolution kernel from DDR3, converting the convolution kernel into a convolution kernel in Winograd domain using a predefined Winograd transformation matrix, dividing the convolution kernel into smaller blocks using Winograd algorithm, converting convolution operation into more efficient matrix multiplication operation, and significantly reducing the number of multiplication operations; reading input feature map from DDR3, converting the input feature map into an input feature map in Winograd domain using a predefined input transformation matrix, and inputting data using Winograd algorithm. It is divided into smaller blocks, which allows the algorithm to perform convolution operations on each block, making data processing more efficient; the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain are distributed to each processing unit of the systolic array to perform matrix point multiplication operations and generate intermediate output matrices. The use of the systolic array structure can ensure that multiple PEs are performing operations in each clock cycle, and the parallelism and throughput are increased, reducing dependence on external storage, enhancing data locality, and thus reducing access delays and energy consumption; the intermediate output matrices are collected, and the intermediate output matrices are inversely transformed using a predefined output transformation matrix to generate an output matrix, which can restore and proofread the data, improve the flexibility and adaptability of the algorithm, and optimize the computing efficiency, thereby achieving high-performance CNN hardware acceleration. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0035] Figure 1 A flowchart of a CNN acceleration method based on the Winograd algorithm provided for one or more embodiments of this specification;

[0036] Figure 2A schematic diagram of the overall accelerator architecture provided for one or more embodiments of this specification;

[0037] Figure 3 A schematic diagram of the implementation of the output matrix conversion module in a single processing unit and the flow of data transmission between PEs provided in one or more embodiments of this specification;

[0038] Figure 4 A basic flow chart of the Winograd algorithm provided for one or more embodiments of this specification;

[0039] Figure 5 A schematic diagram of a systolic array data preparation state at T=0 provided for one or more embodiments of the present specification;

[0040] Figure 6 A schematic diagram of a systolic array data flow state when T=2 provided by one or more embodiments of this specification;

[0041] Figure 7 A schematic diagram of the structure of a CNN acceleration system based on the Winograd algorithm provided for one or more embodiments of this specification;

[0042] Figure 8 A schematic diagram of the structure of a computer device provided for one or more embodiments of this specification. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the protection scope of the present invention.

[0044] The present invention is described in detail below in conjunction with specific implementation methods and the accompanying drawings.

[0045] Method Embodiment

[0046] According to an embodiment of the present invention, a CNN acceleration method based on the Winograd algorithm is provided. Figure 1 As shown, it is a schematic diagram of the process of the CNN acceleration method based on the Winograd algorithm provided in this embodiment. According to the CNN acceleration method based on the Winograd algorithm in this embodiment of the present invention, the following steps are included:

[0047] S110, train the CNN network, obtain the trained model parameters, the model parameters include weight parameters and input feature mapping parameters, the model parameters are fixed-point processed and saved in DDR3, DDR3 is divided into three parts, respectively storing weight data, input data and output data.

[0048] The model parameters are processed in fixed-point format. The value is first multiplied by a scaling factor (usually a power of 2). In this quantization, we multiplied it by 2 to the 13th power, then rounded to the nearest integer, and finally divided by the scaling factor to restore the original value. The decimal point in the fixed-point format is determined by the bit width w of the fixed-point number and the bit width wf of the decimal place. The following formula gives the value of a signed fixed-point number:

[0049]

[0050] Among them, b i Indicates the value of the corresponding bit.

[0051] S120, read convolution kernel g from DDR3, convolution kernel When using the predefined Winograd transformation matrix U = GgG T Convert the convolution kernel into the convolution kernel U in the Winograd domain.

[0052] S130, read the input feature map x to be transformed from the part storing the input data in DDR3, and use the predefined input transformation matrix B T Convert the input feature map into the input feature map of the Winograd domain, and the calculation formula is V = B t xB, where V is the input feature map V in the Winograd domain.

[0053] Among them, S120 and S130 are performed simultaneously.

[0054] S140, distributing the convolution kernel matrix U in the Winograd domain and the input feature mapping matrix V in the Winograd domain to each processing unit of the systolic array to perform a matrix dot multiplication operation to generate an intermediate output matrix M.

[0055] S150, collecting the intermediate output matrix from each PE of the systolic array, using the predefined output transformation matrix A T The intermediate output matrix M is inversely transformed to generate an output matrix Y, and the calculation formula is Y=A T MA,

[0056] This method is improved from the algorithm level and adopts parallel data flow in structure to achieve high-performance hardware acceleration of CNN accelerator. This accelerator mainly consists of the following parts: convolution kernel matrix conversion module, input matrix conversion module, output matrix conversion module, input buffer, weight buffer, output buffer and systolic array data processing unit, such as Figure 2 As shown in FIG. 1 , it is a schematic diagram of the overall accelerator architecture provided by this embodiment. The output matrix conversion module mentioned is in a single processing unit (PE), such as Figure 3 As shown, it is a schematic diagram of the implementation of the output matrix conversion module provided in this embodiment in a single processing unit and the flow of data transmission between PEs.

[0057] The method provided in this embodiment trains a CNN network to obtain trained model parameters, performs fixed-point processing on the model parameters and saves them in DDR3, thereby reducing data storage requirements and improving computing efficiency; reading a convolution kernel from DDR3, using a predefined Winograd transformation matrix to convert the convolution kernel into a convolution kernel in the Winograd domain, dividing the convolution kernel into smaller blocks through the Winograd algorithm, converting the convolution operation into a more efficient matrix multiplication operation, and significantly reducing the number of multiplication operations; reading an input feature map from DDR3, using a predefined input transformation matrix to convert the input feature map into an input feature map in the Winograd domain, and dividing the input data into smaller blocks through the Winograd algorithm, which can allow the algorithm to A convolution operation is performed on each block to make data processing more efficient; the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain are distributed to each processing unit of the systolic array to perform a matrix point multiplication operation to generate an intermediate output matrix. The use of a systolic array structure can ensure that multiple PEs are performing operations in each clock cycle, and the parallelism and throughput are increased, reducing dependence on external storage, enhancing data locality, and thus reducing access latency and energy consumption; the intermediate output matrix is ​​collected, and the intermediate output matrix is ​​inversely transformed using a predefined output transformation matrix to generate an output matrix, which can restore and proofread the data, improve the flexibility and adaptability of the algorithm, and optimize the computing efficiency, thereby achieving high-performance CNN hardware acceleration.

[0058] In one embodiment, the method of reading the convolution kernel from DDR3 and converting the convolution kernel into a convolution kernel matrix in the Winograd domain using a predefined Winograd transformation matrix specifically includes the following steps:

[0059] Read 3*3 convolution kernel matrix from DDR3 Use the predefined Winograd transformation matrix G to perform column transformation and row transformation on the convolution kernel matrix g in sequence to obtain the convolution kernel matrix in the Winograd domain, and write the convolution kernel matrix in the Winograd domain into the weight buffer.

[0060] Among them, using w i =Gg performs column transformation of the convolution kernel, They are the first, second and third columns of data after conversion:

[0061]

[0062] Store the intermediate results of convolution kernel column transformation

[0063] Then use U = w i G T Perform row transformation of intermediate results:

[0064]

[0065] Get the final result of the convolution kernel conversion module Store the matrix into the weight buffer.

[0066] The method provided in this embodiment divides the convolution kernel into smaller blocks through the Winograd algorithm, converts the convolution operation into a more efficient matrix multiplication operation, significantly reduces the number of multiplication operations, and maintains the calculation accuracy.

[0067] In one embodiment, the step of reading the input feature map from DDR3 and converting the input feature map into an input feature map matrix in the Winograd domain using a predefined input transformation matrix specifically includes the following steps:

[0068] Read the 4*4 input feature map matrix from DDR3 The input feature mapping matrix is ​​transformed column by column and row by row using a predefined input transformation matrix to obtain an input feature mapping matrix in a Winograd domain, and the input feature mapping matrix in the Winograd domain is written into an input buffer area.

[0069] Among them, use x i =B T x transforms each column of the matrix x, reading the matrix one column at a time.

[0070] The first column of output is:

[0071] The second column outputs:

[0072] The third column outputs:

[0073] The fourth column outputs:

[0074] Storing intermediate results

[0075] Using V=x i B completes the subsequent calculation:

[0076]

[0077]

[0078] Get the final result of the input conversion module Store the matrix into the input buffer.

[0079] The method provided in this embodiment divides the input data into smaller blocks through the Winograd algorithm, allowing the algorithm to perform convolution operations on each block, making data processing more efficient, reducing the demand for DSP resources, while maintaining the performance and accuracy of the network.

[0080] In one embodiment, the step of distributing the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to the respective processing units of the systolic array to perform the matrix dot multiplication operation further includes the following steps:

[0081] The corresponding positions of the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain are transferred to the next processing unit in the corresponding direction after point multiplication in each processing unit, such as Figure 4 As shown, it is a basic flow chart of the Winograd algorithm provided in this embodiment.

[0082] When the clock cycle T = 0, the input on the left side of the systolic array is the input data transformation matrix V, and the input on the top is the convolution kernel transformation matrix U, such as Figure 5 As shown, it is a schematic diagram of the systolic array data preparation state when T=0 provided in this embodiment. When T=1, U 11 and V 11 Enter PE1, perform the point multiplication operation at the corresponding position, and then input and output the result to the transfer module.

[0083] When T=2, V 12 with U 21 Perform dot multiplication at PE1, V 11 Enter PE2 and U 12 Perform dot product, U 11 Enter PE4 and V 21 Perform a dot product, such as Figure 6 As shown, it is a schematic diagram of the data flow state of the systolic array when T=2 provided in this embodiment. The three PEs perform point multiplication in the same time cycle, and transmit the point multiplication results to S5 at the same time, and perform inverse transformation to obtain the final result. According to the traditional convolution method, only one feature map convolution multiplication and addition operation can be performed in one clock cycle, while the use of the systolic array structure can ensure that multiple PEs are performing operations in each clock cycle, and theoretically the parallelism and throughput are both increased.

[0084] The method provided in this embodiment can perform multiple convolution operations simultaneously through the parallel data processing capability of the systolic array, and allow multiple processing units to work on different data blocks simultaneously in a parallel processing environment, thereby improving the processing speed.

[0085] In one embodiment, the following steps are also included:

[0086] Repeat S140-S150 to determine whether the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain have been completely read, and determine whether there is flowing matrix data in each processing unit to ensure that all data have been calculated.

[0087] The method provided in this embodiment ensures data integrity, optimizes resource utilization, and improves system stability by determining whether the convolution kernel matrix and the input feature mapping matrix have been completely read and monitoring the data flow in the processing unit.

[0088] System Example

[0089] According to an embodiment of the present invention, a CNN acceleration system based on the Winograd algorithm is provided. Figure 7 As shown, it is a structural schematic diagram of the CNN acceleration based on the Winograd algorithm provided in this embodiment. The CNN acceleration system based on the Winograd algorithm according to the embodiment of the present invention includes a preprocessing module 71, a convolution kernel module 72, an input feature module 73, a dot product module 74 and an inverse transformation module 75.

[0090] The preprocessing module 71 is used to train the CNN network, obtain the trained model parameters, perform fixed-point processing on the model parameters and save them in DDR3.

[0091] The convolution kernel module 72 is used to read the convolution kernel from DDR3 and convert the convolution kernel into a convolution kernel matrix in the Winograd domain using a predefined Winograd transformation matrix.

[0092] The input feature module 73 is used to read the input feature map from DDR3 and convert the input feature map into an input feature map matrix in the Winograd domain using a predefined input transformation matrix.

[0093] The dot product module 74 is used to distribute the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to each processing unit of the systolic array to perform a dot product operation of the matrix and generate an intermediate output matrix.

[0094] The inverse transformation module 75 is used to collect the intermediate output matrix, and use a predefined output transformation matrix to perform an inverse transformation on the intermediate output matrix to generate an output matrix.

[0095] The system provided in this embodiment trains the CNN network through the preprocessing module 71, obtains the trained model parameters, and stores the model parameters in DDR3 after fixed-point processing, thereby reducing the data storage requirements and improving the computing efficiency; the convolution kernel module 72 reads the convolution kernel from DDR3, converts the convolution kernel into a convolution kernel in the Winograd domain using a predefined Winograd transformation matrix, divides the convolution kernel into smaller blocks through the Winograd algorithm, and converts the convolution operation into a more efficient matrix multiplication operation, thereby significantly reducing the number of multiplication operations; the input feature module 73 reads the input feature map from DDR3, converts the input feature map into an input feature map in the Winograd domain using a predefined input transformation matrix, and divides the input data into smaller blocks through the Winograd algorithm, thereby allowing The algorithm performs convolution operations on each block, making data processing more efficient; the dot product module 74 distributes the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain to each processing unit of the systolic array to perform the dot product operation of the matrix and generate an intermediate output matrix. The use of the systolic array structure can ensure that multiple PEs are performing operations in each clock cycle, and the parallelism and throughput are increased, reducing the dependence on external storage, enhancing data locality, and thus reducing access delays and energy consumption; the inverse transformation module 75 collects the intermediate output matrix, uses a predefined output transformation matrix to inversely transform the intermediate output matrix, and generates an output matrix, which can restore and proofread the data, improve the flexibility and adaptability of the algorithm, and optimize the computing efficiency, thereby achieving high-performance CNN hardware acceleration.

[0096] In one embodiment, the convolution kernel module 72 is specifically configured as follows:

[0097] Read a 3*3 convolution kernel matrix from DDR3, use the predefined Winograd transformation matrix to perform column transformation and row transformation on the convolution kernel matrix in turn to obtain the convolution kernel matrix in the Winograd domain, and write the convolution kernel matrix in the Winograd domain into the weight buffer.

[0098] The system provided in this embodiment divides the convolution kernel into smaller blocks through the Winograd algorithm, converts the convolution operation into a more efficient matrix multiplication operation, significantly reduces the number of multiplication operations, and maintains the calculation accuracy.

[0099] In one embodiment, the input feature module 73 is specifically configured as follows:

[0100] Read a 4*4 input feature mapping matrix from DDR3, use a predefined input transformation matrix to perform column transformation and row transformation on the input feature mapping matrix in sequence to obtain an input feature mapping matrix in the Winograd domain, and write the input feature mapping matrix in the Winograd domain into the input buffer area.

[0101] The system provided in this embodiment divides the input data into smaller blocks through the Winograd algorithm, allowing the algorithm to perform convolution operations on each block, making data processing more efficient, reducing the demand for DSP resources, while maintaining the performance and accuracy of the network.

[0102] The embodiment of the present invention is a system embodiment corresponding to the above-mentioned method embodiment. The specific operations of the processing steps of each module can be understood by referring to the description of the method embodiment, which will not be repeated here.

[0103] like Figure 8 As shown, the present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the CNN acceleration method based on the Winograd algorithm in the above-mentioned embodiment is implemented, or when the computer program is executed by a processor, the CNN acceleration method based on the Winograd algorithm in the above-mentioned embodiment is implemented.

[0104] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0105] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and the contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A CNN acceleration method based on Winograd algorithm, characterized in that: The following steps are involved: Train the CNN network, obtain the trained model parameters, perform fixed-point processing on the model parameters and save them in DDR3; Read the convolution kernel from DDR3 and use the predefined Winograd transformation matrix to convert the convolution kernel into a convolution kernel matrix in the Winograd domain; Read the input feature map from DDR3 and convert the input feature map into the input feature map matrix of the Winograd domain using the predefined input transformation matrix; Distributing the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to each processing unit of the systolic array to perform a dot multiplication operation of the matrices to generate an intermediate output matrix; The intermediate output matrices are collected, and the intermediate output matrices are inversely transformed using a predefined output transformation matrix to generate an output matrix.

2. The CNN acceleration method according to claim 1, wherein: The convolution kernel is read from DDR3, and the convolution kernel is converted into a convolution kernel matrix in the Winograd domain using a predefined Winograd transformation matrix, specifically including the following steps: Read a 3*3 convolution kernel matrix from DDR3, use the predefined Winograd transformation matrix to perform column transformation and row transformation on the convolution kernel matrix in turn to obtain the convolution kernel matrix in the Winograd domain, and write the convolution kernel matrix in the Winograd domain into the weight buffer.

3. The CNN acceleration method according to claim 1, wherein: The step of reading the input feature map from DDR3 and converting the input feature map into an input feature map matrix in the Winograd domain using a predefined input transformation matrix specifically includes the following steps: Read a 4*4 input feature mapping matrix from DDR3, use a predefined input transformation matrix to perform column transformation and row transformation on the input feature mapping matrix in sequence to obtain an input feature mapping matrix in the Winograd domain, and write the input feature mapping matrix in the Winograd domain into the input buffer area.

4. The CNN acceleration method according to claim 1, wherein: The step of distributing the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to the respective processing units of the systolic array to perform the dot multiplication operation of the matrices further includes the following steps: The corresponding positions of the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain are transferred to the next processing unit in the corresponding direction after point multiplication in each processing unit.

5. The CNN acceleration method according to claim 1, wherein: The following steps are also included: It is determined whether the convolution kernel matrix in the Winograd domain and the input feature mapping matrix in the Winograd domain have been completely read, and whether there is flowing matrix data in each processing unit.

6. A CNN acceleration system based on Winograd algorithm, characterized in that: Including preprocessing module, convolution kernel module, input feature module, point multiplication module and inverse transformation module; The preprocessing module is used to train the CNN network, obtain the trained model parameters, and perform fixed-point processing on the model parameters and save them in DDR3; The convolution kernel module is used to read the convolution kernel from DDR3 and convert the convolution kernel into a convolution kernel matrix in the Winograd domain using a predefined Winograd transformation matrix; The input feature module is used to read the input feature map from DDR3 and convert the input feature map into an input feature map matrix in Winograd domain using a predefined input transformation matrix; The dot product module is used to distribute the convolution kernel matrix in the Winograd domain and the input feature map matrix in the Winograd domain to each processing unit of the systolic array to perform a dot product operation of the matrix to generate an intermediate output matrix; The inverse transformation module is used to collect the intermediate output matrix, and use a predefined output transformation matrix to perform an inverse transformation on the intermediate output matrix to generate an output matrix.

7. The CNN acceleration system according to claim 6, wherein: The convolution kernel module is specifically configured as follows: Read a 3*3 convolution kernel matrix from DDR3, use the predefined Winograd transformation matrix to perform column transformation and row transformation on the convolution kernel matrix in turn to obtain the convolution kernel matrix in the Winograd domain, and write the convolution kernel matrix in the Winograd domain into the weight buffer.

8. The CNN acceleration system as claimed in claim 6, characterized in that: The input feature module is specifically configured as follows: Read a 4*4 input feature mapping matrix from DDR3, use a predefined input transformation matrix to perform column transformation and row transformation on the input feature mapping matrix in sequence to obtain an input feature mapping matrix in the Winograd domain, and write the input feature mapping matrix in the Winograd domain into the input buffer area.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the CNN acceleration method based on the Winograd algorithm as described in any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the CNN acceleration method based on the Winograd algorithm as described in any one of claims 1 to 5 are implemented.

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