Display control method, circuit, electronic device, and computer-readable storage medium

Abstract

The application provides a display control method, circuit, electronic equipment and computer readable medium, and relates to the technical field of digital image processing. The method comprises the following steps: storing to-be-converted data in a first storage unit, and converting the to-be-converted data into first grouping data and second grouping data in the first storage unit; storing signal controls the grouping data to be stored in a second storage unit; transmission signal controls the grouping data to be transmitted to a first-level circuit; the storage signal comprises a first storage sub-signal and a second storage sub-signal; the transmission signal comprises a first transmission sub-signal and a second transmission sub-signal; the second storage sub-signal is triggered after a preset time period is delayed when the first storage sub-signal ends; the trigger time points of the first storage sub-signal and the first transmission sub-signal are consistent; and the trigger time points of the second storage sub-signal and the second transmission sub-signal are consistent. Through optimization of the timing configuration of the control signal, the data turnover and waiting time are reduced, the invalid working time can be effectively reduced, and the chip power consumption is reduced.

Description

Technical Field

[0001] This application relates to the field of digital image processing technology, and more specifically, to a display control method, circuit, electronic device, and computer-readable storage medium. Background Technology

[0002] With the continuous development of display technology, AMOLED displays have been widely used in electronic devices such as smartphones and tablets due to their advantages such as high contrast, wide color gamut, and low power consumption. To improve the resolution of AMOLED displays, PenTile technology is typically employed. PenTile technology achieves higher pixel density through a special sub-pixel arrangement, thereby enhancing the display effect.

[0003] In AMOLED displays, the driver chip needs to process a large amount of image data. Typically, the image data sent by the host is real image data, which the driver chip processes into pentile-arranged subpixel data using subpixel rendering (SPR) technology. While this method improves display resolution, it also increases the complexity of data processing.

[0004] However, this design has certain problems during data transmission. The driver chip needs to transmit sub-pixel 1 data or sub-pixel 2 data to the grayscale voltage conversion circuit in time intervals within a single line of display time. The conventional approach is to select the sub-pixel data to be transmitted in the current time interval using a control signal; a high control signal transmits sub-pixel 1 data, and a low control signal transmits sub-pixel 2 data. During the switching between sub-pixel 1 and sub-pixel 2 data, there is a period of invalid data flipping, causing the grayscale voltage conversion circuit to be ineffective for a period of time, resulting in increased power consumption of the driver chip during this period. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a display control method that, by optimizing the timing configuration of control signals, reduces data flipping and waiting time, thereby effectively reducing inactive working time and chip power consumption. This addresses the problems of excessive inactive circuit working time and high chip power consumption in the prior art.

[0006] The display control method includes: storing data to be converted into a first storage unit, and converting the data to be converted into first grouped data and second grouped data within the first storage unit; controlling the first grouped data and the second grouped data to be stored into a second storage unit via a storage signal; wherein the storage signal includes a first storage sub-signal and a second storage sub-signal; controlling the first grouped data and the second grouped data to be transmitted to a primary circuit via a transmission signal; wherein the transmission signal includes a first transmission sub-signal and a second transmission sub-signal; wherein the second storage sub-signal is triggered after a preset time delay when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0007] In the above implementation process, preliminary storage and grouping operations are first completed in the first storage unit. The data to be converted is stored in the first storage unit. After the first storage unit fully receives the data to be converted and transforms it into first and second group data, it controls the storage of the first and second group data into the second storage unit respectively. Then, the first and second group data are transmitted to the first-level circuit via transmission signals, which include a first transmission sub-signal and a second transmission sub-signal. The triggering of the second storage sub-signal requires a preset delay after the first storage sub-signal ends. The triggering times of the first storage sub-signal and the first transmission sub-signal are consistent, as are the triggering times of the second storage sub-signal and the second transmission sub-signal. This achieves ordered data storage and transmission, improves the stability and reliability of the overall display control method, and allows for the adjustment of the timing of various signals, reducing the circuit's ineffective operating time and lowering chip power consumption.

[0008] Optionally, the display control method further includes: the transmission signal controls the first group data and the second group data to be transmitted to the second stage circuit after passing through the first stage circuit; the second stage circuit converts the first group data and the second group data and outputs a display voltage.

[0009] In the above implementation process, the first and second groups of data, after being processed by the primary circuit, are transmitted to the secondary circuit. In the secondary circuit, these two data groups undergo further transformation processing, ultimately outputting a voltage signal for display. This achieves a complete conversion process from the raw data state to a voltage signal directly usable for display, improving the flexibility and adaptability of the display control method. It better meets the diverse needs for data processing and display effects in different display scenarios, while also enhancing the performance and stability of the entire display system.

[0010] Optionally, wherein the first group data includes a first category of data and a second category of data, and the second group data includes a third category of data and a fourth category of data; controlling the transmission of the first group data and the second group data to the primary circuit via a transmission signal further includes: transmitting the first category of data and / or the third category of data to the secondary circuit when the transmission signal is at a high level; and transmitting the second category of data and / or the fourth category of data to the secondary circuit when the transmission signal is at a low level.

[0011] In the above implementation process, by further subdividing the first group of data into first and second categories, and further subdividing the second group into third and fourth categories, the flexibility and granularity of data processing are enhanced. When the transmission signal is high, the first and / or third categories of data are transmitted to the secondary circuit; when the transmission signal is low, the second and / or fourth categories of data are transmitted to the secondary circuit. Utilizing the high and low level characteristics of the transmission signal, time-division transmission of different categories of data is achieved, reducing conflicts and interference during data transmission, improving the stability and reliability of data transmission, and optimizing the data processing efficiency of the secondary circuit. By adjusting the timing of each signal, the ineffective working time of the circuit is reduced, lowering chip power consumption. This further improves the performance of the entire display control method, better meeting the high requirements for data processing and display effects in complex display scenarios.

[0012] Optionally, controlling the storage of the first packet data and the second packet data into the second storage unit via the storage signal includes: controlling the first packet data to be stored from the first storage unit into the second storage unit via the first storage sub-signal; and controlling the second packet data to be stored from the first storage unit into the second storage unit via the second storage sub-signal.

[0013] In the above implementation process, by subdividing the storage signal into a first storage sub-signal and a second storage sub-signal, separate control of the first group of data and the second group of data is achieved. Specifically, the first storage sub-signal controls the storage operation of the first group of data from the first storage unit to the second storage unit, ensuring the accurate storage of the first group of data; simultaneously, the second storage sub-signal controls the storage process of the second group of data from the first storage unit to the second storage unit, ensuring the reliable storage of the second group of data. This method of controlling the storage of different group data with different storage sub-signals not only improves the flexibility and controllability of data storage but also reduces data conflicts and chaos during the storage process. By adjusting the timing of each signal, the ineffective operating time of the circuit is reduced, thereby lowering chip power consumption.

[0014] Optionally, controlling the transmission of the first packet data and the second packet data to the primary circuit via the transmission signal includes: controlling the first packet data to be transmitted from the second storage unit to the primary circuit via the first transmission sub-signal; and controlling the second packet data to be transmitted from the second storage unit to the primary circuit via the second transmission sub-signal.

[0015] In the above implementation process, by subdividing the transmission signal into a first transmission sub-signal and a second transmission sub-signal, the separate control and transmission of the first and second data packets are achieved. Specifically, the first transmission sub-signal precisely controls the transmission process of the first data packet from the second storage unit to the first-level circuit, ensuring the accurate input of the first data packet; simultaneously, the second transmission sub-signal controls the transmission operation of the second data packet from the second storage unit to the first-level circuit, ensuring the reliable transmission of the second data packet. By controlling the transmission of different data packets with different transmission sub-signals, not only is the flexibility and controllability of data transmission improved, but conflicts and interference during data transmission are also effectively reduced. By adjusting the timing of each signal, the ineffective operating time of the circuit is reduced, thereby lowering chip power consumption.

[0016] Optionally, storing the data to be converted into a first storage unit, and converting the data to be converted into a first group of data and a second group of data within the first storage unit, includes: obtaining the data to be converted from the original data through preprocessing; temporarily storing the data to be converted in the first storage unit; and, after the first storage unit has received all the data to be converted, dividing the data to be converted into the first group of data and the second group of data through the first storage unit.

[0017] In the above implementation process, the raw data is first preprocessed to ensure that the data to be converted meets the requirements of subsequent processing. The preprocessed data to be converted is temporarily stored in the first storage unit. After the first storage unit has received all the data to be converted, it uses its storage and processing capabilities to divide the data into a first group and a second group. Grouping facilitates the separate processing and transmission of different types of data, thereby improving the efficiency and accuracy of the entire display control method and ensuring that the data maintains its orderliness during storage and transmission.

[0018] This application embodiment also provides a display control circuit, the display control circuit including: a first storage unit, a second storage unit, and a primary circuit; the first storage unit is configured to store data to be converted and receive storage signals to perform corresponding operations; wherein, the storage signals include: a first storage sub-signal and a second storage sub-signal; wherein, the first storage unit receives the first storage sub-signal and divides the data to be converted into a first group of data and a second group of data; the second storage unit is configured to receive a transmission signal and then transmit the first group of data and the second group of data to the primary circuit; wherein, the transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; wherein, the second storage sub-signal is triggered after a preset time period when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0019] In the above implementation process, the display control circuit achieves efficient data storage, grouping, and transmission through the coordinated operation of the first storage unit, the second storage unit, and the primary circuit. After receiving the first storage sub-signal, the first storage unit divides the data to be converted into a first group of data and a second group of data. Subsequently, after receiving the transmission signal, the second storage unit sequentially transmits these two groups of data to the primary circuit. The first and second transmission sub-signals in the transmission signal control the transmission process of the first and second groups of data, respectively, ensuring the orderly and accurate transmission of data. Furthermore, the second storage sub-signal triggers after a preset time delay following the termination of the first storage sub-signal, further optimizing the timing relationship between data storage and transmission, reducing conflicts and chaos during data processing, and minimizing the circuit's ineffective operating time by adjusting the timing of various signals, thus reducing chip power consumption. This not only improves the flexibility and controllability of data storage and transmission but also enhances the stability and reliability of the entire display control circuit, providing strong support for achieving efficient display control functions.

[0020] Optionally, the display control circuit further includes a secondary circuit; the secondary circuit is configured to receive and convert the first group data and the second group data and then output a display voltage.

[0021] In the above implementation process, after the first-level circuit completes the initial processing of the first and second group data, the second-level circuit receives these processed data and performs further conversion processing, ultimately outputting a voltage signal for display. This achieves a complete conversion process from the raw data state to a voltage signal directly usable for display. Combined with the previous circuit modules' optimization of data grouping and transmission timing, it reduces conflicts and chaos during data processing. By adjusting the timing of various signals, the circuit's ineffective operating time is reduced, lowering chip power consumption.

[0022] This application also provides an electronic device, which includes a memory and a processor. The memory stores program instructions, and when the processor reads and runs the program instructions, it executes the steps in any of the above implementation methods.

[0023] In the above implementation process, the electronic device effectively executes the display control method through its internal memory and processor. The program instructions stored in the memory contain the various steps of the display control method. When the processor reads and runs these program instructions, the electronic device can complete the storage, grouping, transmission, and final display control operations of data according to the predetermined process.

[0024] This application also provides a computer-readable storage medium storing computer program instructions, which are read and executed by a processor to perform the steps in any of the above implementations.

[0025] In the above implementation process, the computer-readable storage medium serves as a key storage component, storing computer program instructions related to the display control method. When these program instructions are read and executed by the processor, the steps in any of the above implementation methods can be performed, thereby achieving effective deployment and operation of the display control method. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A simplified schematic diagram of a display control method provided in an embodiment of this application;

[0028] Figure 2 A detailed schematic diagram illustrating a display control method provided in an embodiment of this application;

[0029] Figure 3 A schematic diagram illustrating data transmission to a secondary circuit according to an embodiment of this application;

[0030] Figure 4 A schematic diagram of a display control circuit provided in an embodiment of this application;

[0031] Figure 5 A block diagram illustrating an electronic device provided in an embodiment of this application;

[0032] Figure 6 A schematic diagram of data transmission in one embodiment of this application is provided;

[0033] Figure 7 A timing diagram of data transmission in one embodiment of this application is provided;

[0034] Figure 8 A timing diagram of a conventional method provided in the embodiments of this application.

[0035] Icons: 001-Preprocessing module; 010-First storage unit; 020-Second storage unit; 030-First-level circuit; 040-Second-level circuit; 100-Electronic device; 111-Memory; 112-Storage controller; 113-Processor; 114-Peripheral interface; 115-Input / output unit; 116-Display unit. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of the embodiments of this application.

[0037] This application provides a display control method for controlling data display in a driver chip. By generating signals of the same type but different categories, the data to be displayed is sent to the output circuit (secondary circuit 040) according to the configured timing sequence, reducing invalid flipping during data switching and thus reducing the power consumption of the circuit.

[0038] Optionally, please refer to Figure 1 , Figure 1 This is a simplified schematic diagram of the display control method provided in the embodiments of this application.

[0039] The display control method includes: storing the data to be converted into a first storage unit 010, and converting the data to be converted into a first group of data and a second group of data within the first storage unit 010; controlling the storage of the first group of data and the second group of data into a second storage unit 020 via a storage signal; wherein the storage signal includes a first storage sub-signal and a second storage sub-signal; controlling the transmission of the first group of data and the second group of data to a first-level circuit 030 via a transmission signal; wherein the transmission signal includes a first transmission sub-signal and a second transmission sub-signal; wherein the second storage sub-signal is triggered after a preset time delay when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are consistent; the triggering time points of the second storage sub-signal and the second transmission sub-signal are consistent.

[0040] In the above implementation process, the display control method performs preliminary data processing and grouping by storing the data to be converted into the first storage unit 010 and then converting it into first group data and second group data within the first storage unit 010. Subsequently, the first group data and second group data are stored into the second storage unit 020 via storage signals, where the storage signals include first and second storage sub-signals. Further, the first group data and second group data are transmitted to the first-level circuit 030 via transmission signals, where the transmission signals include first and second transmission sub-signals. The trigger time of the transmission signals coincides with the trigger time of the storage signals, maintaining the orderliness and accuracy of data transmission. Furthermore, the second storage sub-signal triggers after a preset time delay following the termination of the first storage sub-signal, further optimizing the timing relationship between data storage and transmission, avoiding conflicts and chaos during data processing, reducing the circuit's ineffective operating time, and lowering chip power consumption.

[0041] Optionally, please combine Figure 1 See Figure 2 , Figure 2 This is a detailed schematic diagram of a display control method provided in an embodiment of this application.

[0042] The original data is preprocessed to obtain the data to be transformed; the data to be transformed is temporarily stored in the first storage unit 010; after the first storage unit 010 has received all the data to be transformed, the data to be transformed is divided into a first group of data and a second group of data through the first storage unit 010, wherein the first group of data includes a first category of data and a second category of data, and the second group of data includes a third category of data and a fourth category of data.

[0043] In the above implementation process, the raw data is preprocessed to obtain the data to be transformed. Preprocessing may include data cleaning, format conversion, and other operations to ensure the data meets the requirements of subsequent processing. Next, the data to be transformed is temporarily stored in the first storage unit 010, awaiting further processing. After the first storage unit 010 has received all the data to be transformed, it divides the data into a first group and a second group. The first group includes a first category of data and a second category of data, while the second group includes a third category of data and a fourth category of data.

[0044] Optionally, the grouped data here can be expanded to more groups or categories. The finer the grouping, the better the data transmission effect, but the more time is required and the more complex the circuitry becomes. Choosing appropriate grouping can ensure output efficiency while reducing chip power consumption. Similarly, each category has its own control signal, and the timing of the various control signals is configurable.

[0045] Please combine Figure 2 Based on this, refer to Figure 3 , Figure 3 This is a schematic diagram of data transmission to the secondary circuit 040 provided in an embodiment of this application.

[0046] The storage signal controls the storage of the first and second data groups into the second storage unit 020. The transmission signal controls the transmission of the first and second data groups through the primary circuit 030 to the secondary circuit 040. When the transmission signal is high, the first type of data and / or the third type of data is transmitted to the secondary circuit 040; when the transmission signal is low, the second type of data and / or the fourth type of data is transmitted to the secondary circuit 040. The secondary circuit 040 converts the first and second data groups and outputs a display voltage.

[0047] In the above implementation process, the first and second groups of data are stored in the second storage unit 020 via storage signals. The storage signals include a first storage sub-signal and a second storage sub-signal, which are used to control the storage operations of the first and second groups of data, respectively. Next, the first and second groups of data are transmitted to the second-level circuit 040 via transmission signals after passing through the first-stage circuit 030. The transmission signals include a first transmission sub-signal and a second transmission sub-signal. When the transmission signal is high, the first type of data and / or the third type of data is transmitted to the second-level circuit 040; when the transmission signal is low, the second type of data and / or the fourth type of data is transmitted to the second-level circuit 040. After processing the first and second groups of data, the second-level circuit 040 outputs a voltage signal for display. Utilizing grouping and timing configuration not only improves the flexibility and efficiency of data processing but also effectively reduces the time spent on invalid data flipping, lowers the power consumption of the driver chip, and enhances the performance and stability of the entire display control method.

[0048] In one embodiment of this application, the method is applied to the field of digital image processing. The original data is processed using subpixel rendering (SPR) to create pentile-arranged subpixel data. For example, if the original data is at 1080 resolution (i.e., 1080 pixels arranged in 3 columns), after SPR processing, 2160 subpixel data are obtained, meaning each pixel has two subpixels. With all pixel data stored in the first storage unit 010, this pixel data is divided into a first group of data and a second group of data. The first group of data includes a first category of data and a second category of data, and the second group of data includes a third category of data and a fourth category of data. The grouped pixel data is stored in the second storage unit 020 under the control of a storage signal, which includes a first storage sub-signal and a second storage sub-signal, respectively used to control the storage operations of the first group of data and the second group of data. The first and second group data are transmitted to the primary circuit 030 via transmission signals. These transmission signals include a first transmission sub-signal and a second transmission sub-signal. When the transmission signal is high, the first type of pixel data and / or the third type of pixel data are transmitted to the secondary circuit 040; when the transmission signal is low, the second type of pixel data and / or the fourth type of pixel data are transmitted to the secondary circuit 040. It should be noted that when the storage signal is high, the corresponding transmission signal changes from low to high. Each transmission signal must also change sequentially when changing from high to low. The secondary circuit 040 outputs the display voltage after converting the first and second group data. This grouping and timing configuration not only improves the flexibility and efficiency of data processing but also effectively reduces the time spent on invalid data flipping, lowers the power consumption of the driver chip, and enhances the performance and stability of the entire display control method.

[0049] Please see Figure 4 , Figure 4 This is a schematic diagram of a display control circuit provided in an embodiment of this application.

[0050] The display control circuit includes: a preprocessing module 001, a first storage unit 010, a second storage unit 020, a primary circuit 030, and a secondary circuit 040. The first storage unit 010 is configured to store data to be converted and receive storage signals to perform corresponding operations. The storage signals include a first storage sub-signal and a second storage sub-signal. The first storage unit 010 receives the first storage sub-signal and divides the data to be converted into a first group of data and a second group of data. The second storage unit 020 receives a transmission signal and then transmits the first group of data and the second group of data to the primary circuit 030. The secondary circuit 040 receives and converts the first group of data and the second group of data and outputs a display voltage. The transmission signals include a first transmission sub-signal and a second transmission sub-signal. The second storage sub-signal is triggered after a preset time delay when the first storage sub-signal ends. The trigger times of the first storage sub-signal and the first transmission sub-signal are the same.

[0051] In one embodiment of this application, the preprocessing module 001 may be a data format conversion module, a data cleaning module, a data compression module, a data enhancement module, a color correction module, or a data sorting module, etc. The first storage unit 010 and the second storage unit 020 may be data buffers or data caches; used to store raw pixel data or preprocessed data to be converted, or first grouped data and second grouped data. The primary circuit 030 may be a MUX2:1 circuit, a data selector, or a multiplexer; used to select and transmit grouped data to the secondary circuit 040. The secondary circuit 040 may be a grayscale conversion circuit, a display driver circuit, or a display signal conversion circuit; used to convert the grouped data into display voltage.

[0052] In one embodiment of this application, the raw pixel data typically originates from a host or other external device, and its input speed and format may not be entirely suitable for direct subsequent data processing. The preprocessing module 001 converts the raw pixel data from one format to another to meet the requirements of subsequent processing. For example, it converts RGB format data to Pentile format data. The first storage unit 010 acts as a buffer, receiving individual data from the input terminal and temporarily storing the raw pixel data after receipt, ensuring the data is complete and continuous before processing. The second storage unit 020 stores the first and second group data updated from the first storage unit 010 via storage signals, ensuring the data is complete and ordered in group form before being transmitted to the first-level circuit 030. The MUX2:1 circuit of the first-level circuit 030 is responsible for selecting and transmitting sub-pixel data to the second-level circuit 040. Through the control of the transmission signals, the MUX2:1 circuit can select either the first and / or third type of pixel data, or the second and / or fourth type of pixel data as needed, ensuring the flexibility and controllability of data transmission. Meanwhile, by optimizing the timing configuration of the control signals, the invalid flipping time during data transmission is reduced, improving data transmission efficiency. The secondary circuit 040 converts the received sub-pixel data into display voltage and outputs it to the AMOLED display. Its main function is to convert digital sub-pixel data into analog display voltage, ensuring the display device can correctly display the image. Furthermore, the grayscale conversion circuit can reduce invalid working time and lower the power consumption of the driver chip by optimizing data transmission and conversion processes, thereby achieving high-quality display effects and excellent performance.

[0053] Figure 5 This is a block diagram illustrating an electronic device according to an embodiment of this application. The electronic device 100 may include a memory 111, a memory controller 112, a processor 113, a peripheral interface 114, an input / output unit 115, and a display unit 116. Those skilled in the art will understand that... Figure 5 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device 100. For example, the electronic device 100 may also include components that are more... Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown.

[0054] The aforementioned memory 111, memory controller 112, processor 113, peripheral interface 114, input / output unit 115, and display unit 116 are electrically connected directly or indirectly to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The aforementioned processor 113 is used to execute executable modules stored in the memory.

[0055] The memory 111 can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. The memory 111 stores programs, and the processor 113 executes these programs upon receiving execution instructions. The methods executed by the electronic device 100 as defined in any embodiment of this application can be applied to or implemented by the processor 113.

[0056] The aforementioned processor 113 may be an integrated circuit chip with signal processing capabilities. The processor 113 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a digital signal processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor.

[0057] The peripheral interface 114 described above couples various input / output devices to the processor 113 and the memory 111. In some embodiments, the peripheral interface 114, the processor 113, and the memory controller 112 can be implemented on a single chip. In other instances, they can be implemented on separate chips.

[0058] The input / output unit 115 described above is used to provide user input data. The input / output unit 115 may be, but is not limited to, a mouse and keyboard, etc.

[0059] The aforementioned display unit 116 provides an interactive interface (e.g., a user interface) between the electronic device 100 and the user, or displays image data for the user's reference. In this embodiment, the display unit can be a liquid crystal display (LCD) or a touch display. If it is a touch display, it can be a capacitive touchscreen or a resistive touchscreen that supports single-point and multi-point touch operations. Supporting single-point and multi-point touch operations means that the touch display can sense touch operations generated simultaneously from one or more locations on the touch display and pass the sensed touch operations to the processor for calculation and processing.

[0060] Please see Figure 6 , Figure 6 This is a schematic diagram of data transmission in one embodiment of this application.

[0061] In one embodiment of this application, taking a driver chip with 1080 source PADs as an example, the 1080 grayscale conversion paths, namely S1-S1080, are divided into high and low groups, where S1-S540 is the low group and S541-S1080 is the high group. Each group contains four types of data: odd number 1, even number 1, odd number 2, and even number 2. In this way, the 1080 grayscale conversion paths, i.e., 2160 data, are divided into eight categories, specifically: low group odd number 1, low group even number 1, low group odd number 2, low group even number 2, high group odd number 1, high group even number 1, high group odd number 2, and high group even number 2. When the group data is updated from LA1 (first storage unit) to LA2 (second storage unit), the data update is controlled by the UPD signal (storage signal). Because the data is divided into 8 categories, each category has its own control signal: UPD_O1_L, UPD_E1_L, UPD_O2_L, UPD_E2_L, UPD_O1_H, UPD_E1_H, UPD_O2_H, UPD_E2_H. When sub-pixel data is transmitted from LA2 through the MUX2:1 circuit to the grayscale conversion circuit, it is controlled by the SEL signal (transmission signal). A high level selects sub-pixel 1 data to be sent to the grayscale conversion circuit, and a low level selects sub-pixel 2 data to be sent to the grayscale conversion circuit. Since LA2 and the grayscale conversion circuit are divided into 8 categories, each category has its own control signal: SEL_O1_L, SEL_E1_L, SEL_O2_L, SEL_E2_L, SEL_O1_H, SEL_E1_H, SEL_O2_H, SEL_E2_H. Figure 6The diagram illustrates the control signals and data transmission for high-level groups Odd 1, Even 1, Odd 2, and Even 2. The low-level groups are processed similarly. When sub-pixel data is updated from LA1 to LA2, the control signals are UPD_O1_L, UPD_E1_L, UPD_O2_L, and UPD_E2_L. When sub-pixel data is transferred from LA2 through the MUX2:1 circuit to the grayscale conversion circuit, the control signals are SEL_O1_L, SEL_E1_L, SEL_O2_L, and SEL_E2_L. Each signal of the same type has a different activation timing and can be configured via registers.

[0062] Please see Figure 7 and Figure 8 , Figure 7 A timing diagram of data transmission in one embodiment of this application is provided; Figure 8 A timing diagram of a conventional method provided in the embodiments of this application.

[0063] first, Figure 7 In the diagram, T0 represents the display time of one row, T1 represents the time interval between each type of control signal, and this interval can be configured via registers to achieve different timing sequences. T2 represents the invalid flipping time of the sub-pixel data output from the MUX2:1 circuit to the grayscale conversion circuit before stabilization. Through eight UPD signals, 2160 sub-pixel data points can be divided into eight different timing points to update from LA1 to LA2. By coordinating the timing of the corresponding SEL control signals, the invalid time T2 is shortened and the number of data points decreases when the sub-pixel data output from the MUX2:1 circuit to the grayscale conversion circuit switches from sub-pixel 2 in the previous row to sub-pixel 1 in the current row. Similarly, the number of invalid data points also decreases within time T3. Time T1 equals the high-level time of the UPD signal multiplied by 7, plus the spacing between UPD signals multiplied by 7. The diagram shows the spacing between the UPD signals, which can be configured via registers to achieve different timing sequences. It should be noted that when the UPD signal is high, the corresponding SEL signal changes from low to high. As each SEL signal transitions from high to low, the values ​​change sequentially. T2 represents the invalid data time before stabilization during the transition from the previous row's sub-pixel 2 data output by the MUX2:1 circuit to the current row's sub-pixel 1 data output. Because sub-pixel data consists of multiple bits, each bit has a different circuit delay. T3 represents the invalid data time before stabilization during the transition from the current row's sub-pixel 1 data output by the MUX2:1 circuit to the current row's sub-pixel 2 data output. Each of the eight data categories has T2 and T3 times, but the timing of T2 and T3 time intervals differs for each category. For example, the T2 time interval for odd-numbered 1 in the lower group occurs before the T2 time interval for odd-numbered 1 in the higher group.

[0064] contrast Figure 8In conventional schemes, grayscale conversion circuits are typically divided into two categories: low-level groups and high-level groups. Taking an original image with a resolution of 1080 as an example, when the MUX2:1 circuit switches from sub-pixel data 1 to sub-pixel data 2, a total of 1080 sub-pixel data are switched within time T3, resulting in 8 times the number of invalid data compared to this scheme. Similarly, when switching from sub-pixel data 2 in the previous row to sub-pixel data 1 in the current row, the number of invalid data is also 8 times that of this scheme within time T2. Furthermore, since the control signal UPD and its corresponding control signal SEL in this scheme have the same timing switching point, this scheme significantly reduces time T2, thereby reducing the time of invalid data flipping.

[0065] In summary, this application provides a display control method, circuit, electronic device, and computer-readable medium. By temporarily storing the raw pixel data in the first storage unit 010, preprocessing and grouping it, and then storing it in the second storage unit 020, the integrity and order of the data are ensured. The second storage unit 020 temporarily stores the grouped data, providing a stable foundation for subsequent data selection and transmission. The first-level circuit 030 selects and transmits the grouped data through transmission signals, ensuring the flexibility and controllability of data transmission. The second-level circuit 040 converts the sub-pixel data into a display voltage output, achieving a high-quality display effect. Throughout the process, by optimizing the timing configuration of data storage, transmission, and conversion, the time for invalid data flipping is reduced, the power consumption of the driver chip is lowered, and the performance and stability of the display control method are improved.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed device can also be implemented in other ways. The device embodiments described above are merely illustrative; for example, the block diagrams in the accompanying drawings illustrate the possible architecture, functions, and operations of the device according to various embodiments of this application. In this regard, each block in the block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram, and combinations of block diagrams, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0067] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0068] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0069] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A display control method, characterized in that, The display control method includes: The data to be converted is stored in the first storage unit, and within the first storage unit, the data to be converted is converted into first grouped data and second grouped data; The storage signal controls the storage of the first group of data and the second group of data into the second storage unit; wherein the storage signal includes: a first storage sub-signal and a second storage sub-signal; The transmission signals control the transmission of the first packet data and the second packet data to the primary circuit; wherein the transmission signals include: a first transmission sub-signal and a second transmission sub-signal; Wherein, the second storage sub-signal is triggered after a preset time period when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are the same; the triggering time points of the second storage sub-signal and the second transmission sub-signal are the same; The display control method further includes: The transmission signal controls the first and second data packets to pass through the first-stage circuit and then transmit the first and second data packets to the second-stage circuit; the second-stage circuit converts the first and second data packets and outputs a display voltage. The first group of data includes a first type of data and a second type of data, and the second group of data includes a third type of data and a fourth type of data. The method of controlling the transmission of the first data packet and the second data packet to the primary circuit via a transmission signal further includes: When the transmission signal is high, the first type of data and / or the third type of data are transmitted to the secondary circuit; When the transmission signal is at a low level, the second type of data and / or the fourth type of data are transmitted to the secondary circuit.

2. The display control method according to claim 1, characterized in that, The step of controlling the storage of the first and second data packets into the second storage unit via a storage signal includes: The first storage sub-signal controls the first group of data to be stored from the first storage unit into the second storage unit; the second storage sub-signal controls the second group of data to be stored from the first storage unit into the second storage unit.

3. The display control method according to claim 1, characterized in that, The step of controlling the transmission of the first and second data packets to the primary circuit via transmission signals includes: The first transmission sub-signal controls the first packet data to be transmitted from the second storage unit to the first-level circuit; the second transmission sub-signal controls the second packet data to be transmitted from the second storage unit to the first-level circuit.

4. The display control method according to claim 1, characterized in that, The step of storing the data to be converted into a first storage unit, and converting the data to be converted into a first group of data and a second group of data within the first storage unit, includes: The raw data is preprocessed to obtain the data to be transformed. The data to be converted is temporarily stored in the first storage unit; After the first storage unit has received all the data to be converted, the data to be converted is divided into the first group of data and the second group of data through the first storage unit.

5. A display control circuit, characterized in that, The display control circuit includes: a first storage unit, a second storage unit, and a primary circuit; The first storage unit is configured to store data to be converted and to receive storage signals to perform corresponding operations; wherein, the storage signals include: a first storage sub-signal and a second storage sub-signal; The first storage unit receives the first storage sub-signal and divides the data to be converted into a first group of data and a second group of data. The second storage unit is configured to receive the transmission signal and then transmit the first packet data and the second packet data to the first-level circuit. The transmission signal includes: a first transmission sub-signal and a second transmission sub-signal; Wherein, the second storage sub-signal is triggered after a preset time period when the first storage sub-signal ends; the triggering time points of the first storage sub-signal and the first transmission sub-signal are the same; the triggering time points of the second storage sub-signal and the second transmission sub-signal are the same; The display control circuit further includes: a secondary circuit; The secondary circuit is configured to receive and convert the first packet data and the second packet data, and then output a display voltage. The first group of data includes a first type of data and a second type of data, and the second group of data includes a third type of data and a fourth type of data. The second storage unit, after receiving the transmission signal, transmits the first packet data and the second packet data to the first-level circuit, and further includes: When the transmission signal is high, the first type of data and / or the third type of data are transmitted to the secondary circuit; When the transmission signal is at a low level, the second type of data and / or the fourth type of data are transmitted to the secondary circuit.

6. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores program instructions, and when the processor executes the program instructions, it performs the steps of the method according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, perform the steps of the method according to any one of claims 1-4.

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