Memory device and preparation method thereof

Abstract

The invention relates to a divisional application of which the application number is 2021111607840. The invention discloses a storage device and a preparation method thereof, and belongs to the technical field of storage, the storage device comprises a first chip and a second chip, the first chip comprises a storage array, and the storage array comprises at least one storage block; the second chip comprises a logic control circuit, the logic control circuit comprises a global bit line decoder, the global bit line decoder is electrically connected with at least one storage block, and a global bit line decoder block formed by constructing the global bit line decoder is located in an overlook projection area of the storage block in the second chip. According to the invention, the area after the first chip and the second chip are stacked can be reduced, so that the occupied area of the memory device is reduced, and the realization of the minimum size of the memory device is facilitated.

Description

[0001] This application is a divisional application of the invention patent with application number "2021111607840", application date "2021.09.30", and name "Memory device and preparation method thereof". Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage device and a method for preparing the same. Background Art

[0003] like Figure 1 As shown, the memory device in the conventional technical solution includes a plurality of memory blocks 510, a plurality of local bit line decoders 520, a plurality of word line decoders 540, a plurality of global bit line decoders 530 and other circuits 550, wherein the construction areas of the memory blocks 510, the construction areas of the local bit line decoders 520, the construction areas of the word line decoders 540, the construction areas of the global bit line decoders 530 and the construction areas of the other circuits 550 do not overlap with each other, for example, the construction area of ​​the local bit line decoders 520 is located on one side of the construction area of ​​the corresponding memory blocks 510, the word line decoders 540 are located on the other side of the construction area of ​​the corresponding local bit line decoders 520 and / or the construction area of ​​the memory blocks 510, and the construction area of ​​the global bit line decoder 530 is located between the construction area of ​​the corresponding local bit line decoders 520 and the construction area of ​​the global bit line decoder 530.

[0004] Specifically, Figure 2 As shown, along a certain direction, the storage blocks 510 and the local bit line decoders 520 are arranged alternately in sequence, and the last local bit line decoder 520 is followed by the global bit line decoder 530 and multiple sense amplifiers 551 in sequence. A word line decoder 540 is arranged on the other side of each storage block 510. Each local bit line decoder 520 is electrically connected to the corresponding storage block 510 and the global bit line decoder 530, and the output end of the global bit line decoder 530 is electrically connected to the corresponding multiple sense amplifiers 551. Similarly, Figure 2 The structural areas of the storage blocks 510, the structural areas of the local bit line decoders 520, the structural areas of the global bit line decoders 530, the structural areas of the sense amplifiers 551, and the structural areas of the word line decoders 540 do not overlap with each other.

[0005] As such, the storage device in the above-mentioned conventional technical solution needs to occupy a relatively large space to integrate the above-mentioned various structures, which is not conducive to minimizing the size of the storage device.

[0006] It should be noted that the above introduction to the background technology is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present application. Therefore, it cannot be considered that the above technical solution is well known to those skilled in the art simply because it appears in the background technology of the present application. Summary of the invention

[0007] The present application provides a memory device and a method for preparing the same, so as to alleviate the technical problem that the memory device needs to occupy a large space.

[0008] In a first aspect, the present application provides a memory device, comprising a first chip and a second chip, the first chip comprising a memory array, the memory array comprising at least one memory block, the memory block comprising a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; the second chip is stacked on top of the first chip along a third direction, the second chip having a top-view projection area of ​​a memory block, the second chip comprising a logic control circuit, the logic control circuit comprising a global bit line decoder, the global bit line decoder being electrically connected to at least one memory block, and a global bit line decoder block formed by the global bit line decoder being located within the top-view projection area.

[0009] In some embodiments, the logic control circuit also includes a local bit line decoder, the local bit line decoder includes a first local bit line sub-decoder, the first local bit line sub-decoder is electrically connected to the storage block and the global bit line decoder, and a first local bit line sub-decoder block formed by the first local bit line sub-decoder is located in the top-view projection area; in the first direction, the projection of the first local bit line sub-decoder block and the projection of the global bit line decoder block do not overlap with each other.

[0010] In some embodiments, the first local bit line sub-decoder includes a first local bit line sub-decoding unit and a second local bit line sub-decoding unit, the first local bit line sub-decoding unit is electrically connected to a portion of the bit line and the global bit line decoder; the second local bit line sub-decoding unit is electrically connected to another portion of the bit line and the global bit line decoder; in a first direction, a projection of a first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit and a projection of a second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit do not overlap with each other; and in a second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

[0011] In some of the embodiments, in a first direction, the length of the global bit line decoder block, the length of the first local bit line sub-decoding unit block, and the length of the second local bit line sub-decoding unit block are all less than or equal to the length of the top-down projection area; and in a second direction, the sum of the width of the global bit line decoder block, the width of the first local bit line sub-decoding unit block, and the width of the second local bit line sub-decoding unit block is less than or equal to the width of the top-down projection area.

[0012] In some embodiments, the logic control circuit further includes a word line decoding circuit, the word line decoding circuit includes a first word line sub-decoder, the first word line sub-decoder is electrically connected to the word line, a first word line sub-decoder block formed by the first word line sub-decoder is located in the top-view projection area, and in the second direction, the first word line sub-decoder block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0013] In some embodiments, the first word line sub-decoder includes a first word line decoding unit and a second word line decoding unit, the first word line decoding unit is electrically connected to a portion of the word line; the second word line decoding unit is electrically connected to another portion of the word line; wherein, in a first direction, a projection of a first word line decoding unit block formed by the first word line decoding unit and a projection of a second word line decoding unit block formed by the second word line decoding unit at least partially overlap; and in a second direction, a projection of the first word line decoding unit block and a projection of the second word line decoding unit block do not overlap each other.

[0014] In some of the embodiments, the logic control circuit further includes a sense amplifier circuit electrically connected to the global bit line decoder, and a sense amplifier circuit block formed by the sense amplifier circuit is located in the top-view projection area; in the first direction, the sense amplifier circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the sense amplifier circuit block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0015] In some embodiments, the sense amplifier circuit includes a first group of sense amplifiers and a second group of sense amplifiers, the first group of sense amplifiers is electrically connected to a global bit line decoder, and the first group of sense amplifiers includes a plurality of sense amplifiers arranged in sequence along a first direction; the second group of sense amplifiers is electrically connected to the global bit line decoder, and the second group of sense amplifiers includes a plurality of sense amplifiers arranged in sequence along the first direction; wherein, in the first direction, a projection of a first group of sense amplifier blocks formed by the first group of sense amplifiers and a projection of a second group of sense amplifier blocks formed by the second group of sense amplifiers at least partially overlap; and in the second direction, a projection of the first group of sense amplifier blocks and a projection of the second group of sense amplifier blocks do not overlap each other.

[0016] In some embodiments, in a first direction, the first word line decoding unit block, the first group of sense amplifier blocks, the second group of sense amplifier blocks, and the second word line decoding unit block are arranged in sequence; in the first direction, the distance from the first group of sense amplifier blocks to the first word line decoding unit block is smaller than the distance from the first group of sense amplifier blocks to the second word line decoding unit block, and the distance from the second group of sense amplifier blocks to the first word line decoding unit block is greater than the distance from the second group of sense amplifier blocks to the second word line decoding unit block.

[0017] In some embodiments, in the first direction, a projection of the first group of sense amplifier blocks overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block, and a projection of the second group of sense amplifier blocks overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block.

[0018] In some of the embodiments, the logic control circuit further includes a plurality of first routing lines, the plurality of first routing lines are electrically connected to the output end of the global bit line decoder and the input end of the plurality of sense amplifiers; in the second direction, the plurality of first routing lines are located between the global bit line decoder block and the sense amplifier circuit block; and the plurality of first routing lines are arranged sequentially along the first direction.

[0019] In some of the embodiments, the logic control circuit also includes multiple second routing lines, which are electrically connected to the input end of the global bit line decoder and the output end of the local bit line decoder; in the first direction, the multiple second routing lines are arranged in sequence; and the multiple second routing lines are located in at least one top-view projection area.

[0020] In some embodiments, the first local bit line sub-decoding unit and the second local bit line sub-decoding unit each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first through silicon via or a pair of first bonding pads.

[0021] In some embodiments, the first word line decoding unit and the second word line decoding unit each have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

[0022] In some embodiments, the first chip includes a first bonding layer, the first bonding layer includes at least one first bonding pad and / or a second bonding pad; the second chip includes a second bonding layer, the second bonding layer includes at least one first bonding pad and / or a second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

[0023] In some embodiments, at least one storage block includes a first storage block to an Nth storage block arranged in sequence along the second direction; when N is an odd number, the global bit line decoder block is located within the top-view projection area of ​​the (N+1) / 2th storage block of the second chip; when N is an even number, the global bit line decoder block is located within the top-view projection area of ​​the N / 2th storage block or the 1+N / 2th storage block of the second chip; wherein N is an integer greater than or equal to 1.

[0024] In a second aspect, the present application provides a method for preparing a memory device, comprising: constructing a memory array on a first chip, the memory array comprising at least one memory block, the memory block comprising a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; constructing a logic control circuit on a second chip, the second chip having a top-view projection area of ​​a memory block, the logic control circuit comprising a global bit line decoder electrically connected to at least one memory block, the global bit line decoder block formed by the global bit line decoder being located within the top-view projection area; and stacking the second chip on top of the first chip along a third direction.

[0025] In some of the embodiments, the preparation method also includes: configuring a local bit line decoder in a logic control circuit, the local bit line decoder including a first local bit line sub-decoder; configuring the first local bit line sub-decoder to be electrically connected to the bit line and the global bit line decoder; and constructing a first local bit line sub-decoder block formed by the first local bit line sub-decoder to be located within a top-view projection area, and in a first direction, a projection of the first local bit line sub-decoder block and a projection of the global bit line decoder block do not overlap with each other.

[0026] In some of the embodiments, the preparation method also includes: configuring the first local bit line sub-decoder to include a first local bit line sub-decoding unit and a second local bit line sub-decoding unit; electrically connecting the first local bit line sub-decoding unit to a portion of the bit line and the global bit line decoder, and electrically connecting the second local bit line sub-decoding unit to another portion of the bit line and the global bit line decoder; and constructing a first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit and a second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit in a top-view projection area; wherein, in a first direction, a projection of the first local bit line sub-decoding unit block and a projection of the second local bit line sub-decoding unit block do not overlap each other; and in a second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

[0027] In some of the embodiments, the preparation method further includes: configuring a word line decoding circuit in a logic control circuit, the word line decoding circuit including a first word line sub-decoder; electrically connecting the first word line sub-decoder to a word line; and constructing a first word line sub-decoder block formed by the first word line sub-decoder within a top-view projection area; wherein, in the second direction, the first word line sub-decoder block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0028] In some of the embodiments, the preparation method also includes: configuring the first word line sub-decoder to include a first word line decoding unit and a second word line decoding unit; electrically connecting the first word line decoding unit to a portion of the word line, and electrically connecting the second word line decoding unit to another portion of the word line; and constructing a projection of a first word line decoding unit block formed by the first word line decoding unit and a projection of a second word line decoding unit block formed by the second word line decoding unit to at least partially overlap in a first direction; and the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap each other in a second direction.

[0029] The memory device and preparation method thereof provided in the present application can reduce the area after the first chip and the second chip are stacked by constructing a global bit line decoder block formed by a global bit line decoder located within the top-view projection area of ​​the memory block in the second chip, thereby reducing the occupied area of ​​the memory device and helping to minimize the size of the memory device.

[0030] Based on the arrangement of the decoder being completely within the projection range and the stacked structure of the two chips, the decoder can be vertically connected to the storage array without the need for additional horizontal wiring, so no wiring space is required between the two sub-modules, which can further reduce the area of ​​the first chip and the second chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0032] Figure 1 A schematic diagram of the distribution of the structures of various parts in a storage device provided by a conventional technical solution.

[0033] Figure 2 Another schematic diagram of the distribution of the various parts of the storage device provided by the traditional technical solution.

[0034] Figure 3 A schematic diagram of the structural distribution of a storage device provided in an embodiment of the present application.

[0035] Figure 4 for Figure 3 Schematic diagram of the structural distribution of the inductive amplifier circuit.

[0036] Figure 5 A schematic diagram of another structural distribution of a storage device provided in an embodiment of the present application.

[0037] Figure 6 A schematic flow chart of a method for preparing a storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0039] In the description of the present disclosure, the word line decoder is also described as X-DEC, and the bit line decoder can be described as a bit line selector, a bit line multiplexer or a Y-MUX, which is used to locate the majority of memory cells in the memory array for further reading and writing operations on the memory cells.

[0040] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating the orientation or position relationship indicated are all based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of simplifying the description of the present disclosure, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0041] In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0042] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include the first feature being in direct contact with the second feature, or may include the first feature being in contact with the second feature not being in direct contact but being in contact through a third feature other than the first feature. Moreover, a first feature being “above”, “above”, and “above” a second feature may include the first feature being directly above and obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may include the first feature being directly below and obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0043] See also Figures 3 to 6 ,like Figure 3 As shown, this embodiment provides a memory device, which includes a first chip 100 and a second chip 200, the first chip 100 includes a memory array 10, the memory array 10 includes at least one memory block, for example, a first memory block 11, a second memory block 12 or an Nth memory block 13, the memory block includes a plurality of word lines extending along a first direction DR1 and a plurality of bit lines extending along a second direction DR2; the second chip 200 is stacked on top of the first chip 100 along a third direction DR3, the second chip 200 has a top-view projection area of ​​a memory block, the second chip 200 includes a logic control circuit, the logic control circuit includes a global bit line decoder 20, the global bit line decoder 20 is electrically connected to at least one memory block, and the global bit line decoder block formed by the global bit line decoder 20 is located in the top-view projection area.

[0044] It can be understood that the memory device provided in this embodiment can reduce the area of ​​the first chip 100 and the second chip 200 after stacking by constructing the global bit line decoder block formed by the global bit line decoder 20 to be located in the top view projection area of ​​the memory block in the second chip 200, thereby reducing the occupied area of ​​the memory device and helping to minimize the size of the memory device. In addition, this stacking structure helps to reduce the connection distance between the logic control circuit and the memory unit.

[0045] The first chip 100 may be one wafer, and the second chip 200 may be another wafer.

[0046] It should be noted that each block in the present application can be understood as the wafer space required to construct the corresponding structure. For example, the top-view projection area can be understood as the space occupied by the storage block, that is, the top-view projection area is formed by the storage block. For another example, the global bit line decoder block can also be understood as the space required to construct the global bit line decoder 20, that is, the global bit line decoder block is formed by the global bit line decoder 20.

[0047] In addition, the storage block in this embodiment can be an independent entity, which can be any storage block in at least one storage block. For example, the storage block can be the first storage block 11, the second storage block 12, or the Nth storage block 13, where N can be any positive integer.

[0048] Therefore, in this embodiment, the global bit line decoder block formed by the global bit line decoder 20 can partially or completely overlap with the construction area of ​​any memory block, which can also reduce the occupied area of ​​the first chip 100 and the second chip 200 after stacking, thereby reducing the occupied space of the memory device and helping to minimize the size of the memory device.

[0049] In one embodiment, in the first direction DR1, the length of the top-view projection area is greater than or equal to the length of the global bit line decoder block. It is understandable that this can maximize the overlap area between the top-view projection area and the global bit line decoder block. The first direction DR1 can be the bit line arrangement direction of the memory array 10.

[0050] In one embodiment, in the second direction DR2, the width of the top-view projection area is greater than the width of the global bit line decoder block. It is understandable that this can further increase the overlapping area between the top-view projection area and the global bit line decoder block. The second direction DR2 can be the word line arrangement direction of the memory array 10.

[0051] In one embodiment, the logic control circuit further includes a local bit line decoder 30, the local bit line decoder 30 includes a first local bit line sub-decoder 30A, the first local bit line sub-decoder 30A is electrically connected to the storage block and the global bit line decoder 20, and the first local bit line sub-decoder block formed by the first local bit line sub-decoder 30A is located in the top view projection area, and in the first direction DR1, the projection of the first local bit line sub-decoder block does not overlap with the projection of the global bit line decoder block.

[0052] It is understandable that by at least partially overlapping the top-view projection area and the first local bit line sub-decoder block, the occupied area of ​​the stacked first chip 100 and the second chip 200 can be further reduced, thereby reducing the occupied space of the memory device and helping to minimize the size of the memory device.

[0053] The first direction DR1 in the present application may also be a horizontal coordinate direction, the second direction DR2 may also be a vertical coordinate direction, and the third direction DR3 may also be a thickness direction of the storage device.

[0054] It should be noted that, in the present embodiment, each storage block is configured with a local bit line sub-decoder, and each storage block includes a corresponding bit line. The local bit line sub-decoder is connected to the bit line of the corresponding storage block, and can be used to simultaneously or time-sharingly control the corresponding bit line to be in an on or off state.

[0055] For example, the first memory block 11 is provided with a first local bit line sub-decoder 30A, the second memory block 12 is provided with a second local bit line sub-decoder 30B, and the Nth memory block 13 is provided with an Nth local bit line sub-decoder 30C.

[0056] In one embodiment, the first local bit line sub-decoder 30A includes a first local bit line sub-decoding unit 31 and a second local bit line sub-decoding unit 32, the first local bit line sub-decoding unit 31 is electrically connected to a portion of the bit line and the global bit line decoder 20; the second local bit line sub-decoding unit 32 is electrically connected to another portion of the bit line and the global bit line decoder 20; in the first direction DR1, the projection of the first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit 31 and the projection of the second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit 32 do not overlap each other; and in the second direction DR2, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

[0057] The first local bit line sub-decoding unit block may be a block formed by any one of the first local bit line sub-decoding unit 31, the third local bit line sub-decoding unit 33, the 2N-1 local bit line sub-decoding unit 35, etc. The second local bit line sub-decoding unit block may be a block formed by any one of the second local bit line sub-decoding unit 32, the fourth local bit line sub-decoding unit 34, the 2N local bit line sub-decoding unit 36, etc.

[0058] It should be noted that, in this embodiment, the first local bit line sub-decoder 30A can be divided into a first local bit line sub-decoder unit 31 and a second local bit line sub-decoder unit 32, which is conducive to minimizing each local bit line sub-decoder, making full use of the fragmented area of ​​the second chip 200, and thus minimizing the area of ​​the second chip 200. At the same time, such a split is more conducive to the layout of the word line decoder, and the word line decoder can also be laid out within the projection range without affecting the routing, thereby further saving area.

[0059] Similarly, the second local bit line sub-decoder 30B configured in the second storage block 12 can also be divided into a third local bit line sub-decoder unit 33 and a fourth local bit line sub-decoder unit 34, so as to be placed in different positions. The Nth local bit line sub-decoder 30C configured in the Nth storage block 13 can also be divided into a 2N-1th local bit line sub-decoder unit 35 and a 2Nth local bit line sub-decoder unit 36, so as to be placed in different positions.

[0060] In one embodiment, the global bit line decoder block may be adjacent to the first local bit line sub-decoding unit block and away from the second local bit line sub-decoding unit block.

[0061] In one embodiment, the top-view projection area or each block may have a specific shape, such as a rectangle, square, circle, or ellipse.

[0062] In some of the embodiments, in the first direction DR1, the length of the global bit line decoder block, the length of the first local bit line sub-decoding unit block, and the length of the second local bit line sub-decoding unit block are all less than or equal to the length of the top-down projection area; and in the second direction DR2, the sum of the width of the global bit line decoder block, the width of the first local bit line sub-decoding unit block, and the width of the second local bit line sub-decoding unit block is less than or equal to the width of the top-down projection area.

[0063] In one embodiment, the logic control circuit further includes a word line decoding circuit 40, the word line decoding circuit 40 includes a first word line sub-decoder 40A, the first word line sub-decoder 40A is electrically connected to the word line, and a first word line sub-decoder block formed by the first word line sub-decoder 40A is located in the top view projection area, and in the second direction DR2, the first word line sub-decoder block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0064] It can be understood that by at least partially overlapping the top-view projection area and the first word line sub-decoder block formed by the first word line sub-decoder 40A, the occupied area of ​​the first chip 100 and the second chip 200 after stacking can be further reduced, thereby reducing the occupied space of the memory device, which helps to minimize the size of the memory device.

[0065] It should be noted that, in this embodiment, each memory block is configured with a word line sub-decoder, each memory block includes a corresponding word line, and the word line sub-decoder is electrically connected to the word line of the corresponding memory block.

[0066] For example, the first memory block 11 is provided with a first word line sub-decoder 40A, the second memory block 12 is provided with a second word line sub-decoder 40B, and the Nth memory block 13 is provided with an Nth word line sub-decoder 40C.

[0067] In one embodiment, the first word line sub-decoder 40A includes a first word line decoding unit 41 and a second word line decoding unit 42, the first word line decoding unit 41 is electrically connected to a portion of the word line; the second word line decoding unit 42 is electrically connected to another portion of the word line; wherein, in the first direction DR1, a projection of a first word line decoding unit block formed by the first word line decoding unit 41 and a projection of a second word line decoding unit block formed by the second word line decoding unit 42 at least partially overlap; and in the second direction DR2, a projection of the first word line decoding unit block and a projection of the second word line decoding unit block do not overlap each other.

[0068] It should be noted that, in the present embodiment, the first word line sub-decoder 40A can be divided into a first word line decoding unit 41 and a second word line decoding unit 42, which is beneficial to minimizing each word line sub-decoder and making full use of the fragmented area of ​​the second chip 200, thereby minimizing the area of ​​the second chip 200.

[0069] Similarly, the second word line sub-decoder 40B configured in the second storage block 12 can also be divided into a third word line decoding unit 43 and a fourth word line decoding unit 44, so as to be placed in different positions. The Nth word line sub-decoder 40C configured in the Nth storage block 13 can also be divided into a 2N-1th word line decoding unit 45 and a 2Nth word line decoding unit 46, so as to be placed in different positions.

[0070] In one embodiment, the logic control circuit further includes a sense amplifier circuit 50, which is electrically connected to the global bit line decoder 20. The sense amplifier circuit block formed by the sense amplifier circuit 50 is located in the top-view projection area. In the first direction DR1, the sense amplifier circuit block is located between the first word line decoding unit block and the second word line decoding unit block, and in the second direction DR2, the sense amplifier circuit block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0071] It is understandable that by at least partially overlapping the top-view projection area and the sensing amplifier circuit block formed by the sensing amplifier circuit 50, the occupied area of ​​the first chip 100 and the second chip 200 after stacking can be further reduced, thereby reducing the occupied space of the memory device, which helps to minimize the size of the memory device.

[0072] like Figure 3 and Figure 4As shown, in one embodiment, the sense amplifier circuit 50 includes a first group of sense amplifiers 51 and a second group of sense amplifiers 52. The first group of sense amplifiers 51 is electrically connected to the global bit line decoder 20. The first group of sense amplifiers 51 includes a plurality of sense amplifiers arranged in sequence along a first direction DR1, such as a sense amplifier 51A, a sense amplifier 51B, a sense amplifier 51C, and a sense amplifier 51D. The second group of sense amplifiers 52 is electrically connected to the global bit line decoder 20. The second group of sense amplifiers 52 includes a plurality of sense amplifiers arranged in sequence along the first direction DR1, such as a sense amplifier 52A, a sense amplifier 52B, a sense amplifier 52C, and a sense amplifier 52D. In the first direction DR1, the projection of a first group of sense amplifier blocks formed by the first group of sense amplifiers 51 and the projection of a second group of sense amplifier blocks formed by the second group of sense amplifiers 52 at least partially overlap. In the second direction DR2, the projection of the first group of sense amplifier blocks and the projection of the second group of sense amplifier blocks do not overlap each other.

[0073] In one embodiment, in a first direction DR1, a first word line decoding unit block, a first group of sense amplifier blocks, a second group of sense amplifier blocks, and a second word line decoding unit block are arranged in sequence; in the first direction DR1, a distance from the first group of sense amplifier blocks to the first word line decoding unit block is smaller than a distance from the first group of sense amplifier blocks to the second word line decoding unit block, and a distance from the second group of sense amplifier blocks to the first word line decoding unit block is greater than a distance from the second group of sense amplifier blocks to the second word line decoding unit block.

[0074] In one embodiment, in the first direction DR1, the projection of the first group of sense amplifier blocks overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block, and the projection of the second group of sense amplifier blocks overlaps with the projection of the first word line decoding unit block and / or the projection of the second word line decoding unit block.

[0075] In one embodiment, the logic control circuit further includes a plurality of first routing lines 70, the plurality of first routing lines 70 are electrically connected to the output end of the global bit line decoder 20 and the input ends of the plurality of sense amplifiers, and in the second direction DR2, the plurality of first routing lines 70 are located between the global bit line decoder block and the sense amplifier circuit block; and the plurality of first routing lines 70 are arranged sequentially along the first direction DR1.

[0076] It should be noted that the multiple first wirings 70 can be located in the same wafer layer as the logic control circuit, which can avoid the multiple first wirings 70 needing to occupy an additional wafer layer, thereby increasing the required thickness of the second chip 200 .

[0077] In one embodiment, the logic control circuit further includes a plurality of second wires 60, the plurality of second wires 60 are electrically connected to the input end of the global bit line decoder 20 and the output end of the local bit line decoder 30, and the plurality of second wires 60 are arranged in sequence in the first direction DR1; and the plurality of second wires 60 are located in at least one top view projection area. It can be understood that one storage block can form a corresponding top view projection area.

[0078] It should be noted that the plurality of second traces 60 and the logic control circuit may be located on a different wafer layer to achieve partial stacking of the two, thereby saving the area required for the second chip 200 .

[0079] The second wiring 60 may be a global bit line.

[0080] In one embodiment, it should be noted that: Figure 3 The structural diagram shown is Figure 5 The difference between the structural diagrams shown is that: Figure 3 In FIG. 1 , the structural regions of the global bit line decoder 20 , the sense amplifier circuit 50 , and the plurality of first wirings 70 all overlap with the structural region of the Nth storage block 13 ; and Figure 5 In the embodiment, the structural areas of the global bit line decoder 20, the sense amplifier circuit 50 and the plurality of first wirings 70 overlap or coincide with the structural area of ​​the second storage block 12. At the same time, the two different configurations also need to change the positions of the connection nodes between the plurality of second wirings 60 and each local bit line sub-decoder and the global bit line decoder 20, as well as the routing paths of the plurality of second wirings 60.

[0081] In one embodiment, at least one storage block includes a first storage block 11 to an Nth storage block 13 arranged in sequence along the second direction DR2; when N is an odd number, the global bit line decoder block is located in the top view projection area of ​​the (N+1) / 2th storage block of the second chip 200; when N is an even number, the global bit line decoder block is located in the top view projection area of ​​the N / 2th storage block or the 1+N / 2th storage block of the second chip 200; wherein N is an integer greater than or equal to 1. It can be understood that the global bit line decoder block storage array 10 can be configured in the middle position in this way.

[0082] In summary, the global bit line decoder block can be located in any top-view projection area. When the global decoder block is located in the top-view projection area of ​​the middle storage block, the overall distance between the global decoder block and other local decoders can be reduced, thereby shortening the routing and reducing the delay.

[0083] In one embodiment, the first local bit line sub-decoding unit 31 and the second local bit line sub-decoding unit 32 each have a plurality of first transmission terminals, and a first transmission terminal is electrically connected to a bit line through a first through silicon via or a pair of first bonding pads.

[0084] In one embodiment, the first word line decoding unit 41 and the second word line decoding unit 42 both have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

[0085] In one embodiment, the first chip 100 includes a first bonding layer, the first bonding layer includes at least one first bonding pad and / or a second bonding pad; the second chip 200 includes a second bonding layer, the second bonding layer includes at least one first bonding pad and / or a second bonding pad; the first bonding pad located in the first bonding layer is bonded to the first bonding pad located in the second bonding layer, and / or the second bonding pad located in the first bonding layer is bonded to the second bonding pad located in the second bonding layer.

[0086] like Figure 6 As shown, in one embodiment, this embodiment provides a method for preparing a memory device, the preparation method comprising the following steps:

[0087] Step S10: constructing a memory array on the first chip, the memory array comprising at least one memory block, the memory block comprising a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction.

[0088] Step S20: construct a logic control circuit on the second chip, the second chip has a top-view projection area of ​​a storage block, the logic control circuit includes a global bit line decoder electrically connected to at least one storage block, and the global bit line decoder block formed by the global bit line decoder is located in the top-view projection area.

[0089] And step S30: stacking the second chip on the first chip along the third direction.

[0090] It can be understood that the preparation method of the memory device provided in this embodiment, by constructing a global bit line decoder block formed by a global bit line decoder located in the top-view projection area of ​​the memory block in the second chip, can reduce the area after the first chip and the second chip are stacked, thereby reducing the occupied area of ​​the memory device and helping to minimize the size of the memory device.

[0091] In one embodiment, the preparation method also includes: configuring a local bit line decoder in a logic control circuit, the local bit line decoder including a first local bit line sub-decoder; configuring the first local bit line sub-decoder to be electrically connected to the bit line and the global bit line decoder; and constructing a first local bit line sub-decoder block formed by the first local bit line sub-decoder to be located within a top-view projection area, and in a first direction, a projection of the first local bit line sub-decoder block and a projection of the global bit line decoder block do not overlap each other.

[0092] It should be noted that, in the first direction, the projection of the first local bit line sub-decoder block and the projection of the global bit line decoder block do not overlap each other. This means that along the first direction, the first local bit line sub-decoder block may have a projection of the first local bit line sub-decoder block, and the global bit line decoder block may have a projection of the global bit line decoder block; and in the first direction, the projection of the first local bit line sub-decoder block and the projection of the global bit line decoder block do not overlap each other on any plane perpendicular to the first direction.

[0093] In one of the embodiments, the preparation method further includes: configuring the first local bit line sub-decoder to include a first local bit line sub-decoding unit and a second local bit line sub-decoding unit; electrically connecting the first local bit line sub-decoding unit to a portion of the bit line and the global bit line decoder, and electrically connecting the second local bit line sub-decoding unit to another portion of the bit line and the global bit line decoder; and constructing a first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit and a second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit in a top-view projection area; wherein, in a first direction, a projection of the first local bit line sub-decoding unit block and a projection of the second local bit line sub-decoding unit block do not overlap each other; and in a second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

[0094] In one embodiment, the preparation method further includes: configuring a word line decoding circuit in a logic control circuit, the word line decoding circuit including a first word line sub-decoder; electrically connecting the first word line sub-decoder and the word line; and constructing a first word line sub-decoder block formed by the first word line sub-decoder in the top view projection area; wherein, in the second direction, the first word line sub-decoder block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

[0095] In one of the embodiments, the preparation method further includes: configuring the first word line sub-decoder to include a first word line decoding unit and a second word line decoding unit; electrically connecting the first word line decoding unit to a portion of the word line, and electrically connecting the second word line decoding unit to another portion of the word line; and constructing a projection of a first word line decoding unit block formed by the first word line decoding unit and a projection of a second word line decoding unit block formed by the second word line decoding unit to overlap at least partially in a first direction; and the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap each other in a second direction.

[0096] It should be noted that the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap each other in the second direction. This means that along the second direction, the first word line decoding unit block may have a projection of the first word line decoding unit block, and the second word line decoding unit block may have a projection of the second word line decoding unit block; and in the second direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap each other on any plane perpendicular to the second direction.

[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] The storage device and the preparation method thereof provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and the core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage device, characterized in that: include: A first chip, wherein the first chip includes a memory array, the memory array includes at least one memory block, and the memory block includes a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; a second chip, stacked on the first chip along a third direction, the second chip having a top-view projection area of ​​the memory block, the second chip comprising a logic control circuit, the logic control circuit comprising a global bit line decoder, a local bit line decoder and a word line decoding circuit, the local bit line decoder comprising a first local bit line sub-decoder, the first local bit line sub-decoder comprising a first local bit line sub-decoding unit and a second local bit line sub-decoding unit; The word line decoding circuit includes a first word line sub-decoder, which is electrically connected to the word line. A first word line sub-decoder block formed by the first word line sub-decoder is located in the top-view projection area, and in the second direction, the first word line sub-decoder block is located between a global bit line decoder block formed by the global bit line decoder and a second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit.

2. The memory device according to claim 1, wherein: In the first direction, a projection of a first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit and a projection of the second local bit line sub-decoding unit block do not overlap each other; and in the second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

3. The memory device according to claim 2, wherein: In the first direction, the length of the global bit line decoder block, the length of the first local bit line sub-decoding unit block, and the length of the second local bit line sub-decoding unit block are all less than or equal to the length of the top-view projection area; and in the second direction, the sum of the width of the global bit line decoder block, the width of the first local bit line sub-decoding unit block, and the width of the second local bit line sub-decoding unit block is less than or equal to the width of the top-view projection area.

4. The memory device according to claim 3, wherein: The first word line sub-decoder comprises: a first word line decoding unit electrically connected to a portion of the word line; a second word line decoding unit electrically connected to another portion of the word line; Wherein, in the first direction, the projection of the first word line decoding unit block formed by the first word line decoding unit and the projection of the second word line decoding unit block formed by the second word line decoding unit at least partially overlap; and in the second direction, the projection of the first word line decoding unit block and the projection of the second word line decoding unit block do not overlap each other.

5. The memory device according to claim 4, wherein: The logic control circuit also includes: A sense amplifier circuit is electrically connected to the global bit line decoder, and a sense amplifier circuit block formed by the sense amplifier circuit is located in the top-view projection area; in the first direction, the sense amplifier circuit block is located between the first word line decoding unit block and the second word line decoding unit block; and in the second direction, the sense amplifier circuit block is located between the global bit line decoder block and the second local bit line sub-decoding unit block.

6. The memory device according to claim 5, characterized in that The inductive amplifier circuit comprises: a first group of sense amplifiers electrically connected to the global bit line decoder, the first group of sense amplifiers comprising a plurality of sense amplifiers sequentially arranged along the first direction; and a second group of sense amplifiers electrically connected to the global bit line decoder, the second group of sense amplifiers comprising a plurality of sense amplifiers sequentially arranged along the first direction; In the first direction, a projection of a first group of sense amplifier blocks formed by the first group of sense amplifiers at least partially overlaps with a projection of a second group of sense amplifier blocks formed by the second group of sense amplifiers; and in the second direction, a projection of the first group of sense amplifier blocks and a projection of the second group of sense amplifier blocks do not overlap with each other.

7. The memory device according to claim 6, wherein: In the first direction, the first word line decoding unit block, the first group of sense amplifier blocks, the second group of sense amplifier blocks, and the second word line decoding unit block are arranged in sequence; in the first direction, a distance from the first group of sense amplifier blocks to the first word line decoding unit block is smaller than a distance from the first group of sense amplifier blocks to the second word line decoding unit block, and a distance from the second group of sense amplifier blocks to the first word line decoding unit block is greater than a distance from the second group of sense amplifier blocks to the second word line decoding unit block.

8. The memory device according to claim 6, wherein: In the first direction, a projection of the first group of sense amplifier blocks overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block, and a projection of the second group of sense amplifier blocks overlaps with a projection of the first word line decoding unit block and / or a projection of the second word line decoding unit block.

9. The memory device according to claim 6, wherein: The logic control circuit also includes: A plurality of first routing lines are electrically connected to the output end of the global bit line decoder and the input ends of the plurality of sense amplifiers; in the second direction, the plurality of first routing lines are located between the global bit line decoder block and the sense amplifier circuit block; and the plurality of first routing lines are arranged in sequence along the first direction.

10. The memory device according to claim 9, wherein: The logic control circuit also includes: A plurality of second routing lines are electrically connected to the input end of the global bit line decoder and the output end of the local bit line decoder; the plurality of second routing lines are arranged in sequence in the first direction; and the plurality of second routing lines are located in at least one of the top-view projection areas.

11. The memory device according to claim 4, wherein: The first local bit line sub-decoding unit and the second local bit line sub-decoding unit each have a plurality of first transmission terminals, and one of the first transmission terminals is electrically connected to one of the bit lines through a first through silicon via or a pair of first bonding pads; The first word line decoding unit and the second word line decoding unit each have a plurality of second transmission terminals, and a second transmission terminal is electrically connected to a word line through a second through silicon via or a pair of second bonding pads.

12. The memory device according to any one of claims 1 to 11, characterized in that: The at least one storage block includes a first storage block to an Nth storage block sequentially arranged along the second direction; When N is an odd number, the global bit line decoder block is located in the top-view projection area of ​​the (N+1) / 2 th storage block in the second chip; When N is an even number, the global bit line decoder block is located in the N / 2th storage block or the 1+N / 2th storage block within the top view projection area of ​​the second chip; Wherein, N is an integer greater than or equal to 1.

13. A method for preparing a memory device, characterized in that: include: Constructing a memory array on a first chip, the memory array comprising at least one memory block, the memory block comprising a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction; Constructing a logic control circuit on a second chip, the second chip having a top-view projection area of ​​the memory block, the logic control circuit comprising a global bit line decoder, a local bit line decoder and a word line decoding circuit, the local bit line decoder comprising a first local bit line sub-decoder, the first local bit line sub-decoder comprising a first local bit line sub-decoding unit and a second local bit line sub-decoding unit, the word line decoding circuit comprising a first word line sub-decoder; as well as stacking the second chip on top of the first chip along a third direction; Among them, the first word line sub-decoder block formed by the first word line sub-decoder is within the top-view projection area; in the second direction, the first word line sub-decoder block is located between the global bit line decoder block formed by the global bit line decoder and the second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit.

14. The preparation method according to claim 13, characterized in that: The preparation method further comprises: configuring the first local bit line sub-decoder to be electrically connected to the bit line and the global bit line decoder; and The first local bit line sub-decoder block formed by constructing the first local bit line sub-decoder is located in the top-view projection area, and in the first direction, the projection of the first local bit line sub-decoder block does not overlap with the projection of the global bit line decoder block.

15. The preparation method according to claim 14, characterized in that: The preparation method further comprises: The first local bit line sub-decoding unit is electrically connected to a portion of the bit lines and the global bit line decoder, and the second local bit line sub-decoding unit is electrically connected to another portion of the bit lines and the global bit line decoder; and Constructing a first local bit line sub-decoding unit block formed by the first local bit line sub-decoding unit and a second local bit line sub-decoding unit block formed by the second local bit line sub-decoding unit within the top-view projection area; In which, in the first direction, the projection of the first local bit line sub-decoding unit block and the projection of the second local bit line sub-decoding unit block do not overlap each other; and in the second direction, the global bit line decoder block is located between the first local bit line sub-decoding unit block and the second local bit line sub-decoding unit block.

16. The preparation method according to claim 15, characterized in that: The preparation method further comprises: configuring the first word line sub-decoder to include a first word line decoding unit and a second word line decoding unit; electrically connecting the first word line decoding unit to a portion of the word lines, and electrically connecting the second word line decoding unit to another portion of the word lines; and A projection of a first word line decoding unit block formed by the first word line decoding unit and a projection of a second word line decoding unit block formed by the second word line decoding unit are constructed to at least partially overlap in the first direction; and a projection of the first word line decoding unit block and a projection of the second word line decoding unit block do not overlap in the second direction.

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