Memory

Abstract

The invention provides a memory, in the memory, for a memory array sheet at a non-head-and-tail position, each bit line is coupled to a corresponding pressure test power supply, and the pressure test power supply corresponding to a first bit line is different from the pressure test power supply corresponding to an adjacent second bit line; for the storage array sheets at the head and tail positions, the first bit lines are coupled to the corresponding pressure test power supplies, and the pressure test power supplies corresponding to the first bit lines with odd numbers are different from the pressure test power supplies corresponding to the first bit lines with even numbers.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a memory. Background Art

[0002] With the development of semiconductor technology, the requirements for the integration degree and performance standards of memories are gradually increasing. Therefore, the internal circuit structure is gradually optimized, and providing a matching test method for the optimized internal circuit structure is also a problem to be solved. Summary of the Invention

[0003] An embodiment of the present disclosure provides a memory.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, the present disclosure provides a memory, which includes N memory array chips arranged in sequence along a first direction, where N is a natural number; each of the memory array chips includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array chips at non-head and non-tail positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array chips at head and tail positions, the first bit lines are electrically connected to the second bit lines adjacent to the first side, and the first bit lines are electrically isolated from the second bit lines adjacent to the second side; the first side and the second side are two opposite sides along the second direction; the memory array chips are numbered along the first direction; and in each of the memory array chips, the first bit lines are numbered along the second direction, and the second bit lines are numbered along the second direction; for the memory array chips at non-head and non-tail positions, each of the bit lines is coupled to a corresponding stress test power supply, and the stress test power supplies corresponding to the first bit lines and the adjacent second bit lines are different; for the memory array chips at head and tail positions, the first bit lines are coupled to corresponding stress test power supplies, and the stress test power supplies corresponding to the first bit lines with odd numbers are different from the stress test power supplies corresponding to the first bit lines with even numbers.

[0006] In some embodiments, for the odd-numbered memory array slices, the first bit line is the second bit line, and for the even-numbered memory array slices, the first bit line is the first bit line; a sense amplifier module is disposed between every two memory array slices, and the sense amplifier module includes a plurality of sense amplifiers arranged in sequence along a second direction; a first end of the sense amplifier is connected to one of the second bit lines on a third side through a first depolarization switch, and a second end of the sense amplifier is connected to one of the second bit lines on the third side through a first isolation switch; the second end of the sense amplifier is further connected to one of the first bit lines on a fourth side through a second depolarization switch, and the first end of the sense amplifier is further connected to one of the first bit lines on the fourth side through a second isolation switch; the third side and the fourth side are two opposite sides along the first direction; a first end or a second end of each sense amplifier is further connected to a precharge power supply through a corresponding precharge switch, so that each bit line is coupled to a precharge power supply.

[0007] In some embodiments, for the memory array slices at non-head and non-tail positions, the precharge power supply to which the bit lines therein are coupled serves as the stress test power supply; for the memory array slices at head and tail positions, the first bit line therein is further coupled to respective edge test power supplies through first test switches, and the edge test power supply to which the first bit line is coupled serves as the stress test power supply.

[0008] In some embodiments, for the memory array slices at non-head and non-tail positions, the bit lines therein are further coupled to respective precharge power supplies through column strobe switches and second test switches; for the memory array slices at head and tail positions, the first bit line therein is further coupled to respective precharge power supplies through column strobe switches and second test switches; for each memory array slice, the precharge power supply to which each bit line is coupled serves as the stress test power supply.

[0009] In some embodiments, for the memory array slices at non-head and non-tail positions, the bit lines therein are further coupled to respective preset test power supplies through column strobe switches and second test switches; for the memory array slices at head and tail positions, the first bit line therein is further coupled to respective preset test power supplies through column strobe switches and second test switches; for each memory array slice, the preset test power supply to which each bit line is coupled serves as the stress test power supply.

[0010] In some embodiments, the sense amplifier modules are numbered along a first direction; for the sense amplifier modules with odd numbers, the first end or the second end of the sense amplifier therein is connected to a first precharge power supply through a corresponding precharge switch; for the sense amplifier modules with even numbers, the first end or the second end of the sense amplifier therein is connected to a second precharge power supply through a corresponding precharge switch, so that the pressure test power supply corresponding to the first bit line is different from the pressure test power supply corresponding to the adjacent second bit line.

[0011] In some embodiments, for the memory array chips at the head and tail positions, the first bit lines with odd numbers are connected to a first edge test power supply via their respective first test switches, and the first bit lines with even numbers are connected to a second edge test power supply via their respective first test switches; or, for the first memory array chip, the first bit lines with odd numbers are connected to a first edge test power supply via their respective first test switches, and the first bit lines with even numbers are connected to a second edge test power supply via their respective first test switches; for the last memory array chip, the first bit lines with odd numbers are connected to the second edge test power supply via their respective first test switches, and the first bit lines with even numbers are connected to the first edge test power supply via their respective first test switches.

[0012] In some embodiments, the memory is configured to control the first edge test power supply to be a first voltage value, the second edge test power supply to be a second voltage value, the first precharge power supply to be a third voltage value, and the second precharge power supply to be a fourth voltage value, and perform a bit line pressure test operation; and control the first edge test power supply to be the second voltage value, the second edge test power supply to be the first voltage value, the first precharge power supply to be the fourth voltage value, and the second precharge power supply to be the third voltage value, and perform the bit line pressure test operation; wherein, the first voltage value is different from the second voltage value, and the third voltage value is different from the fourth voltage value; in the bit line pressure test operation, all the first test switches are in a closed state, the isolation switches and the depolarization switches between the memory array chips at the head and tail positions and the adjacent sense amplifier modules are in an off state, and the remaining isolation switches, the remaining depolarization switches and all the precharge switches are in a closed state.

[0013] In some embodiments, the bit lines in the storage array slices at the head and tail positions are electrically connected to the adjacent sense amplifier modules through the first depolarization switch or the first isolation switch; the memory further includes: a command control circuit configured to generate a test enable signal, an initial isolation signal, and an initial depolarization signal; wherein, when the memory is instructed to perform the bit line stress test operation, the test enable signal, the initial isolation signal, and the initial depolarization signal are all in an active state; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter set and the initial isolation signal; and generate a first edge depolarization signal and a second edge depolarization signal based on the edge test parameter set and the initial depolarization signal; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter set and the initial isolation signal; and generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter set and the initial depolarization signal; wherein all the first test switches are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the sense amplifier modules at the head and tail positions and the adjacent storage array slices are controlled by the first edge isolation signal, the second edge isolation signal, the first edge depolarization signal, and the second edge depolarization signal in one-to-one correspondence; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the sense amplifier modules at non-head and tail positions and the adjacent storage array slices are controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal correspondingly.

[0014] In some embodiments, the edge test parameter group includes a first test parameter and a second test parameter, and the internal test parameter group includes a third test parameter and a fourth test parameter; if the first test parameter is in a first state, the second edge isolation signal and the second edge depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the first test parameter is in a second state, both the second edge isolation signal and the second edge depolarization signal are invalid; if the second test parameter is in a first state, the first edge isolation signal and the first edge depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the second test parameter is in a second state, both the first edge isolation signal and the first edge depolarization signal are invalid; if the fourth test parameter is in a first state, the first internal isolation signal and the first internal depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the fourth test parameter is in a second state, both the first internal isolation signal and the first internal depolarization signal are invalid; if the third test parameter is in a first state, the second internal isolation signal and the second internal depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the third test parameter is in a second state, both the second internal isolation signal and the second internal depolarization signal are invalid; wherein, during the process that the memory is instructed to perform a bit line stress test operation, the second test parameter is in the second state, and the first test parameter, the third test parameter, and the fourth test parameter are all in the first state.

[0015] In some embodiments, the first state is a high level and the second state is a low level; the first preprocessing circuit includes: a first AND gate, whose two input terminals respectively receive the first test parameter and the initial isolation signal, and whose output terminal outputs the second edge isolation signal; a second AND gate, whose two input terminals respectively receive the second test parameter and the initial isolation signal, and whose output terminal outputs the first edge isolation signal; a third AND gate, whose two input terminals respectively receive the first test parameter and the initial depolarization signal, and whose output terminal outputs the second edge depolarization signal; a fourth AND gate, whose two input terminals respectively receive the second test parameter and the initial depolarization signal, and whose output terminal outputs the first edge depolarization signal.

[0016] In some embodiments, the bit lines in the first storage array slice are electrically connected to the adjacent sense amplifier modules through the first depolarization switch or the first isolation switch, and the bit lines in the last storage array slice are electrically connected to the sense amplifier modules at the head and tail positions through the second depolarization switch or the second isolation switch. The memory further includes: a command control circuit configured to generate a test enable signal, an initial isolation signal, and an initial depolarization signal; wherein, when the memory is instructed to perform the stress test operation, the test enable signal, the initial isolation signal, and the initial depolarization signal are all in an active state; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter set and the initial isolation signal; and generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter set and the initial depolarization signal; a third preprocessing circuit configured to generate a first head-end isolation signal and a second head-end isolation signal based on a head-end test parameter set and the initial isolation signal; and generate a first head-end depolarization signal and a second head-end depolarization signal based on the head-end test parameter set and the initial depolarization signal; a fourth preprocessing circuit configured to generate a first tail-end isolation signal and a second tail-end isolation signal based on a tail-end test parameter set and the initial isolation signal; and generate a first tail-end depolarization signal and a second tail-end depolarization signal based on the tail-end test parameter set and the initial depolarization signal; wherein all the first test switches are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the first sense amplifier module and the adjacent storage array slice are respectively controlled by the first head-end isolation signal, the second head-end isolation signal, the first head-end depolarization signal, and the second head-end depolarization signal; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the last sense amplifier module and the adjacent storage array slice are respectively controlled by the first tail-end isolation signal, the second tail-end isolation signal, the first tail-end depolarization signal, and the second tail-end depolarization signal; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the sense amplifier modules at non-head-and-tail positions and the adjacent storage array slices are respectively controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal.

[0017] In some embodiments, the internal test parameter group at least includes a third test parameter and a fourth test parameter; the head-end test parameter group includes a fifth test parameter and a sixth test parameter, and the tail-end test parameter group includes a seventh test parameter and an eighth test parameter; if the third test parameter is in a first state, the second internal isolation signal and the second internal depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the third test parameter is in a second state, the second internal isolation signal and the second internal depolarization signal are both invalid; if the fourth test parameter is in a first state, the first internal isolation signal and the first internal depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the fourth test parameter is in a second state, the first internal isolation signal and the first internal depolarization signal are both invalid; if the fifth test parameter is in a first state, the second head-end isolation signal and the second head-end depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the fifth test parameter is in a second state, the second head-end isolation signal and the second head-end depolarization signal are both invalid; if the sixth test parameter is in a first state, the first head-end isolation signal and the first head-end depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the sixth test parameter is in a second state, the first head-end isolation signal and the first head-end depolarization signal are both invalid; if the seventh test parameter is in a first state, the second tail-end isolation signal and the second tail-end depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the seventh test parameter is in a second state, the second tail-end isolation signal and the second tail-end depolarization signal are both invalid; if the eighth test parameter is in a first state, the first tail-end isolation signal and the first tail-end depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the eighth test parameter is in a second state, the first tail-end isolation signal and the first tail-end depolarization signal are both invalid; wherein, during the process that the memory is instructed to perform a bit line stress test operation, the sixth test parameter and the seventh test parameter are in the second state, and the third test parameter, the fourth test parameter, the fifth test parameter, and the eighth test parameter are all in the first state.

[0018] In some embodiments, the first state is a high level and the second state is a low level; the second preprocessing circuit includes: a fifth AND gate, whose two input terminals respectively receive the third test parameter and the initial isolation signal, and whose output terminal outputs the second internal isolation signal; a sixth AND gate, whose two input terminals respectively receive the fourth test parameter and the initial isolation signal, and whose output terminal outputs the first internal isolation signal; a seventh AND gate, whose two input terminals respectively receive the third test parameter and the initial depolarization signal, and whose output terminal outputs the second internal depolarization signal; an eighth AND gate, whose two input terminals respectively receive the fourth test parameter and the initial depolarization signal, and whose output terminal outputs the first internal depolarization signal.

[0019] In some embodiments, the first state is a high level and the second state is a low level; the third preprocessing circuit includes: a ninth AND gate, whose two input terminals respectively receive the fifth test parameter and the initial isolation signal, and whose output terminal outputs the second head-end isolation signal; a tenth AND gate, whose two input terminals respectively receive the sixth test parameter and the initial isolation signal, and whose output terminal outputs the first head-end isolation signal; an eleventh AND gate, whose two input terminals respectively receive the fifth test parameter and the initial depolarization signal, and whose output terminal outputs the second head-end depolarization signal; a twelfth AND gate, whose two input terminals respectively receive the sixth test parameter and the initial depolarization signal, and whose output terminal outputs the first head-end depolarization signal; the fourth preprocessing circuit includes: a thirteenth AND gate, whose two input terminals respectively receive the seventh test parameter and the initial isolation signal, and whose output terminal outputs the second tail-end isolation signal; a fourteenth AND gate, whose two input terminals respectively receive the eighth test parameter and the initial isolation signal, and whose output terminal outputs the first tail-end isolation signal; a fifteenth AND gate, whose two input terminals respectively receive the seventh test parameter and the initial depolarization signal, and whose output terminal outputs the second tail-end depolarization signal; a sixteenth AND gate, whose two input terminals respectively receive the eighth test parameter and the initial depolarization signal, and whose output terminal outputs the first tail-end depolarization signal.

[0020] In some embodiments, for the memory array chips at non-head and non-tail positions, the bit lines therein are respectively coupled to their respective local data lines via their respective column selection switches; wherein: for the second bit line in the memory array chips at non-head and non-tail positions and with odd numbers and the first bit line in the memory array chips at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are further connected to a first precharge power supply through their respective second test switches; for the first bit line in the memory array chips at non-head and non-tail positions and with odd numbers and the second bit line in the memory array chips at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are further connected to a second precharge power supply through their respective second test switches.

[0021] In some embodiments, for the memory array chips at the head and tail positions, the first bit lines therein are each coupled to a respective local data line via a respective column strobe switch; wherein: for the memory array chips at the head and tail positions, the local data lines coupled to the odd-numbered first bit lines are coupled to a second precharge power supply via the second test switch, and the local data lines coupled to the even-numbered first bit lines are coupled to a first precharge power supply via the second test switch; or, for the first memory array chip, the local data lines coupled to the odd-numbered first bit lines are coupled to a second precharge power supply via the second test switch, and the local data lines coupled to the even-numbered first bit lines are coupled to a first precharge power supply via the second test switch; and, for the last memory array chip, the local data lines coupled to the odd-numbered first bit lines are coupled to a first precharge power supply via the second test switch, and the local data lines coupled to the even-numbered second bit lines are coupled to a first precharge power supply via the second test switch.

[0022] In some embodiments, the memory is configured to control all isolation switches, depolarization switches, and precharge switches to be in an off state, control all column strobe switches and second test switches to be in a closed state, and control the first precharge power supply to be a first voltage value and the second precharge power supply to be a second voltage value to perform a bit line stress test; or, control all isolation switches, depolarization switches, and precharge switches to be in an off state, control all column strobe switches and second test switches to be in a closed state, and control the first precharge power supply to be a second voltage value and the second precharge power supply to be a first voltage value to perform another bit line stress test.

[0023] In some embodiments, for the memory array chips at non-head-and-tail positions, each of the bit lines therein is coupled to a respective local data line via a respective column strobe switch; for the second bit lines in the odd-numbered memory array chips at non-head-and-tail positions and the first bit lines in the even-numbered memory array chips at non-head-and-tail positions, the local data lines coupled thereto are coupled to a first preset test power supply via the second test switch; for the first bit lines in the odd-numbered memory array chips at non-head-and-tail positions and the second bit lines in the even-numbered memory array chips at non-head-and-tail positions, the local data lines coupled thereto are coupled to a second preset test power supply via the second test switch.

[0024] In some embodiments, for the memory array slices at the head and tail positions, the first bit lines therein are each coupled to a respective local data line via a respective column selection switch; wherein: for the memory array slices at the head and tail positions, the local data lines corresponding to the first bit lines with odd numbers are coupled to a second preset test power supply via the second test switch, and the local data lines corresponding to the first bit lines with even numbers are coupled to a first preset test power supply via the second test switch; or, for the first memory array slice, the local data lines corresponding to the first bit lines with odd numbers are coupled to a second preset test power supply via the second test switch, and the local data lines corresponding to the first bit lines with even numbers are coupled to a first preset test power supply via the second test switch; for the last memory array slice, the local data lines corresponding to the first bit lines with odd numbers are coupled to a first preset test power supply via the second test switch, and the local data lines corresponding to the first bit lines with even numbers are coupled to a second preset test power supply via the test switch.

[0025] In some embodiments, the memory is configured to control all isolation switches and depolarization switches to be in an off state, control all precharge switches to be in a closed state, and control the precharge power supply to be a fifth voltage value; control all column selection switches and second test switches to be in a closed state, and control the first preset test power supply to be a first voltage value and the second preset test power supply to be a second voltage value to perform a bit line stress test; control all isolation switches and depolarization switches to be in an off state, control all precharge switches to be in a closed state, and control the precharge power supply to be a fifth voltage value; control all column selection switches and second test switches to be in a closed state, and control the first preset test power supply to be a second voltage value and the second preset test power supply to be a first voltage value to perform another bit line stress test; wherein, the voltage of the fifth voltage value is between the voltage of the first voltage value and the voltage of the second voltage value.

[0026] The embodiments of the present disclosure provide a memory, which reduces the area of the memory array slices at the edge to half of the area of other memory array slices, thereby being able to reduce the area of the chip and improve the integration degree; meanwhile, for this memory, each bit line in the memory array slices at non-head and tail positions is coupled to a stress test power supply, and the first bit lines in the memory array slices at the head and tail positions are coupled to a stress test power supply, which can simultaneously make the adjacent two bit lines in the memory array slices at non-head and tail positions be at different voltages and the first bit lines with odd numbers and the first bit lines with even numbers in the memory array slices at the head and tail positions be at different voltages, and can efficiently implement the bit line stress test, improve the test process of the memory with this structure, and ensure the factory performance. Description of the Drawings

[0027] Figure 1Schematic diagram of a local structure of a DRAM Figure 1 ;

[0028] Figure 2 Schematic diagram of a local structure of a DRAM Figure 2 ;

[0029] Figure 3A Schematic diagram of a local structure of a memory provided by an embodiment of the present disclosure Figure 1 ;

[0030] Figure 3B Schematic diagram of a local structure of a memory provided by an embodiment of the present disclosure Figure 2 ;

[0031] Figure 4 Schematic diagram III of a local structure of a memory provided by an embodiment of the present disclosure;

[0032] Figure 5 Schematic diagram of a local structure of a memory provided by an embodiment of the present disclosure Figure 4 ;

[0033] Figure 6 Schematic diagram of the structure of a sense amplifier provided by an embodiment of the present disclosure;

[0034] Figure 7 Schematic diagram of a local structure of a memory provided by an embodiment of the present disclosure Figure 5 ;

[0035] Figure 8 Schematic diagram of the control part of a memory provided by an embodiment of the present disclosure Figure 1 ;

[0036] Figure 9 Schematic diagram of the control part of a memory provided by an embodiment of the present disclosure Figure 2 ;

[0037] Figure 10 Schematic diagram of a local structure of a memory provided by an embodiment of the present disclosure Figure 6 ;

[0038] Figure 11 Schematic diagram of a local structure of a memory provided by an embodiment of the present disclosure Figure 7 . Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations to the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0040] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0041] If a similar description such as "first / second" appears in the application document, the following explanation shall be added. In the following description, the terms "first / second / third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are for the purpose of describing the embodiments of the present disclosure only and are not intended to limit the present disclosure.

[0043] Taking a Dynamic Random Access Memory (DRAM) as an example, see Figure 1 , which shows a partial structural schematic diagram of a DRAM provided by an embodiment of the present disclosure. As Figure 1 shown, for a DRAM, its core includes a memory array slice (or referred to as a Section), a sense amplifier module, a row decoding and control (XDEC) circuit, a column decoding and control (YDEC) circuit, a secondary sense amplifier (SSa) circuit, and a write driver (Write Driver) circuit. The secondary sense amplifier circuit and the write driver circuit are collectively referred to as the SSa&Write Driver circuit.

[0044] The memory array slice is composed of a large number of memory cells (or referred to as Cells). Data reading, data writing, or data refreshing operations can be performed on the selected memory cells through word lines (Word Line, WL) and bit lines (Bit Line, BL).

[0045] Generally, 65 memory array slices along the first direction can be used as repeatable structures in the memory (for example: memory half bank). Figure 1 Zooming in further, see Figure 2 , the bit lines in each memory array slice (such as 11_1, 11_2... 11_65) are alternately called the first bit line BLa and the second bit line BLb ( Figure 2Only the first bit line BLa and the second bit line BLb of the marked part are shown for illustrative purposes. In particular, for odd-numbered memory array slices (e.g., 11_1, 11_3... 11_65), the first bit line is the second bit line BLb; for even-numbered memory array slices (e.g., 11_2, 11_4... 11_64), the first bit line is the first bit line BLa. In particular, the first bit line BLa and the second bit line BLb are only a division based on position. In fact, the first bit line BLa and the second bit line BLb have exactly the same physical structure.

[0046] A sense amplifier module (e.g., 12_1, 12_2... 12_64) is provided between every two memory array slices. Each sense amplifier module includes a plurality of sense amplifiers (Sense amplifier, Sa). One end of each Sa is connected to the bit line in the memory array slice on one side (e.g., the upper side), and the other end of the Sa is connected to the bit line in the memory array slice on the other side (e.g., the lower side).

[0047] Please refer to Figure 1 and Figure 2 , the word line signal is given by XDEC to turn on the target word line in the memory array slice, and then the column selection signal is given by YDEC to control the corresponding Sa to work, so as to exchange electrical signals with the target bit line, and finally write, read or refresh data to the target memory cell.

[0048] As Figure 2 shown, for the memory array slices at the head and tail positions (Edge), only half of the bit lines can be connected to the adjacent sense amplifier modules, which results in that the other half of the bit lines and their corresponding memory cells are actually unusable. For example, the first bit line BLa in memory array slice 11_1 and memory array slice 11_65 is not connected to the sense amplifier module, causing waste of memory cells and being unfavorable for improving the chip integration.

[0049] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0050] In an embodiment of the present disclosure, refer to Figure 3A or Figure 3B , which shows a partial structural schematic diagram of a memory 10 provided by an embodiment of the present disclosure. As Figure 3A or Figure 3B shown, the memory 10 includes N memory array slices arranged in sequence along a first direction (e.g., 11_1, 11_2... 11_N, that is, the memory array slices are numbered along the first direction). Here, N can be any natural number, Figure 3A taking N as an odd number as an example for illustration, Figure 3B taking N as an even number as an example for illustration.

[0051] Please refer toFigure 3A and Figure 3B Each memory array slice includes a plurality of first bit lines BLa and a plurality of second bit lines BLb, and the first bit lines BLa and the second bit lines BLb are alternately arranged in the second direction; for the memory array slices at non-head and tail positions (such as 11_2... 11_N-1), the first bit line BLa and the adjacent second bit line BLb are electrically isolated; for the memory array slices at head and tail positions (such as 11_1 and 11_N), the first bit line BLa is electrically connected to the second bit line BLb adjacent to the first side (for example, the left side along the second direction), and the first bit line BLa is electrically isolated from the second bit line BLb adjacent to the second side (for example, the right side along the second direction), that is, the first side and the second side are two opposite sides along the second direction.

[0052] Here, the sense amplifier circuit 10 in the embodiments of the present disclosure is applied to various signal amplification scenarios, such as DRAM, Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate DRAM, Low Power DRAM, etc., and those skilled in the art can flexibly apply it.

[0053] It should be noted that for the memory array slices at head and tail positions (11_1, 11_N), since two bit lines are actually connected to form an integral bit line, the length of each bit line can be shortened by nearly half. Specifically, for the memory array slices at non-head and tail positions, the distance between one end of each bit line connected to Sa and the other end of the bit line is denoted as L1, and for the memory array slices at head and tail positions, the distance between one end of the integral bit line (the first bit line + the second bit line) connected to Sa and the other end of the integral bit line is denoted as L2, and L1 = L2.

[0054] Therefore, the area of the memory array slices at head and tail positions (11_1, 11_N) is shortened by nearly half compared with the area of the memory array slices at non-head and tail positions (11_2... 11_N-1), the integration degree of the memory 10 is improved, and the overall area occupied by the storage cells is reduced.

[0055] Please note that as Figure 3A or Figure 3B each memory array slice shows 8 bit lines, but this is only an omitted representation, and actually the number of bit lines in each memory array slice is very large.

[0056] Subsequent illustrations and descriptions will be made with N = 65 for example. For the cases where N is an even number or other values, please make appropriate understanding.

[0057] In particular, bit line stress (BL stress) is an important performance test item for the memory 10. The test method is to apply different voltages to adjacent bit lines and then observe whether the memory cells can operate normally. For Figure 3A or Figure 3B the memory 10 shown, the bit line structures of the memory array chips (11_1, 11_N) at the head and tail positions are different from those of the memory array chips (11_2... 11_N-1) at non-head and tail positions, resulting in the inability to implement BL stress by conventional methods.

[0058] Therefore, the embodiments of the present disclosure also provide a test method for BL stress of the Figure 3A or Figure 3B memory 10 shown.

[0059] For the sake of convenience of description, for Figure 3A or Figure 3B , for the memory array chips with odd numbers (11_1, 11_3, 11_5...), their first bit line is the second bit line BLb; for the memory array chips with even numbers (11_2, 11_4, 11_6...), their first bit line is the first bit line BLa. For each memory array chip, the first bit line BLa therein is sequentially numbered along the second direction, and the second bit line BLb therein is sequentially numbered along the second direction.

[0060] Taking the numbering starting point as an odd number as an example, please refer to Figure 4 (which is shown with N = 65 as an example, and other values of N should be understood adaptively), the bit lines in the memory array chip 11_1 are sequentially: BLbo, BLao, BLbe, BLae along the second direction, and the bit lines in the memory array chip 11_2 are sequentially: BLao, BLbo, BLae, BLbe...

[0061] The embodiments of the present disclosure provide a memory 10. For the memory array chips (11_2, 11_3... 11_64) at non-head and tail positions, each bit line therein is coupled to the corresponding stress test power supply TXo / TXe, and the stress test power supplies corresponding to the first bit line Bla and the adjacent second bit line BLb are different; for example, please refer to Figure 5 , for the memory array chip 11_2, the stress test power supply corresponding to Bla is TXo, and the stress test power supply corresponding to Blb is TXe; for the memory array chip 11_3, the stress test power supply corresponding to Bla is TXe, and the stress test power supply corresponding to Blb is TXo.

[0062] For the memory array chips (11_1, 11_65) at the head and tail positions, the first bit lines therein are all coupled to the corresponding stress test power supplies, and the stress test power supply corresponding to the odd-numbered first bit lines BLao is different from the stress test power supply corresponding to the even-numbered first bit lines BLae. It should be understood that in Figure 5 the first bit line Bla in the memory array chip is specifically coupled to the corresponding stress test power supply through Blb to which it is electrically connected; only taking Figure 5 as an example, the stress test power supply corresponding to Blao is TXe, and the stress test power supply corresponding to Blae is TXo.

[0063] In particular, Figure 5 only as an example, there are more design methods for the stress test power supply in the actual scenario. For example, for the memory array chips at non-head-and-tail positions, all the first bit lines are connected to TXo, and all the second bit lines are connected to Txe.

[0064] Please refer to Figure 5 , there is a sense amplifier module distributed between every two memory array chips, and the sense amplifier modules are numbered along the first direction, that is, the sense amplifier modules are sequentially numbered 12_1, 12_2... 12_64 along the first direction.

[0065] The sense amplifier module includes a plurality of sense amplifiers Sa arranged in sequence along the second direction. For each sense amplifier module, the sense amplifiers are numbered along the second direction. The odd-numbered sense amplifiers Sa are denoted as 40o, and the even-numbered sense amplifiers Sa are denoted as 40e. The structure of each sense amplifier Sa please refer to Figure 6 . As Figure 6 shown, the sense amplifier Sa includes a first transistor 21, a second transistor 22, a third transistor 23, and a fourth transistor 24 connected in cross-coupling. The drains of the first transistor 21 and the third transistor 23 are both connected to the second complementary bit line SaBlb, the drains of the second transistor 22 and the fourth transistor 24 are both connected to the first complementary bit line SaBLa, the gate of the third transistor 23 is connected to the first bit line BLa, and the gate of the fourth transistor 24 is connected to the second bit line BLb; in addition, NCS refers to the pull-down module, and PCS refers to the pull-up module. This part does not affect the understanding of the solution of the present disclosure and will not be further described.

[0066] Please refer to Figure 6, one end of the sense amplifier Sa is connected to a second bit line BLb on the third side (e.g., above along the first direction) through a first depolarization switch 31, and the other end of the sense amplifier Sa is connected to a second bit line BLb on the third side through a first isolation switch 32. The other end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side (e.g., below along the first direction) through a second depolarization switch 33, and the one end of the sense amplifier Sa is also connected to a first bit line BLa on the fourth side through a second isolation switch 34, that is, the third side and the fourth side are two opposite sides along the third direction.

[0067] Exemplarily, the first depolarization switch 31, the second depolarization switch 33, the first isolation switch 32, and the second isolation switch 34 are all transistors.

[0068] One end or the other end of each sense amplifier Sa is also connected to a precharge power supply VAD through a corresponding precharge switch 35. It should be understood that, in Figure 6 , the second bit line BLb is coupled to the precharge power supply VAD through the first depolarization switch 31 and the precharge switch 35, and the first bit line BLa is coupled to the precharge power supply VAD through the second isolation switch 34 and the precharge switch 35, that is, each bit line is coupled to a precharge power supply VAD, and the two bit lines connected to the same sense amplifier share the same precharge power supply VAD.

[0069] In this way, the embodiments of the present disclosure provide a memory, which reduces the area of the storage array chips at the edge to half of the area of other storage array chips, and each bit line of the storage array chip has its own stress test power supply, which can efficiently implement the bit line stress test.

[0070] In the first specific embodiment, for the storage array chips (11_2, 11_3... 11_64) at non-head and non-tail positions, the precharge power supply to which the bit lines are coupled is used as the stress test power supply; however, for the storage array chips (11_1, 11_65) at head and tail positions, the first bit lines are also connected to their respective edge test power supplies through first test switches, and the edge test power supplies to which the first bit lines are coupled are used as the stress test power supplies.

[0071] The following is a specific description.

[0072] Please refer to Figure 7 , the memory 10 includes two groups of precharge power supplies VAD, one group is called the first precharge power supply VAD2O, and the other group is called the second precharge power supply VAD2E; only for the storage array chips (11_2, 11_3... 11_64) at non-head and non-tail positions, the first precharge power supply VAD2O is used as the stress test power supply Txo, and the second precharge power supply VAD2E is used as the stress test power supply Txe.

[0073] On the one hand, asFigure 7 As shown, for the odd-numbered sense amplifier modules (12_1, 12_3... 12_63), one end or the other end of the sense amplifier Sa therein is also connected to the first precharge power supply VAD2O through the precharge switch 35; for the even-numbered sense amplifier modules (12_2, 12_4... 12_64), one end or the other end of the sense amplifier Sa therein is also connected to the second precharge power supply VAD2E through the precharge switch 35, so as to make the pressure test power supply corresponding to the first bit line BLa different from the pressure test power supply corresponding to the adjacent second bit line BLb.

[0074] It should be understood that in Figure 7 , the second end of the odd-numbered sense amplifier 40o is connected to the corresponding precharge power supply through the precharge switch 35, and the first end of the even-numbered sense amplifier 40e is connected to the corresponding precharge power supply through the precharge switch 35, but this does not constitute a corresponding limitation, as long as it is ensured that the precharge power supply corresponding to the sense amplifier Sa in the odd-numbered sense amplifier module is the first precharge power supply VAD2O, and the precharge power supply corresponding to the sense amplifier Sa in the even-numbered sense amplifier module is the second precharge power supply VAD2E.

[0075] On the other hand, the memory 10 further includes two sets of edge test power supplies, one set is called the first edge test power supply VAD2Eedge, and the other set is called the second edge test power supply VAD2Oedge; for the memory array chips (11_1 and 11_65) at the head and tail positions, the first edge test power supply VAD2Eedge is used as the pressure test power supply TXe, and the second edge test power supply VAD2Oedge is used as the pressure test power supply TXo.

[0076] In one case, please refer to Figure 7 , for the memory array chips (11_1, 11_65) at the head and tail positions, the odd-numbered first bit lines BLao are connected to the first edge test power supply VAD2Eedge through their respective first test switches 13, and the even-numbered first bit lines BLae are connected to the second edge test power supply VAD2Oedge through their respective first test switches 13, so as to make the pressure test power supply corresponding to the odd-numbered first bit lines BLao different from the pressure test power supply corresponding to the even-numbered first bit lines BLae.

[0077] In another case, for the first memory array slice 11_1, the odd-numbered first bit lines BLao are connected to the first edge test power supply VAD2Eedge via respective test switches, and the even-numbered first bit lines BLae are connected to the second edge test power supply VAD2Oedge via respective test switches; for the last memory array slice 11_65, the odd-numbered first bit lines BLao are connected to the second edge test power supply VAD2Oedge via respective test switches, and the even-numbered first bit lines BLae are connected to the first edge test power supply VAD2Eedge via respective test switches, so that the test power supplies corresponding to the odd-numbered first bit lines BLao are different from the test power supplies corresponding to the even-numbered first bit lines BLae.

[0078] In this way, adjacent bit lines in the memory array slices at non-head and non-tail positions are connected to different pre-charge power supplies, and the odd-numbered first bit lines BLao and the even-numbered first bit lines BLae in the memory array slices at the head and tail positions are connected to different edge test power supplies, so that the bit line stress test BL stress can be conveniently implemented to ensure the product performance of the memory.

[0079] Based on Figure 7 the above structure, the process of the memory 10 performing BL stress on the memory array slices at non-head and non-tail positions is as follows:

[0080] First, the memory 10 is specifically configured to control the first edge test power supply VAD2Eedge to be a first voltage value, the second edge test power supply VAD2Oedge to be a second voltage value, the first pre-charge power supply VAD2O to be a third voltage value, and the second pre-charge power supply VAD2E to be a fourth voltage value, and perform a bit line stress test operation; wherein, the first voltage value and the second voltage value are different, and the third voltage value and the fourth voltage value are different. For example: the first voltage value is a high level and the second voltage value is a low level, or vice versa; the third voltage value is a high level and the fourth voltage value is a low level, or vice versa.

[0081] At the same time, during the bit line stress test operation, all the first test switches 13 are in the closed state, the isolation switches and the depolarization switches between the memory array slices at the head and tail positions and the adjacent sense amplifying modules are in the off state, and the remaining isolation switches, the remaining depolarization switches and all the pre-charge switches are in the closed state.

[0082] Assume that the first voltage value = the third voltage value = high level, the second voltage value = the fourth voltage value = low level, and taking the Figure 7 memory structure shown as an example for specific description:

[0083] In this way, on the one hand, the isolation switches and depolarization switches between the memory array chips at non-head and non-tail positions and the adjacent sense amplifiers are both in the closed state. Therefore, the bit lines therein are electrically connected to their respective precharge power supplies via the corresponding sense amplifiers. Specifically:

[0084] (1) In the memory array chips at non-head and non-tail positions and with odd numbers (such as memory array chips 11_3, 11_5... 11_63), the first bit line BLa is at a low level (precharged by VAD2E), and the second bit line BLb is at a high level (precharged by VAD2O);

[0085] (2) For the memory array chips at non-head and non-tail positions and with even numbers (such as memory array chips 11_2, 11_4... 11_64), the first bit line BLa is at a high level (precharged by VAD2O), and the second bit line BLb is at a low level (precharged by VAD2E);

[0086] On the other hand, since the isolation switches and depolarization switches between the memory array chips at head and tail positions and the adjacent sense amplifiers are in the off state, the first bit line BLa of the memory array chips at head and tail positions is not connected to the corresponding precharge power supply. However, since all the first test switches 13 are turned on, the first bit line BLa of the memory array chips at head and tail positions is connected to the corresponding test power supply. Specifically:

[0087] (3) For memory array chips 11_1 and 11_65, the first bit line BLao with an odd number and its electrically connected second bit line BLbo are both at a high level (precharged by VAD2Eedge); the first bit line BLa with an even number and its electrically connected second bit line BLb are both at a low level (precharged by VAD2OEdge).

[0088] In this way, by only controlling the voltage values of each power supply terminal and the working states of the corresponding switches, the adjacent bit lines in all memory array chips can be made to be at different level values, thus facilitating the execution of the bit line stress test.

[0089] In some embodiments, the memory 10 is further configured to control the first edge test power supply VAD2Eedge to be a second voltage value, the second edge test power supply VAD2Oedge to be a first voltage value, the first precharge power supply VAD2O to be a fourth voltage value, and the second precharge power supply VAD2E to be a third voltage value, and perform the bit line stress test operation.

[0090] Assume that the first voltage value = the third voltage value = high level, the second voltage value = the fourth voltage value = low level, and taking the Figure 7 shown memory structure as an example for specific description:

[0091] (4) In the storage array slices with odd numbers that are not at the head or tail positions (such as storage array slices 11_3, 11_5... 11_63), the first bit line BLa is at a high level (pre-charged by VAD2E), and the second bit line BLb is at a low level (pre-charged by VAD2O);

[0092] (5) For the storage array slices with even numbers that are not at the head or tail positions (such as storage array slices 11_2, 11_4... 11_64), the first bit line BLa is at a low level (by VAD2O), and the second bit line BLb is at a high level (pre-charged by VAD2E);

[0093] (6) For storage array slices 11_1 and 11_65, the first bit line BLa with an odd number and the second bit line BLb electrically connected to it are both at a low level (pre-charged by VAD2Eedge); the first bit line BLa with an even number and the second bit line BLb electrically connected to it are both at a high level (pre-charged by VAD2OEdge).

[0094] In this way, by dividing the pre-charge power supply into two groups for management and additionally setting a separate test power supply for the bit lines in the storage array slices at the head and tail positions, the bit line stress test can be efficiently implemented.

[0095] To implement the above test method, please refer to Figure 6 , the gates of the first debiasing switch 31 and the second debiasing switch 33 are respectively connected to different control signals OcEnb and OcEna, and the gates of the first isolation switch 32 and the second isolation switch 34 are respectively connected to different control signals Isob and Isoa.

[0096] Combined with Figure 6 and Figure 7 It can be seen that the sense amplifier module 12_1 is connected to the storage array slice 11_1 through the first debiasing switch 31 and the first isolation switch 32, but the sense amplifier module 12_64 is connected to the storage array slice 11_65 through the second debiasing switch 33 and the second isolation switch 34. To more conveniently implement the above test method, in a specific embodiment, by changing certain definitions (such as changing the definitions of the first bit line BLa and the second bit line BLb in the last and the penultimate storage array slices, or changing the definitions of the debiasing switch and the isolation switch in the sense amplifier module 12_64, etc.), the sense amplifier module 12_64 is also connected to the storage array slice 11_65 through the first debiasing switch 31 and the first isolation switch 32.

[0097] That is to say, the bit lines in the memory array slices at the head and tail positions are connected to the adjacent sense amplifier modules through the first depolarization switch 31 or the first isolation switch 32. Thus, only the first depolarization switch 31 and the first isolation switch 32 corresponding to the sense amplifier module 12_1 and the sense amplifier module 12_64 need to be turned off, so that the memory array slices at the head and tail positions are electrically isolated from the adjacent sense amplifiers Sa. At this time, please refer to Figure 7 , the memory 10 further includes a command control circuit ( Figure 8 not shown for the moment), a first preprocessing circuit 50 and a second preprocessing circuit 60. Specifically,

[0098] The command control circuit is configured to generate a test enable signal, an initial isolation signal IsoPre and an initial depolarization signal OcPre; wherein, when the memory 10 is instructed to perform a bit line stress test operation, the test enable signal, the initial isolation signal IsoPre and the initial depolarization signal OcPre are all in an effective state;

[0099] The first preprocessing circuit 50 is configured to generate a first edge isolation signal IsobEdge and a second edge isolation signal IsoaEdge based on the edge test parameter group TmEdge<1:0> and the initial isolation signal IsoPre; and generate a first edge depolarization signal OcEnbEdge and a second edge depolarization signal OcEnaEdge based on the edge test parameter group TmEdge<1:0> and the initial depolarization signal OcPre;

[0100] The second preprocessing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter group TmInter<1:0> and the initial isolation signal IsoPre; and generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter group TmInter<1:0> and the initial depolarization signal OcPre;

[0101] Among them, the test enable signal is used to control all the first test switches 13; meanwhile, (1) the first edge isolation signal IsobEdge is used to control the first isolation switch 32 between the sense amplifier modules at the head and tail positions and the memory array chips at the head and tail positions; (2) the second edge isolation signal IsoaEdge is used to control the second isolation switch 34 between the sense amplifier modules at the head and tail positions and the memory array chips at non-head-and-tail positions; (3) the first edge depolarization signal OcEnbEdge is used to control the first depolarization switch 31 between the sense amplifier modules at the head and tail positions and the memory array chips at the head and tail positions; (4) the second edge depolarization signal OcEnaEdge is used to control the second depolarization switch 33 between the sense amplifier modules at the head and tail positions and the memory array chips at non-head-and-tail positions; (5) the first internal isolation signal IsobInter is used to control the first isolation switch 32 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips; (6) the second internal isolation signal IsoaInter is used to control the second isolation switch 34 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips; (7) the first internal depolarization signal OcEnbInter is used to control the first depolarization switch 31 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips; (8) the second internal depolarization signal OcEnaInter is used to control the second depolarization switch 33 between the sense amplifier modules at non-head-and-tail positions and the adjacent memory array chips.

[0102] In this way, the bit lines in the memory array chips are divided into two categories. During the bit line stress test, the first precharge power supply VAD2O and the second precharge power supply VAD2E are used to charge two consecutive first bit lines BLa and second bit lines BLb in the memory array chips at non-head-and-tail positions respectively, and the first edge test power supply VAD2Eedge and the second edge test power supply VAD2Oedge are used to charge two adjacent first bit lines BLa (and their respective connected second bit lines BLb) in the memory array chips at the head and tail positions respectively, so that the adjacent bit lines of the entire memory array chip are in different voltage states, which can efficiently complete the bit line stress test, save energy consumption and avoid the problems of bit line overcharge and overpressure.

[0103] In a specific embodiment, as Figure 8 shown, the edge test parameter group at least includes a first test parameter TmEdge<0> and a second test parameter TmEdge<1>, and the internal test parameter group at least includes a third test parameter TmInter<0> and a fourth test parameter TmInter<1>.

[0104] If the second test parameter TmEdge<1> is in the first state, the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the second test parameter TmEdge<1> is in the second state, the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge are both invalid;

[0105] If the first test parameter TmEdge<0> is in the first state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the first test parameter TmEdge<0> is in the second state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge are both invalid;

[0106] If the fourth test parameter TmInter<1> is in the first state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the fourth test parameter TmInter<1> is in the second state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter are both invalid;

[0107] If the third test parameter TmInter<0> is in the first state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the third test parameter TmInter<0> is in the second state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter are both invalid.

[0108] During the process when the memory is instructed to perform the bit line stress test operation, the second test parameter TmEdge<1> is in the second state, and the first test parameter TmEdge<0>, the third test parameter TmInter<0>, and the fourth test parameter TmInter<1> are all in the first state.

[0109] It should be noted that for the above isolation signals, depolarization signals, and precharge signals, when they are invalid, the corresponding switches are in the off state; when they are valid, the corresponding switches are in the on state.

[0110] Provide a specific working scenario: The first isolation switch 32, the second isolation switch 34, the first depolarization switch 31, and the second depolarization switch 33 are all N-type field effect transistors. Effective means high level state, and ineffective means low level state.

[0111] Then, during the bit line pressure test operation, TmEdge<1:0> = 01, TmInter<1:0> = 11. Therefore, the first edge isolation signal IsobEdge = the first edge depolarization signal OcEnbEdge = 0, and the second edge isolation signal IsoaEdge = the second edge depolarization signal OcEnaEdge = 1. As a result, the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_65, that is, the bit lines in the memory array chips at the head and tail positions are electrically isolated from the corresponding precharge power supplies; however, the sense amplifier module 12_1 is electrically connected to the memory array chip 11_2, and the sense amplifier module 12_64 is electrically connected to the memory array chip 11_64. The sense amplifier modules 12_2 to 12_63 in the middle part are each electrically connected to the memory array chips on both sides, so that the bit lines in the memory array chips at non-head and tail positions are electrically connected to the corresponding precharge power supplies.

[0112] In the above scenario, please refer to Figure 8 , the first preprocessing circuit 50 includes:

[0113] The first AND gate 501, whose two input terminals respectively receive the first test parameter TmEdge<0> and the initial isolation signal IsoPre, and whose output terminal outputs the second edge isolation signal IsoaEdge;

[0114] The second AND gate 502, whose two input terminals respectively receive the second test parameter TmEdge<1> and the initial isolation signal IsoPre, and whose output terminal outputs the first edge isolation signal IsobEdge;

[0115] The third AND gate 503, whose two input terminals respectively receive the first test parameter TmEdge<0> and the initial depolarization signal OcPre, and whose output terminal outputs the second edge depolarization signal OcEnaEdge;

[0116] The fourth AND gate 504, whose two input terminals respectively receive the second test parameter TmEdge<1> and the initial depolarization signal OcPre, and whose output terminal outputs the first edge depolarization signal OcEnbEdge;

[0117] The second preprocessing circuit 60 includes:

[0118] The fifth AND gate 601 has two input terminals respectively receiving the third test parameter TmInter<0> and the initial isolation signal IsoPre, and its output terminal outputs the second internal isolation signal IsoaInter;

[0119] The sixth AND gate 602 has two input terminals respectively receiving the fourth test parameter TmInter<1> and the initial isolation signal IsoPre, and its output terminal outputs the first internal isolation signal IsobInter;

[0120] The seventh AND gate 603 has two input terminals respectively receiving the third test parameter TmInter<0> and the initial depolarization signal OcPre, and its output terminal outputs the second internal depolarization signal OcEnaInter;

[0121] The eighth AND gate 604 has two input terminals respectively receiving the fourth test parameter TmInter<1> and the initial depolarization signal OcPre, and its output terminal outputs the first internal depolarization signal OcEnbInter.

[0122] In another specific embodiment, please refer to Figure 6 and Figure 7 , the sense amplifier module 12_1 is connected to the memory array chip 11_1 through the first depolarization switch 31 and the first isolation switch 32, but the sense amplifier module 12_64 is connected to the memory array chip 11_65 through the second depolarization switch 33 and the second isolation switch 34.

[0123] That is to say, the bit lines in the first memory array chip 11_1 are electrically connected to the adjacent sense amplifier modules through the first depolarization switch or the first isolation switch, and the bit lines in the last memory array chip 11_65 are electrically connected to the sense amplifier modules at the head and tail positions through the second depolarization switch or the second isolation switch. Please refer to Figure 9 , the memory 10 further includes a command control circuit, a second preprocessing circuit 50, a third preprocessing circuit 70, and a fourth preprocessing circuit 80.

[0124] The command control circuit ( Figure 9 not shown temporarily) is configured to generate a test enable signal, an initial isolation signal IsoPre, and an initial depolarization signal OcPre; wherein, when the memory is instructed to perform a stress test operation, the test enable signal, the initial isolation signal IsoPre, and the initial depolarization signal OcPre are all in an effective state;

[0125] The second preprocessing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter group TmInter<1:0> and the initial isolation signal IsoPre; and generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter group and the initial depolarization signal OcPre.

[0126] The third preprocessing circuit 70 is configured to generate a first head-end isolation signal IsobEdge0 and a second head-end isolation signal IsoaEdge0 based on the head-end test parameter group TmEdge0<1:0> and the initial isolation signal IsoPre; and generate a first head-end depolarization signal OcEnbEdge0 and a second head-end depolarization signal OcEnaEdge0 based on the head-end test parameter group and the initial depolarization signal OcPre.

[0127] The fourth preprocessing circuit 80 is configured to generate a first tail-end isolation signal IsobEdge1 and a second tail-end isolation signal IsoaEdge1 based on the tail-end test parameter group TmEdge1<1:0> and the initial isolation signal IsoPre; and generate a first tail-end depolarization signal OcEnbEdge1 and a second tail-end depolarization signal OcEnaEdge1 based on the tail-end test parameter group and the initial depolarization signal OcPre.

[0128] Among them, all the test switches 13 are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the first read amplification module 11_1 and the adjacent memory array chip are controlled by the first head-end isolation signal IsobEdge0, the second head-end isolation signal IsoaEdge0, the first head-end depolarization signal OcEnbEdge0, and the second head-end depolarization signal OcEnaEdge0 respectively; the first isolation switch 31, the second isolation switch 33, the first depolarization switch 32, and the second depolarization switch 34 between the last read amplification module 11_65 and the adjacent memory array chip are controlled by the first tail-end isolation signal IsobEdge1, the second tail-end isolation signal IsoaEdge1, the first tail-end depolarization signal OcEnbEdge1, and the second tail-end depolarization signal respectively; the first isolation switch 31, the second isolation switch 33, the first depolarization switch 32, and the second depolarization switch 34 between the read amplification modules (11_2, 11_3... 11_64) at non-head and non-tail positions and the adjacent memory array chip are controlled by the first internal isolation signal IsobInter, the second internal isolation signal IsoaInter, the first internal depolarization signal OcEnbInter, and the second internal depolarization signal OcEnaInter respectively.

[0129] In some embodiments, the internal test parameter group includes at least a third test parameter TmInter<0> and a fourth test parameter TmInter<1>; the head-end test parameter group includes a fifth test parameter TmEdge0<0> and a sixth test parameter TmEdge0<1>, and the tail-end test parameter group includes a seventh test parameter TmEdge1<0> and an eighth test parameter TmEdge1<1>;

[0130] If the third test parameter TmInter<0> is in the first state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the third test parameter TmInter<0> is in the second state, both the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter are invalid;

[0131] If the fourth test parameter TmInter<1> is in the first state, the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the fourth test parameter TmInter<1> is in the second state, both the first internal isolation signal IsobInter and the first internal depolarization signal OcEnbInter are invalid;

[0132] If the fifth test parameter TmEdge0<0> is in the first state, the second head-end isolation signal IsoaEdge0 and the second head-end depolarization signal OcEnaEdge0 respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the fifth test parameter TmEdge0<0> is in the second state, both the second head-end isolation signal IsoaEdge0 and the second head-end depolarization signal OcEnaEdge0 are invalid;

[0133] If the sixth test parameter TmEdge0<1> is in the first state, the first head-end isolation signal IsobEdge0 and the first head-end depolarization signal OcEnbEdge0 respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the sixth test parameter TmEdge0<1> is in the second state, both the first head-end isolation signal IsobEdge0 and the first head-end depolarization signal OcEnbEdge0 are invalid;

[0134] If the seventh test parameter TmEdge1<0> is in the first state, the second tail-end isolation signal IsoaEdge1 and the second tail-end depolarization signal OcEnaEdge1 respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the seventh test parameter TmEdge1<0> is in the second state, the second tail-end isolation signal IsoaEdge1 and the second tail-end depolarization signal OcEnaEdge1 are both invalid;

[0135] If the eighth test parameter TmEdge1<1> is in the first state, the first tail-end isolation signal IsobEdge1 and the first tail-end depolarization signal OcEnbEdge1 respectively have the same levels as the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the eighth test parameter TmEdge1<1> is in the second state, the first tail-end isolation signal IsobEdge1 and the first tail-end depolarization signal OcEnbEdge1 are both invalid;

[0136] Among them, during the process when the memory is instructed to perform the bit line stress test operation, the sixth test parameter TmEdge0<1> and the seventh test parameter TmEdge1<0> are in the second state, and the third test parameter TmInter<0>, the fourth test parameter TmInter<1>, the fifth test parameter TmEdge0<0>, and the eighth test parameter TmEdge1<1> are all in the first state.

[0137] Specifically, during the execution of the bit line stress test operation, TmEdge0<1:0> = 01, TmInter<1:0> = 11, TmEdge1<1:0> = 10. Therefore, the sense amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the sense amplifier module 12_64 is electrically isolated from the memory array chip 11_65. However, the sense amplifier module 12_1 is electrically connected to the memory array chip 11_2, and the sense amplifier module 12_64 is electrically connected to the memory array chip 11_64; the sense amplifier modules 12_2 to 12_63 are each electrically connected to the memory array chips on both sides; thus, the bit lines in the memory array chips at non-head and tail positions can all be precharged by the precharge power supply, but the bit lines in the memory array chips at head and tail positions cannot all be precharged by the precharge power supply, but are charged via the edge test power supply.

[0138] In the above scenario, at this time, the structure of the second preprocessing circuit 60 is also as Figure 8 shown and will not be elaborated

[0139] Please refer to Figure 9 , the third preprocessing circuit 70 includes:

[0140] The ninth AND gate 701 has its two input terminals respectively receiving the fifth test parameter TmEdge0<0> and the initial isolation signal IsoPre, and its output terminal outputs the second head-end isolation signal IsoaEdge0;

[0141] The tenth AND gate 702 has its two input terminals respectively receiving the sixth test parameter TmEdge0<1> and the initial isolation signal IsoPre, and its output terminal outputs the first head-end isolation signal IsobEdge0;

[0142] The eleventh AND gate 703 has its two input terminals respectively receiving the fifth test parameter TmEdge0<0> and the initial depolarization signal OcPre, and its output terminal outputs the second head-end depolarization signal OcEnaEdge0;

[0143] The twelfth AND gate 704 has its two input terminals respectively receiving the sixth test parameter TmEdge0<1> and the initial depolarization signal OcPre, and its output terminal outputs the first head-end depolarization signal OcEnbEdge0;

[0144] In this scenario, please refer to Figure 8 , the fourth preprocessing circuit 80 includes:

[0145] The thirteenth AND gate 801 has its two input terminals respectively receiving the seventh test parameter TmEdge1<0> and the initial isolation signal IsoPre, and its output terminal outputs the second tail-end isolation signal IsoaEdge1;

[0146] The fourteenth AND gate 802 has its two input terminals respectively receiving the eighth test parameter TmEdge1<1> and the initial isolation signal IsoPre, and its output terminal outputs the first tail-end isolation signal IsobEdge1;

[0147] The fifteenth AND gate 803 has its two input terminals respectively receiving the seventh test parameter TmEdge1<0> and the initial depolarization signal OcPre, and its output terminal outputs the second tail-end depolarization signal OcEnaEdge1;

[0148] The sixteenth AND gate 804 has its two input terminals respectively receiving the eighth test parameter TmEdge1<1> and the initial depolarization signal OcPre, and its output terminal outputs the first tail-end depolarization signal OcEnbEdge1.

[0149] In summary, the embodiment of the present disclosure provides a memory, which reduces the area of the memory array chips located at the edge to half of the area of other memory array chips; at the same time, divides the precharge power supply into two groups for management, and separately sets a dedicated edge test power supply for the bit lines in the memory array chips at the head and tail positions, which can efficiently implement the bit line stress test, improve the test process of the memory with this structure, and ensure the factory performance.

[0150] In the second specific embodiment, for the memory array slices (11_2, 11_3... 11_64) at non-head and non-tail positions, the bit lines therein are also coupled to their respective precharge power supplies through column selection switches and second test switches; for the memory array slices (11_1, 11_65) at head and tail positions, the first bit line therein is also coupled to its respective precharge power supply through a column selection switch and a second test switch. That is to say, only when both the column selection switch and the second test switch are turned on, the first bit line is electrically connected to its own precharge power supply. For each memory array slice, the precharge power supply coupled to each bit line is used as a stress test power supply.

[0151] The following is a specific description.

[0152] Please refer to Figure 10 , the memory 10 includes two groups of precharge power supplies, namely the first precharge power supply VAD2O and the second precharge power supply VAD2E.

[0153] Meanwhile, in one possibility, for all memory array slices, each bit line is coupled to the first precharge power supply VAD2O through its respective precharge switch 35. However, one type of bit lines is connected to the first precharge power supply VAD2O through a column selection switch + a second test switch, and the other type of bit lines is connected to the second precharge power supply VAD2E through a column selection switch + a second test switch. In this way, during the stress test, the precharge switch 35 is turned off, and both the column selection switch and the second test switch are turned on, so that (in the internal array slice) two adjacent bit lines (or two consecutive first bit lines in the head and tail array slices) are precharged by the first precharge power supply VAD2O and the second precharge power supply VAD2E respectively; during normal operation, the precharge switch 35 is turned on, the second test switch is turned off, and all bit lines are precharged by the first precharge power supply VAD2O, thus realizing the normal precharge function.

[0154] Similarly, in another possibility, for all memory array slices, each bit line is coupled to the second precharge power supply VAD2E through its respective precharge switch 35; or, in still another possibility, some bit lines are coupled to the first precharge power supply VAD2O through their respective precharge switches 35, and the remaining bit lines are coupled to the second precharge power supply VAD2E through their respective precharge switches 35, such as the situation described in the previous embodiment.

[0155] Please refer to Figure 6 and Figure 10, each bit line is coupled to the corresponding precharge power supply through the precharge switch 35, and is also coupled to the precharge power supply through the column select switch 38 + the second test switch 14; at the same time, during the stress test, the precharge switch 35 is turned off, while the column select switch 38 + the second test switch 14 are both closed. At this time, the first precharge power supply VAD2O and the second precharge power supply VAD2E can be used as the stress test power supplies TXo and TXe respectively.

[0156] Specifically, for the memory array chips (11_2, 11_3... 11_64) at non-head and non-tail positions, the bit lines therein are all coupled to their respective local data lines (IO / ION) through their respective column select switches 38; where: (1) For the second bit line BLb in the memory array chips with odd numbers (11_3, 11_5... 11_63) at non-head and non-tail positions and the first bit line BLa in the memory array chips with even numbers (11_2, 11_4... 11_64), the local data lines to which they are coupled are also connected to the first precharge power supply VAD2O through their respective second test switches 14; (2) For the first bit line BLa in the memory array chips with odd numbers (11_3, 11_5... 11_63) at non-head and non-tail positions and the second bit line BLb in the memory array chips with even numbers (11_2, 11_4... 11_65), the local data lines to which they are coupled are also connected to the second precharge power supply VAD2E through their respective second test switches 14.

[0157] At the same time, for the memory array chips (11_1, 11_65) at head and tail positions, the first bit lines therein are all coupled to their respective local data lines through their respective column select switches.

[0158] In one case, please refer to Figure 10 , (1) For the memory array chips (11_1, 11_65) at head and tail positions, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the second precharge power supply VAD2E through the second test switch 14, and the local data lines coupled to the even-numbered second bit lines BLae are coupled to the first precharge power supply VAD2O through the second test switch 14.

[0159] In another case, for the first memory array chip 11_1, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the second precharge power supply VAD2E through the second test switch 14, and the local data lines coupled to the even-numbered first bit lines BLae are coupled to the first precharge power supply VAD2O through the second test switch 14; and for the last memory array chip 11_65, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the first precharge power supply VAD2O through the second test switch 14, and the local data lines coupled to the even-numbered first bit lines BLae are coupled to the second precharge power supply VAD2E through the second test switch 14.

[0160] Briefly speaking, for the memory array chips at the head and tail positions, the precharge power supply to which the first bit line is connected via the precharge switch 35 and the precharge power supply to which the first bit line is connected via the column select switch 38 + the second test switch 14 may not be the same precharge power supply. Assume that in one case, all the first bit lines BLa in the memory array chip 11_1 are connected to the first precharge power supply VAD2O through the precharge switch 35, but Bla0 in the memory array chip 11_1 is coupled to the second precharge power supply VAD2E via the column select switch 38 + the second test switch 14, and Blae is coupled to the first precharge power supply VAD2O via the column select switch 38 + the second test switch 14. This is just one possible case. At the same time, during the bit line stress test, all the bit lines are connected to the corresponding precharge power supply through the column select switch 38 + the second test switch 14, but the precharge switch is closed; in the normal precharge operation, all the bit lines are connected to the corresponding precharge power supply through the precharge switch, but the column select switch 38 + the second test switch 14 is closed.

[0161] Based on Figure 10 the above structure, the process of the memory 10 performing BL stress on the memory array chips at non-head and non-tail positions is as follows:

[0162] The memory 10 is configured to control all the isolation switches, depolarization switches, and precharge switches to be in the off state, control all the column select switches and the second test switches to be in the closed state, and control the first precharge power supply to be a first voltage value and the second precharge power supply to be a second voltage value to perform a bit line stress test;

[0163] In this way, during the bit line stress test, all the bit lines are connected to the corresponding precharge power supply through the column select switch 38 + the second test switch 14. Assume that the first voltage value = the third voltage value = high level (e.g., 1.55V), and the second voltage value = the fourth voltage value = low level (e.g., 0V). Please refer to Figure 10 for details:

[0164] (1) In the non-head and non-tail position and odd-numbered memory array chips (such as memory array chips 11_3, 11_5... 11_63), the first bit line BLa is all at low level (precharged by VAD2E), and the second bit line BLb is all at high level (precharged by VAD2O);

[0165] (2) For the non-head and non-tail position and even-numbered memory array chips (such as memory array chips 11_2, 11_4... 11_64), the first bit line BLa is all at high level (precharged by VAD2O), and the second bit line BLb is all at low level (precharged by VAD2E);

[0166] (3) For the storage array chips 11_1 and 11_65, the first bit line BLao with odd numbers and the second bit line BLbo electrically connected thereto are both at low level (pre-charged by VAD2E); the first bit line BLa with even numbers and the second bit line BLb electrically connected thereto are both at high level (pre-charged by VAD2O).

[0167] In addition, the memory 10 is further configured to control all isolation switches, depolarization switches, and pre-charge switches to be in the off state, control all column select switches and second test switches to be in the closed state, and control the first pre-charge power supply to be the second voltage value and the second pre-charge power supply to be the first voltage value to perform another bit line stress test.

[0168] Assume that the first voltage value = the third voltage value = high level, and the second voltage value = the fourth voltage value = low level. Please refer to Figure 10 , specifically:

[0169] (4) In the storage array chips with odd numbers at non-head and non-tail positions (such as storage array chips 11_3, 11_5... 11_63), the first bit line BLa is at high level (pre-charged by VAD2E), and the second bit line BLb is at low level (pre-charged by VAD2O);

[0170] (5) In the storage array chips with even numbers at non-head and non-tail positions (such as storage array chips 11_2, 11_4... 11_64), the first bit line BLa is at low level (pre-charged by VAD2O), and the second bit line BLb is at high level (pre-charged by VAD2E);

[0171] (6) For the storage array chips 11_1 and 11_65, the first bit line BLao with odd numbers and the second bit line BLbo electrically connected thereto are both at high level (pre-charged by VAD2E); the first bit line BLa with even numbers and the second bit line BLb electrically connected thereto are both at low level (pre-charged by VAD2O).

[0172] The embodiment of the present disclosure provides a memory. Each bit line is further connected to a pre-charge power supply through a column select switch and a second test switch to be used as a stress test power supply. On the one hand, it can efficiently implement the bit line stress test, improve the test process of the memory with this structure, and ensure the factory performance; on the other hand, there is no need to set 2 groups of separate edge test power supplies for the storage array chips at the head and tail positions, reducing the circuit area.

[0173] In the third specific embodiment, for the memory array chips (11_2, 11_3... 11_64) at non-head and non-tail positions, the bit lines therein are also coupled to their respective preset test power supplies through the column selection switches 38 and the second test switches 14; for the memory array chips (11_1, 11_65) at the head and tail positions, the first bit lines therein are also coupled to their respective preset test power supplies through the column selection switches and the second test switches; for each memory array chip, the preset test power supply coupled to each bit line is used as the stress test power supply.

[0174] That is to say, in addition to the precharge power supply, the memory 10 is also provided with two sets of preset test power supplies, namely the first preset test power supply Vintlp2o and the second preset test power supply Vintlp2o, which are used as the stress test power supplies TXo and TXe respectively.

[0175] The following is a specific description.

[0176] Please refer to Figure 6 and Figure 11 , for the memory array chips (11_2, 11_3... 11_64) at non-head and non-tail positions, each bit line therein is coupled to its respective local data line (IO / ION) through its respective column selection switch 38; (1) for the second bit line BLb in the memory array chips (11_3, 11_5... 11_63) at non-head and non-tail positions and with odd numbers and the first bit line BLa in the memory array chips (11_2, 11_4... 11_64) at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are coupled to the first preset test power supply Vintlp2o through the second test switch 14; (2) for the first bit line BLa in the memory array chips (11_3, 11_5... 11_63) at non-head and non-tail positions and with odd numbers and the second bit line BLb in the memory array chips (11_2, 11_4... 11_65) at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are coupled to the second preset test power supply Vintlp2e through the second test switch 14.

[0177] Meanwhile, for the memory array chips (11_1, 11_65) at the head and tail positions, the first bit lines therein are all coupled to their respective local data lines through their respective column selection switches; where:

[0178] In one case, please refer to Figure 11 , (1) for the memory array chips (11_1, 11_65) at the head and tail positions, the local data lines to which the odd-numbered first bit lines BLao are coupled are coupled to the second preset test power supply Vintlp2e through the second test switch 14, and the local data lines to which the even-numbered second bit lines BLae are coupled are coupled to the first preset test power supply Vintlp2o through the second test switch 14.

[0179] In another case, for the first memory array slice 11_1, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the second preset test power supply Vintlp2e via the second test switch 14, and the local data lines coupled to the even-numbered first bit lines BLae are coupled to the first preset test power supply Vintlp2o via the second test switch 14; and, for the last memory array slice 11_65, the local data lines coupled to the odd-numbered first bit lines BLao are coupled to the first preset test power supply Vintlp2o via the second test switch 14, and the local data lines coupled to the even-numbered first bit lines BLae are coupled to the second preset test power supply Vintlp2e via the second test switch 14.

[0180] Exemplarily, the first preset test power supply can use the precharge power supply of the local data line IO, and the second preset test power supply can use the precharge power supply of the local data line ION, without adding an additional independent power supply, saving circuit area.

[0181] Based on Figure 11 the structure, the process of the memory 10 performing BL stress on the memory array slices at non-head and non-tail positions is as follows:

[0182] The memory 10 is configured to control all isolation switches and depolarization switches to be in the off state, control all precharge switches to be in the closed state, and control the precharge power supply VAD to be the fifth voltage value; control all column selection switches and second test switches to be in the closed state, and control the first preset test power supply to be the first voltage value and the second preset test power supply to be the second voltage value to perform a bit line stress test.

[0183] It should be noted that the voltage of the fifth voltage value is between the voltage of the first voltage value and the voltage of the second voltage value. In this way, the first voltage value can be a high level (e.g., 1.55V), the second voltage value is a low level (e.g., 0V)), and the fifth voltage value can be 0.5V. Thus, during the bit line stress test, via the precharge switch 38, the pull-up unit NCS and the pull-down unit PCS are precharged to 0.5V by the precharge power supply VAD, so that the sense amplifier SA will not be over-stressed.

[0184] Under the above voltage conditions, as Figure 11 shown,

[0185] (1) Among the non-head and non-tail positions and odd-numbered memory array slices (such as memory array slices 11_3, 11_5... 11_63), the first bit lines BLa are all at a low level (precharged by Vintlp2e), and the second bit lines BLb are all at a high level (precharged by Vintlp2o);

[0186] (2) For the even-numbered memory array slices at non-head and non-tail positions (such as memory array slices 11_2, 11_4... 11_64), the first bit line BLa is at a high level (pre-charged by Vintlp2o), and the second bit line BLb is at a low level (pre-charged by Vintlp2e);

[0187] (3) For memory array slices 11_1 and 11_65, the odd-numbered first bit line BLao and the second bit line BLbo electrically connected thereto are at a low level (pre-charged by Vintlp2e); the even-numbered first bit line BLae and the second bit line BLbe electrically connected thereto are at a high level (pre-charged by Vintlp2o).

[0188] In addition, the memory 10 is further configured to control all isolation switches and depolarization switches to be in an off state, control all pre-charge switches to be in a closed state, and control the pre-charge power supply to be a fifth voltage value; control all column selection switches and second test switches to be in a closed state, and control the first preset test power supply to be a second voltage value and the second preset test power supply to be a first voltage value to perform another bit line stress test;

[0189] Assume that the first voltage value = the third voltage value = high level, the second voltage value = the fourth voltage value = low level, and the fifth voltage value = 0.5V. Please refer to Figure 11 , specifically:

[0190] (4) For the odd-numbered memory array slices at non-head and non-tail positions (such as memory array slices 11_3, 11_5... 11_63), the first bit line BLa is at a high level (pre-charged by Vintlp2e), and the second bit line BLb is at a low level (pre-charged by Vintlp2o);

[0191] (5) For the even-numbered memory array slices at non-head and non-tail positions (such as memory array slices 11_2, 11_4... 11_64), the first bit line BLa is at a low level (pre-charged by Vintlp2o), and the second bit line BLb is at a high level (pre-charged by Vintlp2e);

[0192] (6) For memory array slices 11_1 and 11_65, the odd-numbered first bit line BLao and the second bit line BLbo electrically connected thereto are at a high level (pre-charged by Vintlp2e); the even-numbered first bit line BLa and the second bit line BLb electrically connected thereto are at a low level (pre-charged by Vintlp2o).

[0193] Briefly speaking, during the bit line stress test, all bit lines are connected to the corresponding preset test power supply through the column select switch 38 + the second test switch 14, and at the same time, the precharge switch is turned on, so that the pull-up module PCS and the pull-down module NCS are approximately 0.5V, avoiding excessive stress on the sense amplifier SA; in the conventional precharge operation, all bit lines are connected to the corresponding precharge power supply through the precharge switch, but the column select switch 38 + the second test switch 14 is turned off.

[0194] The embodiment of the present disclosure provides a memory, which reduces the area of the memory array chips located at the edge to half of the area of other memory array chips. In addition to the precharge power supply, two groups of preset test power supplies are provided, which can efficiently implement the bit line stress test, improve the test process of the memory with this structure, and ensure the factory performance.

[0195] In another embodiment of the present disclosure, a test method is provided. This test method is applied to the aforementioned memory 10, which includes N memory array chips arranged in sequence along the first direction. The memory array chips include a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along the second direction; for the memory array chips at non-head and non-tail positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array chips at the head and tail positions, the first bit lines are electrically connected to the second bit lines adjacent to the first side and the first bit lines are electrically isolated from the second bit lines adjacent to the second side.

[0196] For the convenience of description, the memory array chips are numbered along the first direction. For the memory array chips with odd numbers, the first bit line of each is the second bit line; for the memory array chips with even numbers, the first bit line of each is the first bit line; for each memory array chip, the first bit lines therein are numbered in sequence along the second direction, and the second bit lines therein are numbered in sequence along the second direction.

[0197] The method includes:

[0198] S901: During the process of performing the bit line stress test operation, for the memory array chips at the head and tail positions, each first bit line is charged with the stress test power supply corresponding to each first bit line; and for the memory array chips at non-head and non-tail positions, each bit line is charged with the stress test power supply corresponding to each bit line; the above is carried out simultaneously.

[0199] Among them, for the memory array chips at the head and tail positions, the voltage of the stress test power supply corresponding to the first bit lines with odd numbers is different from the voltage of the stress test power supply corresponding to the first bit lines with even numbers; for the memory array chips at non-head and non-tail positions, the voltage of the stress test power supply corresponding to the first bit lines therein is different from the voltage of the stress test power supply corresponding to the adjacent second bit lines.

[0200] In summary, for the aforementioned memory 10, the embodiments of the present disclosure further provide a test method. Through one step, adjacent bit lines of all memory array chips can be at different voltages, enabling efficient bit line stress testing, improving the test process of the memory with this structure, and ensuring the performance at the time of factory shipment.

[0201] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element.

[0202] The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0203] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, the memory includes N memory array slices arranged in sequence along a first direction, where N is a natural number; each memory array slice includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices at non-head and non-tail positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array slices at head and tail positions, the first bit lines are electrically connected to the second bit lines adjacent to the first side, and the first bit lines are electrically isolated from the second bit lines adjacent to the second side; the first side and the second side are two opposite sides along the second direction; number the memory array slices along the first direction; and in each memory array slice, number the first bit lines along the second direction and number the second bit lines along the second direction; for the memory array slices at non-head and non-tail positions, each bit line therein is coupled to a corresponding stress test power supply, and the stress test power supply corresponding to the first bit line and the stress test power supply corresponding to the adjacent second bit line are different; for the memory array slices at head and tail positions, the first bit lines therein are coupled to corresponding stress test power supplies, and the stress test power supplies corresponding to the first bit lines with odd numbers are different from the stress test power supplies corresponding to the first bit lines with even numbers.

2. The memory according to claim 1, characterized in that, the first bit line of the memory array slices with odd numbers is a second bit line, and the first bit line of the memory array slices with even numbers is a first bit line; a sense amplifier module is distributed between every two memory array slices, and the sense amplifier module includes a plurality of sense amplifiers arranged in sequence along the second direction; a first end of the sense amplifier is connected to a second bit line on a third side through a first depolarization switch, and a second end of the sense amplifier is connected to a second bit line on the third side through a first isolation switch; the second end of the sense amplifier is further connected to a first bit line on a fourth side through a second depolarization switch, and the first end of the sense amplifier is further connected to a first bit line on the fourth side through a second isolation switch; the third side and the fourth side are two opposite sides along the first direction; a first end or a second end of each sense amplifier is further connected to a precharge power supply through a corresponding precharge switch, so that each bit line is coupled to a precharge power supply.

3. The memory according to claim 2, characterized in that, for the memory array slices at non-head and non-tail positions, the precharge power supply to which the bit lines therein are coupled is used as the stress test power supply; for the memory array slices at head and tail positions, the first bit lines are further coupled to respective edge test power supplies through first test switches, and the edge test power supplies to which the first bit lines are coupled are used as the stress test power supplies.

4. The memory according to claim 2, characterized in that, for the memory array slices at non-head and non-tail positions, the bit lines therein are further coupled to their respective precharge power supplies through column strobe switches and second test switches; For the memory array chips at the head and tail positions, the first bit line is also coupled to the respective precharge power supplies through column select switches and second test switches; For each of the memory array chips, the precharge power supply coupled to each bit line is used as the stress test power supply.

5. The memory according to claim 2, wherein, For the memory array chips at non-head and non-tail positions, the bit lines are also coupled to respective preset test power supplies through column select switches and second test switches; For the memory array chips at the head and tail positions, the first bit line is also coupled to the respective preset test power supplies through column select switches and second test switches; For each of the memory array chips, the preset test power supply coupled to each bit line is used as the stress test power supply.

6. The memory according to claim 3, wherein, The sense amplifier modules are numbered in the first direction; For the sense amplifier modules with odd numbers, the first end or the second end of the sense amplifier is connected to the first precharge power supply through the corresponding precharge switch; for the sense amplifier modules with even numbers, the first end or the second end of the sense amplifier is connected to the second precharge power supply through the corresponding precharge switch, so that the stress test power supply corresponding to the first bit line is different from the stress test power supply corresponding to the adjacent second bit line.

7. The memory according to claim 6, wherein, For the memory array chips at the head and tail positions, the first bit lines with odd numbers are connected to the first edge test power supply through their respective first test switches, and the first bit lines with even numbers are connected to the second edge test power supply through their respective first test switches; Or, For the first memory array chip, the first bit lines with odd numbers are connected to the first edge test power supply through their respective first test switches, and the first bit lines with even numbers are connected to the second edge test power supply through their respective first test switches; for the last memory array chip, the first bit lines with odd numbers are connected to the second edge test power supply through their respective first test switches, and the first bit lines with even numbers are connected to the first edge test power supply through their respective first test switches.

8. The memory according to claim 7, wherein, The memory is configured to control the first edge test power supply to be a first voltage value, the second edge test power supply to be a second voltage value, the first precharge power supply to be a third voltage value, the second precharge power supply to be a fourth voltage value, and perform a bit line stress test operation; And, Control the first edge test power supply to be the second voltage value, the second edge test power supply to be the first voltage value, the first precharge power supply to be the fourth voltage value, the second precharge power supply to be the third voltage value, and perform the bit line stress test operation; wherein, the first voltage value is different from the second voltage value, and the third voltage value is different from the fourth voltage value; In the bit line stress test operation, all the first test switches are in the closed state, the isolation switches and the depolarization switches between the memory array chips at the head and tail positions and the adjacent sense amplifying modules are in the off state, and the remaining isolation switches, the remaining depolarization switches and all the precharge switches are in the closed state.

9. The memory according to claim 8, wherein, the bit lines in the memory array chips at the head and tail positions are electrically connected to the adjacent sense amplifying modules through the first depolarization switch or the first isolation switch; the memory further includes: a command control circuit configured to generate a test enable signal, an initial isolation signal and an initial depolarization signal; wherein, when the memory is instructed to perform the bit line stress test operation, the test enable signal, the initial isolation signal and the initial depolarization signal are all in an effective state; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter set and the initial isolation signal; and generate a first edge depolarization signal and a second edge depolarization signal based on the edge test parameter set and the initial depolarization signal; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter set and the initial isolation signal; and generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter set and the initial depolarization signal; wherein, all the first test switches are controlled by the test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the sense amplifying modules at the head and tail positions and the adjacent memory array chips are respectively controlled by the first edge isolation signal, the second edge isolation signal, the first edge depolarization signal, and the second edge depolarization signal; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the sense amplifying modules at non-head and non-tail positions and the adjacent memory array chips are respectively controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal.

10. The memory according to claim 9, wherein, the edge test parameter set includes a first test parameter and a second test parameter, and the internal test parameter set includes a third test parameter and a fourth test parameter; if the first test parameter is in a first state, the second edge isolation signal and the second edge depolarization signal are respectively the same as the initial isolation signal and the initial depolarization signal in level; if the first test parameter is in a second state, the second edge isolation signal and the second edge depolarization signal are both invalid; If the second test parameter is in the first state, the first edge isolation signal and the first edge depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the second test parameter is in the second state, the first edge isolation signal and the first edge depolarization signal are both invalid. If the fourth test parameter is in the first state, the first internal isolation signal and the first internal depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid. If the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal respectively have the same levels as the initial isolation signal and the initial depolarization signal; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid. Wherein, during the process that the memory is instructed to perform the bit line stress test operation, the second test parameter is in the second state, and the first test parameter, the third test parameter and the fourth test parameter are all in the first state.

11. The memory according to claim 10, wherein, the first state is a high level, and the second state is a low level; the first preprocessing circuit includes: a first AND gate, whose two input terminals respectively receive the first test parameter and the initial isolation signal, and whose output terminal outputs the second edge isolation signal; a second AND gate, whose two input terminals respectively receive the second test parameter and the initial isolation signal, and whose output terminal outputs the first edge isolation signal; a third AND gate, whose two input terminals respectively receive the first test parameter and the initial depolarization signal, and whose output terminal outputs the second edge depolarization signal; a fourth AND gate, whose two input terminals respectively receive the second test parameter and the initial depolarization signal, and whose output terminal outputs the first edge depolarization signal.

12. The memory according to claim 8, wherein, the bit lines in the first storage array slice are electrically connected to the adjacent sense amplifier modules through the first depolarization switch or the first isolation switch, and the bit lines in the last storage array slice are electrically connected to the sense amplifier modules at the head and tail positions through the second depolarization switch or the second isolation switch. The memory further includes: a command control circuit configured to generate a test enable signal, an initial isolation signal and an initial depolarization signal; wherein, when the memory is instructed to perform the stress test operation, the test enable signal, the initial isolation signal and the initial depolarization signal are all in an effective state; a second preprocessing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal; and generate a first internal depolarization signal and a second internal depolarization signal based on the internal test parameter group and the initial depolarization signal. The third preprocessing circuit is configured to generate a first head-end isolation signal and a second head-end isolation signal based on the head-end test parameter group and the initial isolation signal; and generate a first head-end depolarization signal and a second head-end depolarization signal based on the head-end test parameter group and the initial depolarization signal; The fourth preprocessing circuit is configured to generate a first tail-end isolation signal and a second tail-end isolation signal based on the tail-end test parameter group and the initial isolation signal; and generate a first tail-end depolarization signal and a second tail-end depolarization signal based on the tail-end test parameter group and the initial depolarization signal; Wherein, all the first test switches are controlled by a test enable signal, and the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the first read amplification module and the adjacent memory array chip are controlled by the first head-end isolation signal, the second head-end isolation signal, the first head-end depolarization signal, and the second head-end depolarization signal respectively; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the last read amplification module and the adjacent memory array chip are controlled by the first tail-end isolation signal, the second tail-end isolation signal, the first tail-end depolarization signal, and the second tail-end depolarization signal respectively; the first isolation switch, the second isolation switch, the first depolarization switch, and the second depolarization switch between the read amplification modules at non-head and non-tail positions and the adjacent memory array chips are controlled by the first internal isolation signal, the second internal isolation signal, the first internal depolarization signal, and the second internal depolarization signal respectively.

13. The memory according to claim 12, wherein, the internal test parameter group at least includes a third test parameter and a fourth test parameter; the head-end test parameter group includes a fifth test parameter and a sixth test parameter, and the tail-end test parameter group includes a seventh test parameter and an eighth test parameter; if the third test parameter is in the first state, the second internal isolation signal and the second internal depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the third test parameter is in the second state, the second internal isolation signal and the second internal depolarization signal are both invalid; if the fourth test parameter is in the first state, the first internal isolation signal and the first internal depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal depolarization signal are both invalid; if the fifth test parameter is in the first state, the second head-end isolation signal and the second head-end depolarization signal are respectively at the same levels as the initial isolation signal and the initial depolarization signal; if the fifth test parameter is in the second state, the second head-end isolation signal and the second head-end depolarization signal are both invalid; If the sixth test parameter is in the first state, the first head-end isolation signal and the first head-end depolarization signal respectively have the same level as the initial isolation signal and the initial depolarization signal; if the sixth test parameter is in the second state, the first head-end isolation signal and the first head-end depolarization signal are both invalid. If the seventh test parameter is in the first state, the second tail-end isolation signal and the second tail-end depolarization signal respectively have the same level as the initial isolation signal and the initial depolarization signal; if the seventh test parameter is in the second state, the second tail-end isolation signal and the second tail-end depolarization signal are both invalid. If the eighth test parameter is in the first state, the first tail-end isolation signal and the first tail-end depolarization signal respectively have the same level as the initial isolation signal and the initial depolarization signal; if the eighth test parameter is in the second state, the first tail-end isolation signal and the first tail-end depolarization signal are both invalid. Wherein, during the process that the memory is instructed to perform the bit line stress test operation, the sixth test parameter and the seventh test parameter are in the second state, and the third test parameter, the fourth test parameter, the fifth test parameter, and the eighth test parameter are all in the first state.

14. The memory according to claim 10 or 13, characterized in that the first state is a high level, and the second state is a low level; the second preprocessing circuit includes: a fifth AND gate, whose two input terminals respectively receive the third test parameter and the initial isolation signal, and whose output terminal outputs the second internal isolation signal; a sixth AND gate, whose two input terminals respectively receive the fourth test parameter and the initial isolation signal, and whose output terminal outputs the first internal isolation signal; a seventh AND gate, whose two input terminals respectively receive the third test parameter and the initial depolarization signal, and whose output terminal outputs the second internal depolarization signal; an eighth AND gate, whose two input terminals respectively receive the fourth test parameter and the initial depolarization signal, and whose output terminal outputs the first internal depolarization signal.

15. The memory according to claim 13, characterized in that the first state is a high level, and the second state is a low level; the third preprocessing circuit includes: a ninth AND gate, whose two input terminals respectively receive the fifth test parameter and the initial isolation signal, and whose output terminal outputs the second head-end isolation signal; a tenth AND gate, whose two input terminals respectively receive the sixth test parameter and the initial isolation signal, and whose output terminal outputs the first head-end isolation signal; an eleventh AND gate, whose two input terminals respectively receive the fifth test parameter and the initial depolarization signal, and whose output terminal outputs the second head-end depolarization signal; a twelfth AND gate, whose two input terminals respectively receive the sixth test parameter and the initial depolarization signal, and whose output terminal outputs the first head-end depolarization signal; the fourth preprocessing circuit includes: a thirteenth AND gate, whose two input terminals respectively receive the seventh test parameter and the initial isolation signal, and whose output terminal outputs the second tail-end isolation signal; The fourteenth AND gate, with its two input terminals respectively receiving the eighth test parameter and the initial isolation signal, and its output terminal outputting the first tail-end isolation signal; The fifteenth AND gate, with its two input terminals respectively receiving the seventh test parameter and the initial depolarization signal, and its output terminal outputting the second tail-end depolarization signal; The sixteenth AND gate, with its two input terminals respectively receiving the eighth test parameter and the initial depolarization signal, and its output terminal outputting the first tail-end depolarization signal.

16. The memory according to claim 4, wherein, for the memory array chips at non-head and non-tail positions, the bit lines therein are all coupled to their respective local data lines via their respective column selection switches; wherein: for the second bit lines in the memory array chips at non-head and non-tail positions and with odd numbers, and the first bit lines in the memory array chips at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are also connected to the first pre-charge power supply through their respective second test switches; for the first bit lines in the memory array chips at non-head and non-tail positions and with odd numbers, and the second bit lines in the memory array chips at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are also connected to the second pre-charge power supply through their respective second test switches.

17. The memory according to claim 16, wherein, for the memory array chips at head and tail positions, the first bit lines therein are all coupled to their respective local data lines via their respective column selection switches; wherein: for the memory array chips at head and tail positions, the local data lines to which the odd-numbered first bit lines are coupled are coupled to the second pre-charge power supply via the second test switch, and the local data lines to which the even-numbered first bit lines are coupled are coupled to the first pre-charge power supply via the second test switch; alternatively, for the first memory array chip, the local data lines to which the odd-numbered first bit lines are coupled are coupled to the second pre-charge power supply via the second test switch, and the local data lines to which the even-numbered first bit lines are coupled are coupled to the first pre-charge power supply via the second test switch; and for the last memory array chip, the local data lines to which the odd-numbered first bit lines are coupled are coupled to the first pre-charge power supply via the second test switch, and the local data lines to which the even-numbered second bit lines are coupled are coupled to the first pre-charge power supply via the second test switch.

18. The memory according to claim 17, wherein, the memory is configured to control all isolation switches, depolarization switches, and pre-charge switches to be in the off state, control all column selection switches and second test switches to be in the closed state, and control the first pre-charge power supply to be a first voltage value and the second pre-charge power supply to be a second voltage value to perform a bit line stress test; or, control all isolation switches, depolarization switches, and pre-charge switches to be in the off state, control all column selection switches and second test switches to be in the closed state, and control the first pre-charge power supply to be the second voltage value and the second pre-charge power supply to be the first voltage value to perform another bit line stress test.

19. The memory according to claim 5, wherein, For the memory array slices at non-head and non-tail positions, each of the bit lines therein is coupled to a respective local data line via a respective column strobe switch; For the second bit line in the memory array slices at non-head and non-tail positions and with odd numbers, and the first bit line in the memory array slices at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are coupled to a first preset test power supply via the second test switch; For the first bit line in the memory array slices at non-head and non-tail positions and with odd numbers, and the second bit line in the memory array slices at non-head and non-tail positions and with even numbers, the local data lines to which they are coupled are coupled to a second preset test power supply via the second test switch.

20. The memory according to claim 19, wherein, For the memory array slices at head and tail positions, the first bit lines therein are each coupled to a respective local data line via a respective column strobe switch; wherein: For the memory array slices at head and tail positions, the local data lines corresponding to the first bit lines with odd numbers are coupled to a second preset test power supply via the second test switch, and the local data lines corresponding to the first bit lines with even numbers are coupled to a first preset test power supply via the second test switch; Alternatively, for the first memory array slice, the local data lines corresponding to the first bit lines with odd numbers are coupled to a second preset test power supply via the second test switch, and the local data lines corresponding to the first bit lines with even numbers are coupled to a first preset test power supply via the second test switch; for the last memory array slice, the local data lines corresponding to the first bit lines with odd numbers are coupled to a first preset test power supply via the second test switch, and the local data lines corresponding to the first bit lines with even numbers are coupled to a second preset test power supply via the test switch.

21. The memory according to claim 20, wherein, The memory is configured to control all isolation switches and depolarization switches to be in an off state, control all precharge switches to be in a closed state, and control the precharge power supply to be a fifth voltage value; control all column strobe switches and second test switches to be in a closed state, and control the first preset test power supply to be a first voltage value and the second preset test power supply to be a second voltage value to perform a bit line stress test once; Control all isolation switches and depolarization switches to be in an off state, control all precharge switches to be in a closed state, and control the precharge power supply to be a fifth voltage value; control all column strobe switches and second test switches to be in a closed state, and control the first preset test power supply to be a second voltage value and the second preset test power supply to be a first voltage value to perform another bit line stress test; wherein the voltage of the fifth voltage value is between the voltage of the first voltage value and the voltage of the second voltage value.

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