Forming air gaps between bit lines in semiconductor device

Abstract

Systems, apparatuses, and methods are provided for forming air gaps between bit lines in a semiconductor device. In one aspect, a semiconductor device includes a memory array of memory cells and a bit line coupled to the memory array. Adjacent ones of the bit lines are separated by isolation regions in a first direction. The isolation region extends in a second direction perpendicular to the first direction. The isolation region includes an air gap. In the second direction, an end of the air gap is over an adjacent end of a bit line of the adjacent bit lines.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. BACKGROUND

[0002] Semiconductor memory devices can be classified as non-volatile memory devices (e.g., flash memory devices) and volatile memory devices (e.g., dynamic random access memory, DRAM). Semiconductor memory devices can have various structures to increase the density of memory cells and lines on a chip. Memory devices typically include a memory array of memory cells and a control circuit to facilitate operation of the memory array. SUMMARY

[0003] The present disclosure describes methods, apparatuses, systems, and techniques for forming an air gap between adjacent bit lines in a semiconductor device.

[0004] One aspect of the present invention features a semiconductor device including a memory array of memory cells and bit lines coupled to the memory array. Adjacent ones of the bit lines are separated by an isolation region along a first direction. The isolation region extends along a second direction perpendicular to the first direction. The isolation region includes an air gap. Along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines.

[0005] In some embodiments, a memory cell of the memory cells includes a transistor and a capacitor. The transistor includes a transistor body, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, the transistor body extending along the second direction. The first terminal of the transistor is coupled to the capacitor. The second terminal of the transistor is coupled to a corresponding one of the bit lines.

[0006] In some embodiments, along the second direction, a distance between the end of the air gap and an end of the gate structure is greater than a distance between the adjacent end of the bit line and the end of the gate structure.

[0007] In some embodiments, the air gap is surrounded by an isolation material.

[0008] In some embodiments, the isolation material includes a low-k porous dielectric material.

[0009] In some embodiments, the low-k porous dielectric material has a dielectric constant in a range from about 1.5 to about 3.5.

[0010] In some embodiments, along the second direction, the end of the air gap is a height away from the adjacent end of the bit line of the adjacent bit lines. A ratio of the height to a width of the isolation region along the first direction is in a range from about 0 to about 0.8.

[0011] In some implementations, the height is in a range from about 3 nm to about 10 nm.

[0012] In some implementations, the air gap includes a first portion and a second portion arranged along the second direction. A width of the air gap along the first direction in the first portion is less than a width of the air gap along the first direction in the second portion.

[0013] In some implementations, a width of the air gap along the first direction gradually decreases toward an end of the air gap in the first portion of the air gap.

[0014] In some implementations, a ratio of a maximum width of the air gap along the first direction to a width of the isolation region along the first direction is greater than 0.6.

[0015] In some implementations, a ratio of a height of the air gap along the second direction to a width of the isolation region along the first direction is in a range from about 2 to about 5.

[0016] In some implementations, an aspect ratio of the air gap between a height of the air gap along the second direction and a width of the air gap is greater than or equal to 3.

[0017] Another aspect of the disclosure features a method including forming bit lines separated by a dielectric material. Etching the dielectric material between adjacent ones of the bit lines to form a trench between the adjacent bit lines along a first direction. Forming an isolation region in the trench between the adjacent bit lines. The isolation region extends along a second direction perpendicular to the first direction. The isolation region includes an air gap surrounded by an isolation material. Along the second direction, an end of the air gap is above adjacent ends of ones of the bit lines.

[0018] In some implementations, forming the isolation region in the trench between the adjacent bit lines includes introducing a gaseous mixture of a porous connecting material and oxygen gas into a reaction chamber.

[0019] In some implementations, the isolation region between the adjacent bit lines is formed using plasma-enhanced chemical vapor deposition (PECVD).

[0020] In some implementations, forming the isolation region in the trench between the adjacent bit lines includes controlling a size of the air gap by adjusting a concentration of the porous connecting material.

[0021] In some implementations, the method further includes forming a capacitor and a transistor. The transistor includes a transistor body, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, the transistor body extending along the second direction. The first terminal of the transistor is coupled to the capacitor. The second terminal of the transistor is coupled to a corresponding one of the bit lines.

[0022] In some embodiments, along the second direction, a distance between an end of the air gap and an end of the gate structure is greater than a distance between adjacent ends of the bit lines and the end of the gate structure.

[0023] Another aspect of the disclosure features a system including a memory device configured to store data and a memory controller coupled to the memory device and configured to operate the memory device. The memory device includes a memory array of memory cells and bit lines coupled to the memory array. Adjacent ones of the bit lines are separated by an isolation region along a first direction. The isolation region extends along a second direction perpendicular to the first direction. The isolation region includes an air gap. Along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines.

[0024] The details of one or more implementations of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the relevant art(s) to make and use the disclosure.

[0026] Figure 1 A cross-sectional view of an example 3D semiconductor device is shown.

[0027] Figure 2 A cross-sectional view of an example air gap between bit lines is shown.

[0028] Figures 3A-3B Cross-sectional views of a portion of an example semiconductor device during various stages of a fabrication process are shown.

[0029] Figures 4A-4B A cross-sectional view of an example air gap between bit lines is shown.

[0030] Figure 5 An example process for forming an example semiconductor device or a portion of an example semiconductor device is shown.

[0031] Figure 6 A block diagram of a system having one or more semiconductor devices is shown.

[0032] It should be understood that the various example implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0033] In memory arrays of memory devices (e.g., DRAMs), multiple bit lines extend parallel to one another. Due to the close physical proximity of these bit lines, parasitic capacitance can occur. The parasitic capacitance can be influenced by the insulating layers and / or other materials between adjacent bit lines. The parasitic capacitance can slow down read and write operations of memory cells. For example, during a read operation, the charge stored in a memory cell needs to be accurately sensed. The presence of parasitic capacitance can interfere with the sensing process, resulting in errors or delays. Similarly, during a write operation, a bit line needs to be charged or discharged to write data into a memory cell. The parasitic capacitance can affect the speed and efficiency of the write process.

[0034] Embodiments of the present disclosure provide semiconductor devices and methods of forming such semiconductor devices. In some embodiments, a semiconductor device includes a memory array of memory cells and bit lines coupled to the memory array. Adjacent ones of the bit lines are separated by an isolation region along a first direction. The isolation region extends along a second direction perpendicular to the first direction. The isolation region includes an air gap. Along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines.

[0035] Embodiments of the present disclosure can provide one or more of the following technical advantages and / or benefits. For example, adjacent bit lines can be separated with an air gap. The relatively small dielectric constant of air (e.g., about 1) in the air gap compared to silicon dioxide (e.g., about 3.9) can reduce the capacitance between adjacent bit lines, thereby reducing crosstalk and improving overall device performance. Additionally, the techniques described in the present disclosure can form a larger air gap between adjacent bit lines, which results in improved signal integrity and lower susceptibility to noise. Furthermore, the air gap can extend beyond the ends of the adjacent bit lines in a direction away from word lines or gate structures. This helps to reduce edge capacitance, which is parasitic capacitance at the ends of two adjacent bit lines. The parasitic capacitance between two conductors can be more significant at the ends of adjacent bit lines compared to along their lengths because electric field lines tend to concentrate more at sharp points or ends of the bit lines, resulting in higher capacitance. With the air gap extending beyond the ends of the adjacent bit lines, the edge capacitance at the bit line ends can also be reduced, further improving device performance. Moreover, the techniques described in the present disclosure can provide a porous low-k dielectric material around the air gap. The porous low-k dielectric material can also help to reduce crosstalk between adjacent bit lines.

[0036] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash, NOR flash, resistive random access memory (RRAM), phase change memory (PCM) (e.g., phase change random access memory (PCRAM)), spin transfer torque (STT)-magnetic random access memory (MRAM), etc.). The technology can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating gate based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell flash) devices, MLC (multi-level cell flash) devices like 2-level cell flash devices, TLC (triple-level cell flash) devices, QLC (quad-level cell flash) devices, or PLC (penta-level cell flash) devices. Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid state drives (SSD), embedded systems, etc.

[0037] Figure 1 A side view of a cross-section of an example 3D semiconductor device 100 is shown. The 3D semiconductor device 100 can be a 3D dynamic random access memory (DRAM). It should be understood that Figure 1 is for illustrative purposes only and can not necessarily reflect actual device structures (e.g., interconnects) in practice. In some implementations, the 3D semiconductor device 100 is a bonded chip that includes a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 can be joined at a bonding interface 106 between them.

[0038] As Figure 1 shown, the first semiconductor structure 102 can include a substrate 110, which can include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other appropriate material. The first semiconductor structure 102 can include peripheral circuitry 112 on and / or in the substrate 110. In some implementations, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 114) can also be formed on or in the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the first semiconductor structure 102 can also be formed on a semiconductor die that can be referred to as a control die or CMOS die 102.

[0039] In some implementations, the first semiconductor structure 102 further includes an interconnect layer 116 above the peripheral circuitry 112 to transmit electrical signals to and from the peripheral circuitry 112. The interconnect layer 116 can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and via contacts. The interconnect layer 116 can also include one or more interlayer dielectric (ILD) layers in which the interconnect lines and via contacts can be formed. That is, the interconnect layer 116 can include interconnect lines and via contacts in a plurality of ILD layers. In some implementations, the peripheral circuitry 112 is coupled to one another through interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 can include a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layers can be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0040] As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 can further include a bonding layer 118 at the back side at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuitry 112. The bonding layer 118 can include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 can include a conductive material, such as Cu. The remaining areas of the bonding layer 118 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 119 and the surrounding dielectric in the bonding layer 118 can be used for hybrid bonding. Similarly, as shown, the second semiconductor structure 104 can further include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 can include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 can include a conductive material, such as Cu. The remaining areas of the bonding layer 120 can be formed with a dielectric material, such as silicon oxide. The bonding contacts 121 and the surrounding dielectric in the bonding layer 120 can be used for hybrid bonding. The bonding contacts 121 can be in contact with the bonding contacts 119 at the bonding interface 106. In some implementations, the bonding layer 120 includes a dielectric layer opposite the memory cells (e.g., DRAM cells) 124, with the bit lines 123 positioned between the dielectric layer and the memory cells 124, as shown. The dielectric layer can include the bonding interface 106 with the bonding contacts 121. Figure 1 Figure 1 Figure 1

[0041] ​​​The second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at a bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layer 120 and the bonding layer 118 as a result of hybrid bonding (also referred to as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can achieve both metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layer 120 and the bonding layer 118 meet and bond. In some examples, the bonding interface 106 can be a layer with a thickness that includes a top surface of the bonding layer 118 of the first semiconductor structure 102 and a bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0042] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122 that includes bit lines 123 above the bonding layer 120 to transport electrical signals. The interconnect layer 122 can include a plurality of interconnects, such as middle-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 further include local interconnects, such as the bit lines 123 and word line contacts (not shown). The interconnect layer 122 can further include one or more ILD layers in which interconnect lines and via contacts can be formed. The interconnects in the interconnect layer 122 can include conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers can be formed with dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0043] In some embodiments, the peripheral circuitry 112 includes word line drivers / row decoders that are coupled to word line contacts in the interconnect layer 122 through the bonding contacts 121 and the bonding contacts 119 in the bonding layer 120 and the bonding layer 118 and the interconnect layer 116. In some embodiments, the peripheral circuitry 112 includes bit line drivers / column decoders that are coupled to the bit lines 123 and bit line contacts in the interconnect layer 122 through the bonding contacts 121 and the bonding contacts 119 in the bonding layer 120 and the bonding layer 118 and the interconnect layer 116. In some embodiments, the bit lines 123 are metal bit lines rather than semiconductor bit lines (e.g., doped silicon bit lines). For example, the bit lines 123 can include W, Co, Cu, Al, or any other suitable metal that has a higher conductivity than doped silicon. In some embodiments, the bit line contacts are ohmic contacts rather than Schottky contacts.

[0044] In some embodiments, the bit lines 123 are made of a composite conductive material that can be based on a metal material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other appropriate metal silicide that has a higher conductivity than doped silicon.

[0045] In some embodiments, adjacent bit lines 123 are separated by an isolation region. The isolation region can include an air gap 210, for example, as described in further detail below in Figure 2 The relatively small dielectric constant of air (e.g., about 1) in the air gap compared to silicon dioxide (e.g., about 3.9) can reduce the capacitance between adjacent bit lines, thereby reducing cross-talk and improving overall device performance. Thus, a larger air gap between the bit lines 123 can be beneficial, which provides improved signal integrity and lower susceptibility to noise.

[0046] In some embodiments, the second semiconductor structure 104 includes a DRAM device in which memory cells are provided in the form of an array of DRAM cells 124 over the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122 including the bit lines 123 can be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 can be coupled to strings of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and can be referred to as an array die 104.

[0047] In some embodiments, a semiconductor device can include a plurality of array dies (e.g., the array die 104) and a CMOS die (e.g., the CMOS die 102). The plurality of array dies and the CMOS die can be stacked and bonded together. The CMOS die can be coupled to each of the plurality of array dies, respectively, and can drive each of the plurality of array dies, respectively, to operate in a similar manner as the semiconductor device. The semiconductor device can be any appropriate device. In some examples, the semiconductor device includes at least a first wafer and a second wafer that are face-to-face bonded. The array dies can be disposed on the first wafer along with other array dies, and the CMOS die can be disposed on the second wafer along with other CMOS dies. The first wafer and the second wafer can be bonded together, so the array dies on the first wafer can be bonded with corresponding CMOS dies on the second wafer. In some examples, the semiconductor device is a chip in which at least the array dies and the CMOS die are bonded together. In an example, the chip is cut from the wafers that are bonded together. In another example, the semiconductor device is a semiconductor package that includes one or more semiconductor chips assembled on a package substrate.

[0048] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may be any suitable structure, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the individual DRAM cells 124. In some embodiments, the vertical transistor 126 includes a semiconductor body 130 extending vertically (in the z-direction) (in which an active region of a channel may be formed), and a gate structure 136 in contact with one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a rectangular parallelepiped shape or a cylindrical shape, and the gate structure 136 may be adjacent to a single side of the semiconductor body 130 in a plan view, for example, as shown in FIG. Figure 1 As shown. In some embodiments, the vertical transistor 126 has a structure including two or more gates, such as a dual-gate structure, a triple-gate structure, or a gate-all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the semiconductor body 130 in the bit line direction (e.g., in the Y direction). In some embodiments, the gate dielectric 132 abuts one side of the semiconductor body 130, and the gate electrode 134 abuts the gate dielectric 132.

[0049] like Figure 1 As shown, in some embodiments, the semiconductor body 130 has two ends ( Figure 1 In some embodiments, the semiconductor body 130 has a vertical dimension (e.g., an upper end and a lower end in the z-direction), and at least one end (e.g., the lower end) extends beyond the gate dielectric 132 in a vertical direction (z-direction) into the ILD layer. In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (the upper end and the lower end) of the semiconductor body 130 extend beyond the gate electrode 134 in a vertical direction (z-direction) into the ILD layer. That is, the semiconductor body 130 can have a vertical dimension (e.g., in the z-direction) that is larger than the vertical dimension (e.g., the depth) of the gate electrode 134, and neither the upper end nor the lower end of the semiconductor body 130 is flush with the corresponding end of the gate electrode 134. Thus, short circuits between the bit line 123 and the word line / gate electrode 134, or between the word line / gate electrode 134 and the capacitor 128, can be avoided. The vertical transistor 126 may further include a source and a drain (both referred to as 138 because their positions may be interchanged) disposed at both ends (upper end and lower end) of the semiconductor body 130 in the vertical direction (z direction). In some embodiments, one of the source and drain 138 (e.g., atFigure 1 ) is coupled to capacitor 128, and the other of source and drain 138 (e.g., at Figure 1 That is, the vertical transistor 126 may have a first terminal in the positive z-direction and a second terminal opposite to the first terminal in the negative z-direction, such as Figure 1 shown.

[0050] In some embodiments, the semiconductor body 130 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may include single crystal silicon. The source and drain 138 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 comprises a conductive material including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 comprises multiple conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure 136 can be a "gate oxide / gate polysilicon" gate, where the gate dielectric 132 comprises silicon oxide and the gate electrode 134 comprises doped polysilicon. In another example, the gate structure 136 can be HKMG, where the gate dielectric 132 comprises a high-k dielectric and the gate electrode 134 comprises a metal.

[0051] As described above, since the gate electrode 134 can be part of a word line or extend as a word line in a word line direction (e.g., X direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each word line extending in the word line direction. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a perpendicular direction perpendicular to the two lateral directions in which the bit lines 123 and the word lines 134 extend. The word line 134 contacts a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 134 includes multiple conductive layers, such as a W layer on top of a TiN layer, such as Figure 1 As shown in .

[0052] In some embodiments, as Figure 1 As shown, vertical transistor 126 extends vertically through and contacts word line 134, and the source or drain 138 of vertical transistor 126 contacts bit line 123 (or bit line contact, if any) at the lower end of vertical transistor 126. Therefore, due to the vertical arrangement of vertical transistor 126, word line 134 and bit line 123 can be arranged in different planes in the vertical direction, which simplifies the routing of word line 134 and bit line 123. In some embodiments, bit line 123 is vertically arranged between bonding layer 120 and word line 134, and word line 134 is vertically arranged between bit line 123 and capacitor 128. Word line 134 can be coupled to peripheral circuit 112 in first semiconductor structure 102 through word line contact (not shown) in interconnect layer 122, bonding contact 121 and bonding contact 119 in bonding layer 120 and bonding layer 118, and interconnect in interconnect layer 116. Similarly, the bit lines 123 in the interconnect layer 122 may be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnects in the interconnect layer 116 .

[0053] In some embodiments, vertical transistors 126 may be arranged in a mirror-symmetrical manner to increase the density of DRAM cells 124 in the bit line direction (Y direction). Figure 1As shown, two adjacent vertical transistors 126 in the bit line direction are mirror symmetric to each other with respect to the trench isolation 160. That is, the second semiconductor structure 104 can include a plurality of trench isolations 160, each extending parallel to the word lines 134 in the word line direction (X direction) and disposed between the vertical gates 134 of two rows of adjacent vertical transistors 126. In some embodiments, the rows of vertical transistors 126 separated by the trench isolation 160 are mirror symmetric to each other with respect to the trench isolation 160. The trench isolation 160 can be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. It should be appreciated that the trench isolation 160 can include an air gap, each disposed laterally between adjacent vertical gates 134. Due to the relatively small pitch of the vertical transistors 126 in the bit line direction (e.g., Y direction), the air gap can be formed. On the other hand, the relatively large dielectric constant of air (e.g., about 4 times that of silicon oxide) in the air gap compared to some dielectrics (e.g., silicon oxide) can improve the insulating effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, depending on the pitch of the word lines / gate electrodes 134 in the bit line direction, air gaps are also formed laterally between the word lines / gate electrodes 134 in the bit line direction.

[0054] In some embodiments, instead of having the trench isolation 160 with air gaps disposed between adjacent vertical gates 134 of two rows of adjacent vertical transistors 126, a shielding conductive structure 170 (e.g., including a metal such as W) is disposed between adjacent semiconductor bodies 130 of two rows of adjacent vertical transistors 126. The shielding conductive structure 170 can be in contact with at least one of the adjacent semiconductor bodies 130, and can be coupled to a low voltage (e.g., a fixed negative voltage), which can reduce the charge accumulation in the memory cells 124, mitigating the floating body effect in the memory cells 124. Moreover, by applying a fixed low voltage on the shielding conductive structure 170 between the memory cells 124, the threshold voltage of the memory cells 124 can be conveniently adjusted, which can reduce the overall manufacturing complexity and cost, and improve the reliability of the memory cells 124. Furthermore, the conductive structure 170 can be coupled out from the same side as the word lines or a different side from the word lines. For example, the shielding conductive structure 170 can be coupled out from the backside of the second semiconductor structure 104. The shielding conductive structure 170 can also be referred to as a shielding conductive material.

[0055] As Figure 1As shown, in some embodiments, the capacitor 128 includes a first electrode 144 over the source or drain 138 of the vertical transistor 126 (e.g., the upper end of the semiconductor body 130) and coupled to the source or drain 138 of the vertical transistor 126 via a capacitor contact 142. In some embodiments, the capacitor contact 142 is an ohmic contact (e.g., a metal silicide contact) rather than a Schottky contact. For example, the capacitor contact 142 can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other appropriate metal silicide having a higher conductivity than doped silicon. The capacitor 128 can also include a capacitor dielectric over and in contact with the first electrode 144, and a second electrode over and in contact with the capacitor dielectric. That is, the capacitor 128 can be a vertical capacitor in which the electrodes and capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric can be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to the source or drain 138 of a respective vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., a common ground). The capacitor 128 can have a first end in the negative z-direction and a second end in the positive z-direction opposite the first end, as shown. Figure 1 As shown, in some embodiments, the first end of the capacitor 128 is coupled to the first terminal of the vertical transistor 126 via an ohmic contact (e.g., the capacitor contact 142 made of a metal silicide material). As shown, Figure 1 As shown, the second semiconductor structure 104 can also include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146 for coupling the capacitor 128 to the peripheral circuit 112 or directly to ground. In some embodiments, the capacitor contact 147 (e.g., the conductor) extends in the z-direction from the dielectric layer of the bond layer 120 to couple to the second end of the capacitor 128 via the common plate 146, as shown. Figure 1 In some embodiments, in which the ILD layer in which the capacitor 128 is formed has the same dielectric material as the two ILD layers in which the semiconductor body 130 extends, such as silicon oxide.

[0056] It should be appreciated that the structure and configuration of the capacitor 128 is not limited to Figure 1capacitor 128 can be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some implementations, the electrodes include a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0057] As shown in FIG. 1, the DRAM cell 124 includes a vertical transistor 126, a capacitor 128, and a bit line 123. The vertical transistor 126 is a vertical transistor that extends vertically through the DRAM cell 124. The capacitor 128 is a planar capacitor that extends horizontally across the DRAM cell 124. The bit line 123 is a planar bit line that extends horizontally across the DRAM cell 124. The vertical transistor 126 is coupled to the capacitor 128 and the bit line 123. Figure 1 As shown in FIG. 1, the vertical transistor 126 vertically extends through and contacts the word line 134, a source or drain 138 of the vertical transistor 126 at a lower end of the vertical transistor 126 contacts the bit line 123, and the source or drain 138 of the vertical transistor 126 at an upper end of the vertical transistor 126 is coupled to the capacitor 128. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be disposed in different planes in the vertical direction and are coupled to opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some implementations, the bit line 123 and the capacitor 128 are disposed on opposite sides of the vertical transistor 126 in the vertical direction, which simplifies the routing of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to DRAM cells in which the bit line and the capacitor are disposed on the same side of the planar transistor.

[0058] As shown in FIG. 1, the vertical transistor 126 vertically extends through and contacts the word line 134, a source or drain 138 of the vertical transistor 126 at a lower end of the vertical transistor 126 contacts the bit line 123, and the source or drain 138 of the vertical transistor 126 at an upper end of the vertical transistor 126 is coupled to the capacitor 128. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be disposed in different planes in the vertical direction and are coupled to opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some implementations, the bit line 123 and the capacitor 128 are disposed on opposite sides of the vertical transistor 126 in the vertical direction, which simplifies the routing of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to DRAM cells in which the bit line and the capacitor are disposed on the same side of the planar transistor. Figure 2 As shown in FIG. 1, the vertical transistor 126 vertically extends through and contacts the word line 134, a source or drain 138 of the vertical transistor 126 at a lower end of the vertical transistor 126 contacts the bit line 123, and the source or drain 138 of the vertical transistor 126 at an upper end of the vertical transistor 126 is coupled to the capacitor 128. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be disposed in different planes in the vertical direction and are coupled to opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some implementations, the bit line 123 and the capacitor 128 are disposed on opposite sides of the vertical transistor 126 in the vertical direction, which simplifies the routing of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to DRAM cells in which the bit line and the capacitor are disposed on the same side of the planar transistor.

[0059] In some implementations, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 can be part of a carrier wafer. It should be appreciated that in some examples, the substrate 148 can not be included in the second semiconductor structure 104.

[0060] like Figure 1 As shown, the second semiconductor structure 104 may further include a substrate 148 and a pad output interconnect layer 150 above the DRAM cell 124. The pad output interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad output interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. The capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad output interconnect layer 150. In some embodiments, the interconnects in the pad output interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 100 and external circuits, for example, for pad output purposes.

[0061] In some embodiments, second semiconductor structure 104 further includes one or more contacts 152 extending through substrate 148 and a portion of pad output interconnect layer 150 to couple pad output interconnect layer 150 to DRAM cell 124 and interconnect layer 122. As a result, peripheral circuit 112 can be coupled to DRAM cell 124 through interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuit 112 and DRAM cell 124 can be coupled to external circuitry through contacts 152 and pad output interconnect layer 150. Contact pads 154 and contacts 152 can include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, contact pads 154 can include Al, and contacts 152 can include W. In some embodiments, contacts 152 include vias surrounded by dielectric spacers (e.g., comprising silicon oxide) to electrically isolate the vias from substrate 148. Depending on the thickness of substrate 148 , contacts 152 may be ILVs with a depth of submicrometers (eg, between 10 nm and 1 μm) or TSVs with a depth of micrometers or tens of micrometers (eg, between 1 μm and 100 μm).

[0062] Although not shown, it should be understood that the pad output of the 3D memory device is not limited to the output from Figure 1 The second semiconductor structure 104 is shown with a DRAM cell 124 and may be from the first semiconductor structure 102 with the peripheral circuit 112. Although not shown, it is also understood that the air gaps between the word lines 134 and / or between the semiconductor bodies 130 may be partially or completely filled with a dielectric. Although not shown, it is also understood that arrays of more than one DRAM cell 124 may be stacked on top of each other to vertically scale up the number of DRAM cells 124.

[0063] In some embodiments, instead of Figure 2The second semiconductor structure 104 is shown with a substrate 148 above the DRAM cell 124. The substrate 148 is disposed below the DRAM cell 124. The substrate can be part of a carrier wafer. The DRAM cell 124 can be formed in the front side of the substrate, and the bit line 123 can be formed in the back side of the substrate. The bit line 123 can be conductively coupled to the DRAM cell 124 (e.g., the terminal 138 of the vertical transistor 126) through the substrate.

[0064] Figure 2 A cross-sectional view of an example air gap between bit lines for a portion of an example semiconductor device 200 is shown. The example semiconductor device 200 may be implemented as Figure 3B The semiconductor device 100 in FIG. Figure 2 As shown, the bit lines 123 can be coupled to the semiconductor bodies 130 of the memory cells 124 of the memory array. Adjacent bit lines 123 can be separated by isolation regions 202 along a first direction (e.g., an X direction or a word line direction). The isolation regions 202 can extend along a second direction perpendicular to the first direction. The second direction can be, for example, Figure 2 The Z direction is shown. The isolation region 202 may include an air gap 210. An end 204 of the air gap 210 is above an adjacent end 206 of the bit line 123 in the adjacent bit line. In some embodiments, a portion of the bit line 123 includes a metal material or a silicide material. Figure 2 As shown, the top portion of the bit line (e.g., the portion further away from the gate structure 136) includes a silicide material 228. In some embodiments, the silicide material 228 includes, but is not limited to, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Another portion of the bit line 123 (e.g., the bottom portion 230) can be coupled to the semiconductor body 130. In some cases, the bottom portion 230 of the bit line 123 and the semiconductor body 130 can include the same semiconductor material, such as silicon or polysilicon, for example, as described with respect to Figure 2 described.

[0065] In some embodiments, the air gap 210 is surrounded by an isolation material 214. In some embodiments, the isolation material 214 includes a low-k (low dielectric constant) porous dielectric material. In some embodiments, the porous dielectric material is created by introducing pores or voids into the material structure, which reduces its overall density. This can result in a lower dielectric constant k compared to silicon dioxide (Si02). In some embodiments, the low-k porous dielectric material has a dielectric constant within a range (e.g., from about 1.5 to about 3.5). In some embodiments, the low-k porous dielectric material includes, but is not limited to, silicon oxycarbide (SiOC), organosilicate glass (OSG), carbon-doped oxide (CDO), or black diamond (BD). In some embodiments, the low-k porous dielectric material includes silicon oxide doped with carbon.

[0066] In some embodiments, adjacent semiconductor bodies 130 are isolated by a dielectric material 213. The dielectric material 213 can be the same as or different from the isolation material 214. In some embodiments, the dielectric material 213 includes silicon oxide.

[0067] In some embodiments, along the second direction (e.g., the Z direction), a distance between the end 204 of the air gap 210 and an end 232 (e.g., a top surface) of the gate structure 136 is greater than a distance between an adjacent end 206 of the bit line 123 and the end 232 of the gate structure 136. As shown, the distance between the end 204 of the air gap 210 and the end 232 of the gate structure 136 can be represented as a first distance 208. The distance between the adjacent end 206 of the bit line 123 and the end 232 of the gate structure 136 can be represented as a second distance 212. The first distance 208 can be greater than the second distance 212. Figure 2

[0068] In some embodiments, along the second direction (e.g., the Z direction), the end 204 of the air gap 210 is distanced from the adjacent end 206 of the bit line 123 in the adjacent bit line by a height 216. A ratio of the height 216 to a width of the isolation region 202 along the first direction (e.g., the X direction) can be within a range of, for example, from about 0 to about 0.8. In some embodiments, the height 216 is within a range of, for example, from about 3 nm to about 10 nm. The width 218 of the isolation region 202 can be a spacing distance between two adjacent bit lines 123.

[0069] In some embodiments, the air gap 210 includes a first portion 222 and a second portion 224 along the second direction (e.g., the Z direction). A width 226 of the air gap 210 in the first portion 222 along the first direction (e.g., the X direction or word line direction) is less than a width 238 of the air gap 210 in the second portion 224, as shown. Figure 2 ​In some embodiments, the width 226 of the air gap 210 in the first portion 222 refers to the average width of the air gap 210 in the first portion 222. Likewise, the width 238 of the air gap 210 in the second portion 224 refers to the average width of the air gap 210 in the second portion 224. In some embodiments, the width 226 of the air gap 210 in the first portion 222 refers to any width of the air gap 210 in the first portion 222 except for the width at the interface of the first portion 222 and the second portion 224.

[0070] In some embodiments, in the first portion 222, the width of the air gap 210 at a first location is less than the width of the air gap at a second location, where the first location is closer to the end 204 of the air gap 210 than the second location. In some embodiments, as shown in FIG. 2A, the width 226 of the air gap 210 gradually decreases in the first portion 222 of the air gap 210 toward the end 204 of the air gap 210. Figures 3A-3B Figure 3A In some embodiments, the cross-section of the second portion 224 has a rectangular shape or a rectangular-like shape, for example, as shown in FIG. 2B. The width 238 of the air gap 210 in the second portion 224 can be uniform in the second direction in the second portion 224. Figure 3A

[0071] In some examples, the ratio of the maximum width of the air gap 210 along the first direction (e.g., the X-direction or word line direction) to the width of the isolation region along the first direction is greater than 0.6, for example, 0.7, 0.8, 0.9, or greater. Thus, in the isolation region 202, the width of the air gap 210 can be greater than the combined width of the isolation material 214 along the X-direction, as shown in FIG. 2A. Figure 1

[0072] In some examples, the ratio of the height 234 of the air gap 210 along the second direction (e.g., the Z-direction) to the width 218 of the isolation region 202 along the first direction (e.g., the X-direction) is in a range of, for example, from about 2 to about 5.

[0073] In some embodiments, the aspect ratio of the air gap 210 between the height 234 of the air gap 210 and the width 236 of the air gap 210 is greater than or equal to 3. For example, the height 234 of the air gap 210 can be 50 nm, while the width 236 of the air gap 210 can be 10 nm.

[0074] In some embodiments, a spacer (not shown) is located between the bit line 123 and the isolation material 214. The spacer can include silicon nitride. The spacer can be used to protect the bit line 123 from contamination during the manufacturing process.​​​

[0075] Figure 1 Cross-sectional views of a portion of an example semiconductor device during various stages of fabrication are shown. As shown, Figure 3B a plurality of semiconductor bodies 130 can be formed. Each semiconductor body 130 can extend along a Z direction. Adjacent semiconductor bodies 130 can be arranged along an X direction (e.g., a word line direction, as shown) and / or a Y direction (e.g., a bit line direction, as shown). Adjacent semiconductor bodies 130 can be separated by a dielectric material 213. In some embodiments, the dielectric material 213 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Figure 1 Figures 2-4B

[0076] A gate structure 136 can be deposited adjacent to the semiconductor bodies 130 to form a gate oxide. The gate structure 136 can extend along a word line direction (e.g., an X direction). The gate structure 136 can include a gate dielectric 132 and a gate electrode 134 (e.g., as shown). The gate dielectric 132 can include a dielectric material in contact with the semiconductor bodies 130. The dielectric material can include silicon oxide, silicon nitride, or a high-k dielectric material including, but not limited to, AI2O3, HfO2, Ta2O5, ZrO2, TiO2, any material having a dielectric constant higher than or equal to 3.9, or any combination thereof. The gate electrode 134 can abut the gate dielectric 132. In some embodiments, the gate electrode 134 includes a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes a plurality of conductive layers, such as a W layer on top of a TiN layer. Figure 1

[0077] A silicide material 228 can be formed by performing a silicidation process at the exposed upper end of the semiconductor bodies 130. The silicidation process can involve depositing a metal at the exposed upper end of the semiconductor bodies 130, followed by an anneal process. During the anneal, the deposited metal can react with silicon on the semiconductor bodies 130 to form a silicide layer at the metal-silicon interface. In some embodiments, the silicide material 228 includes, but is not limited to, WSi, CoSi, CuSi, AlSi, or any other appropriate metal silicide.

[0078] Figures 4A-4B ​​​​As shown, the dielectric material 213 can be partially etched or removed to expose sidewalls of the upper portions of the semiconductor bodies 130. As a result, trenches can be formed between adjacent upper portions of the semiconductor bodies 130. This exposed upper portion of the semiconductor bodies 130 can serve as the bit lines 123. The etching can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0079] In some embodiments, the exposed upper portion of the semiconductor bodies 130 (e.g., the bit lines 123) is doped such that the dopant or dopant level of the bit lines 123 is different from the dopant or dopant level of the remaining portions of the semiconductor bodies 130. The remaining portions of the semiconductor bodies 130 can be the segments of the semiconductor bodies 130 that are not used as the bit lines 123. In some embodiments, the bit lines 123 are doped with N+ type dopants (e.g., phosphorus (P) or arsenic (As)) or P type dopants (e.g., boron (B) or gallium (Ga)) at a desired doping level.

[0080] In some embodiments, the semiconductor bodies 130 and the gate structures 136 are formed from the front side of a substrate (not shown), while the silicide material 228 and the air gaps 210 are formed from the back side of the substrate. This process can involve flipping the substrate and thinning or polishing the back side of the substrate prior to forming the silicide material 228 and the air gaps 210. A carrier wafer can be utilized that is bonded to the front side of the substrate during this process. The carrier wafer can provide mechanical support during subsequent processing steps (e.g., polishing the back side of the substrate, forming the silicide material 228 and the air gaps 210).

[0081] Although not shown, it should be appreciated that the semiconductor bodies 130 can further extend beyond the gate structures 136 in the negative Z direction. The lower ends (e.g., the ends in the negative Z direction) of the semiconductor bodies 130 can be coupled to the capacitors 128, as shown. It should also be appreciated that the positive Z direction in Figure 4A Figure 4A may be opposite to the positive Z direction in Figure 2

[0082] Figure 4B A cross-sectional view of an example air gap between the bit lines 123 is shown. As shown, the dielectric material 213 can be partially etched or removed to expose sidewalls of the upper portions of the semiconductor bodies 130. As a result, trenches can be formed between adjacent upper portions of the semiconductor bodies 130. This exposed upper portion of the semiconductor bodies 130 can serve as the bit lines 123. The etching can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof. Figure 4B ​​As shown, to form an isolation region 422 in a portion of the semiconductor device 400, a separation material 402 can be deposited into the trenches between the bit lines 123. In some embodiments, the separation material 402 is a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the separation material 402 is deposited using plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the PECVD deposition process utilizes a precursor gas silane (SiH4) as one of the main reactants for film deposition. Silane can be used to deposit silicon-containing films, such as silicon dioxide (SiO2) or silicon nitride (Si3N4). In some embodiments, due to the high aspect ratio of the trenches between adjacent bit lines 123, an air gap 410 is formed between adjacent bit lines 123, and the air gap 410 is surrounded by the separation material 402, as shown in FIG. Figure 2 As shown. In some embodiments, the air gap 410 is narrow such that the width of the air gap 410 along the x-direction (e.g., the wordline direction) is less than the combined width of the spacer material 402 along the same direction. In some embodiments, the air gap 410 does not extend beyond the isolation region 422 between adjacent bitlines 123 in the positive z-direction. In other words, the distance between the end 404 of the air gap 410 and the end 232 of the gate structure 136 is less than the distance between the adjacent end 206 of the bitline 123 and the end 232 of the gate structure 136.

[0083] As with Figure 2 Same or substantially similar Figure 5 As shown, isolation material 214 can be deposited in the trenches between bit lines 123. In some embodiments, isolation material 214 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the deposition of isolation material 214 utilizes a chain-type precursor having a porous connecting material. The porous connecting material may include a CH3 group (methyl). The chain-type precursor can be used to grow a low-K dielectric material. The molecular units in the chain-type precursor can be arranged in a linear manner, similar to one or more chains. The linear nature of the chain can promote controlled growth during the deposition process. In addition, the CH3 group can be easily broken during the deposition process. When the CH3 group breaks, it can promote the growth of the dielectric in a specific direction (for example, Figure 1controlled breaking and growth along the Y-axis can help improve film uniformity. During growth, voids or empty spaces can form within the isolation material 214. These voids can arise due to various factors, such as breaking of CH3 groups, incomplete filling of trenches, insufficient bonding between precursor molecules, or release of gas or solvent during the deposition process. The voids can cause the formation of a porous material, such as the isolation material 214. The presence of these voids can reduce the overall density of the isolation material 214, thereby lowering its dielectric constant k. This reduction in dielectric constant can be beneficial in semiconductor manufacturing, as it can help reduce the parasitic capacitance between adjacent bit lines 123.

[0084] In some embodiments, the isolation region 202 between adjacent bit lines 123 is formed using plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the deposition process involves introducing a gaseous mixture of a porous link material of a chain-type precursor and oxygen gas into a reaction chamber. In some embodiments, the porous link material has one or more chemical elements, including silicon (Si), carbon (C), oxygen (O), and hydrogen (H). In some embodiments, chemical bonds between two or more of the chemical elements or chemical compounds in the porous link material are breakable during the formation of the isolation region 202. For example, the porous link material can include CH3 groups, and the CH3 groups can be breakable during deposition of the isolation material 214.

[0085] In some embodiments, the air gap 210 is formed in the isolation region 202 by utilizing the porous link material as a precursor. As described in Figures 2-3B The air gap 210 can extend beyond the adjacent ends 206 of the bit lines in the positive z-direction, such that the distance between the end 204 of the air gap 210 and the end 232 of the gate structure 136 is greater than the distance between the adjacent ends 206 of the bit lines and the end 232 of the gate structure 136. The air gap 210 can also have other characteristics or properties as described above in Figures 1-4B

[0086] In some embodiments, the air gap 210 of the semiconductor device 200 is larger in size (e.g., width and / or height) than the air gap 410 of the semiconductor device 400. The larger air gap 210 between the bit lines 123 can reduce the parasitic capacitance between adjacent bit lines 123. The lower capacitance can reduce capacitive coupling, thereby mitigating unwanted signal cross-talk and interference between adjacent bit lines 123. This can further result in improved signal integrity and lower susceptibility to noise.

[0087] Figures 2-4B An example process of forming an example of a semiconductor device or a portion of a semiconductor device is shown. The semiconductor device or the portion of the semiconductor device can be, for example,​Figures 2-4B The semiconductor device 100 or Figure 2 and a portion of the semiconductor device 200 shown in FIG. 4B.

[0088] In step 502, bit lines are formed and separated by dielectric material. The bit lines may be, for example, Figure 2 The dielectric material may be, for example, Figure 2 of dielectric material 213.

[0089] At step 504, the dielectric material is at least partially etched between adjacent bit lines to form trenches along a first direction between the adjacent bit lines. The first direction may be, for example, Figures 1-4B X direction.

[0090] At step 506, an isolation region is formed in the trench between adjacent bit lines. The isolation region includes an air gap surrounded by an isolation material. Along the second direction, the ends of the air gap are above adjacent ends of the bit lines in the adjacent bit lines. The isolation region may be, for example, Figure 2 and 4B The air gap may be, for example, Figures 2-4B and 4B The air gap 210. The isolation material may be, for example, Figure 1 and 4B of the isolation material 214. The second direction may be, for example, Figure 1 The ends of the air gap can be, for example, Figures 1-4B and 4B The end 204 of the air gap 210. The adjacent end of the bit line may be, for example Figures 1-4B The adjacent end 206 of the bit line 123.

[0091] In some embodiments, plasma enhanced chemical vapor deposition (PECVD) is used to form the isolation region between adjacent bit lines. In some embodiments, forming the isolation region 202 in the trench between adjacent bit lines 123 includes introducing a gas mixture of a porous connecting material and oxygen in the gas phase into the reaction chamber. In some embodiments, the size of the air gap 210 is controlled by adjusting the concentration of the porous connecting material. In some embodiments, a higher concentration of porous connecting material results in a higher deposition rate of the isolation material 214. In some cases, with a higher deposition rate, the isolation material 214 can accumulate faster near the upper end of the trench. Therefore, when the trench is filled with the isolation material 214, the time for air to escape from the trench may be less. This can result in a larger air gap 210 being formed in the trench because the isolation material 214 can capture air when it fills the trench.

[0092] In some implementations, the size of the air gap 210 is controlled by adjusting a radio frequency (RF) power of the reaction chamber. In a PECVD process, the RF power can be used to generate and control a plasma. The plasma can help activate precursor gases, such as the porous connection material, causing chemical reactions and deposition of the isolation material 214 onto the substrate. By adjusting the RF power, the density and energy of the plasma can be controlled, which in turn affects the deposition rate. Higher RF power can result in an increased deposition rate of the isolation material 214. As described above, a higher deposition rate of the isolation material 214 can result in a larger air gap 210 being formed.

[0093] In some implementations, the porous connection material has one or more chemical elements, including silicon (Si), carbon (C), oxygen (O), and hydrogen (H).

[0094] In some implementations, chemical bonds between two or more chemical elements or chemical compounds in the porous connection material are breakable during formation of the isolation region. For example, the porous connection material can include CH3 groups, and the CH3 groups can be breakable during deposition of the isolation material 214.

[0095] In some implementations, the method includes forming a capacitor and a transistor. The transistor includes a transistor body extending along a second direction (e.g., the Z-direction), a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body. The first terminal of the transistor is coupled to the capacitor. The second terminal of the transistor is coupled to a corresponding bit line of the bit lines. The capacitor can be, for example, the capacitor 128. The transistor can be, for example, the transistor 126. The transistor body can be, for example, the semiconductor body 130. The gate structure can be, for example, the gate structure 136. The first terminal and the second terminal can be, for example, the source and drain 138. Figure 1 Figures 2-4B Figure 6 Figure 6 Figure 1

[0096] In some implementations, along the second direction, a distance between an end of the air gap and an end of the gate structure is greater than a distance between adjacent ends of the bit lines and the end of the gate structure. The end of the gate structure can be, for example, the end 232 of the gate structure 136. Figure 2

[0097] Figures 3A-3B ​​​​​​A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown, system 600 may include a host device 608 and a memory system 602 having one or more 3D memory devices 604 and a memory controller 606. Host device 608 may include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). Host device 608 may be configured to send data to or receive data from one or more 3D memory devices 604.

[0098] The 3D memory device 604 may be any 3D memory device disclosed herein, such as ​ The 3D semiconductor device 100, or ​ and 4B a portion of the 3D semiconductor device 200, or ​ FIG. 2 is an intermediate structure of a 3D semiconductor device 200 during manufacturing.

[0099] In some embodiments, the 3D memory device 604 includes NAND flash memory. A memory controller 606 (also referred to as a controller circuit) is coupled to the 3D memory device 604 and a host device 608. Consistent with embodiments of the present disclosure, the 3D memory device 604 may include a plurality of conductive interconnects through a cover layer, the plurality of conductive interconnects contacting conductive pads in the conductive pad layer, and the memory controller 606 may be coupled to the 3D memory device 604 via at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the 3D memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host device 608.

[0100] In some embodiments, the memory controller 606 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile telephones, etc.). In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC) used as data storage for mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 606 can be configured to control operations of the 3D memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 604, including, but not limited to, bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes related to data read from or written to the 3D memory device 604. Any other suitable functions can also be performed by the memory controller 606, such as formatting the 3D memory device 604.

[0101] The memory controller 606 can communicate with external devices (e.g., host device 608) according to a particular communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0102] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, such as included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 602 can be implemented and packaged into different types of end electronic products. In one example as shown, the memory controller 606 and a single 3D memory device 604 can be integrated into a memory card 602. The memory card 602 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCMicro), a SD card (SD, miniSD, microSD, SDHC), a UFS, etc. ​ ​

[0103] The subject matter described in this disclosure and the implementation of the actions and operations can be implemented in digital electronic circuitry, in tangibly embodied computer software or firmware, or in computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or a combination of one or more thereof. The implementation of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing apparatus or for controlling the operation of the data processing apparatus. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to an appropriate receiver apparatus for execution by the data processing apparatus. The computer storage medium can be a portion of or a part of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof. A computer storage medium is not a propagated signal.

[0104] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other implementations, whether or not explicitly described.

[0105] Generally, a term can be understood, at least in part, from its usage in the context. For example, the term "one or more," as used herein, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to express singular usage or to express plural usage, depending, at least in part, on the context. Additionally, the term "based on" may be understood to not necessarily be intended to express an exclusive set of factors, but rather may allow for the presence of other factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0106] It should be readily understood that the terms "on," "over," and "above" in the present disclosure are to be interpreted in the broadest possible way consistent with the context. Thus, "on" means not only "directly on" but also "on" with intervening features or layers therebetween. Further, "over" or "above" means not only "over" or "above" but also "directly over" or "directly above" (i.e., directly on).

[0107] Further, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during different stages of manufacture, for example, the spatially relative terms can refer to the device as it is used in a particular orientation during use, or can refer to the device as it is being manufactured or handled (e.g., packaging) in a different orientation, depending on the particular context. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0108] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor device is formed, and thus the semiconductor device is formed on the top side of the substrate, unless otherwise specified. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0109] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a continuous structure that is homogeneous or non-homogeneous in thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (with contacts, interconnect lines, and / or vertical interconnect channels (vias) formed therein) and one or more dielectric layers.

[0110] As used herein, the term “nominal / nominally” refers to a desired or target value of a characteristic or parameter of a component or process step, as well as a range of values above and / or below the desired value, set during a design phase of a product or process. As used herein, a range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” denotes a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” can denote a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0111] In the present disclosure, the term “horizontal / horizontally / lateral / laterally” denotes nominally parallel to a lateral surface of a substrate, and the term “vertical” or “vertically” denotes nominally perpendicular to the lateral surface of the substrate.

[0112] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” e.g., NAND strings) in a lateral orientation on a substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0113] The present disclosure provides many different embodiments or examples of implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature over or on a second feature can include embodiments in which the first feature and the second feature are in direct contact and / or there can be an additional feature or features between the first feature and the second feature such that the first feature and the second feature do not make direct contact. In addition, the present disclosure can repeat certain previously described features and / or descriptions of components and arrangements in various examples. Such repetition of the previously described features and / or descriptions of components and arrangements is for simplicity and clarity and does not itself take disclosure away from those various embodiments and / or configurations.

[0114] The foregoing description of various embodiments of the specific implementations can be readily modified / adjusted for various applications. Accordingly, such modifications and alterations are intended to be within the scope and spirit of the disclosed implementations. The above description is that of current embodiments of the application. Various alterations and changes can be made thereto without departing from the spirit of the application, and it is understood that the disclosed embodiments are for exemplary only. Any combination of the modifications and alterations are to be within the scope of the application. The various embodiments delineated above are widely intended and are to be accorded the broadest scope of the appended claims to encompass all such modifications.

[0115] Although the present disclosure includes a number of specific implementation details, these should not be construed as limitations on the scope of what is claimed, but rather as descriptions of features that can be specific to particular embodiments of the application. Certain features described in the context of separate embodiments in the present disclosure can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any appropriate subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claim can be directed to a subcombination or variation of a subcombination.

[0116] Similarly, while operations are illustrated in the drawings in a particular order, and described in a particular order in the claims, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.

[0117] Particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes illustrated in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In some instances, multitasking and parallel processing can be advantageous.

[0118] The breadth and scope of the present disclosure should not be limited by any of the above-described example implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: a memory array of memory cells; and bit lines coupled to the memory array, wherein adjacent ones of the bit lines are separated along a first direction by an isolation region, the isolation region extending along a second direction perpendicular to the first direction, the isolation region comprising an air gap, wherein along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines.

2. The semiconductor device of claim 1, wherein, a memory cell of the memory cells comprises a transistor and a capacitor, the transistor comprising a transistor body, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, the transistor body extending along the second direction, and wherein the first terminal of the transistor is coupled to the capacitor and the second terminal of the transistor is coupled to a corresponding one of the bit lines.

3. The semiconductor device of claim 2, wherein, Along the second direction, a distance between the end of the air gap and an end of the gate structure is greater than a distance between the adjacent end of the bit line and the end of the gate structure.

4. The semiconductor device according to any one of claims 1 to 3, wherein The air gap is surrounded by an isolation material.

5. The semiconductor device of claim 4, wherein, The isolation material comprises a low-k porous dielectric material.

6. The semiconductor device of claim 5, wherein, The low-k porous dielectric material has a dielectric constant in a range from about 1.5 to about 3.

5.

7. The semiconductor device according to any one of Claims 1 to 6, wherein Along the second direction, the end of the air gap is a height away from the adjacent end of the bit line of the adjacent bit lines, and wherein a ratio of the height to a width of the isolation region along the first direction is in a range from about 0 to about 0.

8.

8. The semiconductor device of claim 7, wherein, The height is in a range from about 3 nm to about 10 nm.

9. The semiconductor device according to any one of Claims 1 to 8, wherein, The air gap comprises a first portion and a second portion arranged along the second direction, and wherein a width of the air gap along the first direction in the first portion is less than a width of the air gap along the first direction in the second portion.

10. The semiconductor device of claim 9, wherein, The width of the air gap along the first direction gradually decreases toward the end of the air gap in the first portion of the air gap.

11. The semiconductor device according to any one of Claims 1 to 10, wherein A ratio of a maximum width of the air gap along the first direction to a width of the isolation region along the first direction is greater than 0.

6.

12. The semiconductor device according to any one of Claims 1 to 11, wherein, A ratio of a height of the air gap along the second direction to a width of the isolation region along the first direction is in a range from about 2 to about 5.

13. The semiconductor device according to any one of Claims 1 to 12, wherein, An aspect ratio of the air gap between a height of the air gap along the second direction and a width of the air gap is greater than or equal to 3.

14. A method comprising: forming bit lines separated by a dielectric material; etching the dielectric material between adjacent ones of the bit lines to form a trench between the adjacent bit lines along a first direction; and forming an isolation region in the trench between the adjacent bit lines, the isolation region extending along a second direction perpendicular to the first direction, wherein the isolation region comprises an air gap surrounded by an isolation material, and along the second direction, an end of the air gap is above an adjacent end of a bit line of the adjacent bit lines.

15. The method of claim 14, wherein, Forming the isolation region in the trench between the adjacent bit lines comprises introducing a gaseous mixture of a porous connecting material and oxygen gas into a reaction chamber.

16. The method of claim 14 or 15, wherein, The isolation regions between the adjacent bit lines are formed using plasma enhanced chemical vapor deposition (PECVD).

17. The method of claim 15 or 16, wherein, Forming the isolation regions in the trenches between the adjacent bit lines includes controlling a size of the air gap by adjusting a concentration of the porous connecting material.

18. The method of any one of claims 14-17, further comprising forming a capacitor and a transistor, the transistor including a transistor body, a gate structure, and a first terminal and a second terminal on opposite ends of the transistor body, the transistor body extending along the second direction, and wherein the first terminal of the transistor is coupled to the capacitor and the second terminal of the transistor is coupled to a corresponding one of the bit lines.

19. The method of claim 18, wherein, Along the second direction, a distance between the end of the air gap and an end of the gate structure is greater than a distance between the adjacent ends of the bit lines and the end of the gate structure.

20. A system comprising: a memory device configured to store data, the memory device including: a memory array of memory cells, and bit lines coupled to the memory array, wherein adjacent ones of the bit lines are separated by an isolation region along a first direction, the isolation region extending along a second direction perpendicular to the first direction, the isolation region including an air gap, wherein along the second direction, an end of the air gap is above adjacent ends of bit lines of the adjacent ones of the bit lines; and a memory controller coupled to the memory device and configured to operate the memory device.

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