A circuit for recycling residual electricity of busbar after spark

Abstract

The present invention discloses a circuit for recycling excess power in the busbar after a spark. By efficiently recycling, storing and recycling the excess power in the busbar after a spark discharge, it can effectively solve the problems of increased busbar voltage, untimely consumption of excess power and delayed system response in the prior art after a spark discharge. First, the circuit quickly transfers excess electric energy in the busbar filter capacitor C0 to the storage capacitor through the excess power recovery storage circuit after a spark occurs, thereby avoiding a rapid increase in busbar voltage due to continuous power supply of the filter inductor L and reverse charging of the inductive load, thereby preventing secondary breakdown, arcing and other damages to the equipment caused by busbar overvoltage, and ensuring the stable operation of the electrostatic precipitator. Secondly, the busbar voltage is monitored and adjusted in real time through the excess power recovery storage control circuit, and the excess power recovery process is accurately controlled using a PWM signal, dynamically reducing the busbar voltage to the target range, and avoiding equipment operation failures caused by unstable busbar voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of environmental protection, and in particular to a circuit for recycling excess electricity in a busbar after sparking. Background Art

[0002] As a highly efficient exhaust gas treatment device, electrostatic precipitators (ESPs) are widely used in heavy industries such as thermal power plants and steel mills. Using a high-voltage electric field, ESPs charge suspended particles in the airflow and attract them to a collecting electrode, effectively removing smoke and reducing particulate matter concentration in the flue gas, improving air quality, and reducing environmental pollution. Their advantages include high dust removal efficiency, low energy consumption, low operating resistance, and strong large-scale flue gas treatment capabilities, making them a crucial industrial flue gas treatment facility.

[0003] However, during actual operation, the electrodes (cathode and anode) within the ESP can spark over time due to factors such as the dust composition, temperature, and humidity in the airflow. This can lead to unstable electric fields within the ESP. This discharge can cause a transient increase in the busbar voltage. If effective measures are not taken promptly, this can cause serious damage to the equipment, reduce dust removal efficiency, and even cause equipment failure, impacting production continuity and environmental performance.

[0004] At present, domestic electrostatic precipitator power supply equipment usually uses two methods to deal with the problem of increased bus voltage after spark discharge. The first method is to connect a discharge resistor or a controllable discharge circuit in parallel to the bus filter capacitor end, and use these resistors or circuits to consume the bus voltage during the spark lockout period. The second method is to turn on the inverter circuit and connect the load after the spark lockout ends, thereby reducing the bus voltage, and then start the front-end rectifier and voltage regulation circuit after the voltage returns to a safe value. However, these existing technical solutions have certain limitations and cannot effectively solve the problems of excessively rapid bus voltage increases during spark lockout, inability to consume voltage in real time, or system response delays, which will still affect the stability of the equipment and the dust removal effect.

[0005] Therefore, during the operation of existing electrostatic precipitators, the increase in bus voltage after spark discharge, the untimely consumption of bus voltage and the delayed response have become problems that need to be solved urgently. Summary of the Invention

[0006] To this end, an embodiment of the present invention provides a post-spark bus residual electricity recovery circuit to solve the problems of increased bus voltage after spark discharge, untimely bus voltage consumption and delayed response during the operation of the prior art electrostatic precipitator.

[0007] In order to achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0008] A post-spark busbar excess electricity recovery circuit, the excess electricity recovery circuit is applied to the power supply circuit of an electrostatic precipitator, the power supply circuit includes a rectifier and voltage regulator module, a filter inductor L, a busbar filter capacitor C0 and a load module, the input end of the rectifier and voltage regulator module is used to receive a 380V AC voltage, the first output end of the rectifier and voltage regulator module is connected to the first end of the filter inductor L, the second end of the filter inductor L is respectively connected to the first end of the busbar filter capacitor C0 and the first input end of the load module, the second output end of the rectifier and voltage regulator module and the second end of the busbar filter capacitor C0 are respectively connected to the second input end of the load module;

[0009] The surplus power recycling circuit includes a controller, a surplus power recovery and storage circuit, a surplus power recovery and storage control circuit, and a surplus power recycling control circuit;

[0010] The first input end of the surplus power recovery storage circuit is connected to the second end of the filter inductor L, the second input end of the surplus power recovery storage circuit is connected to the first output end of the surplus power recovery storage control circuit, and the third input end of the surplus power recovery storage circuit is connected to the first output end of the surplus power recycling control circuit; the first output end of the surplus power recovery storage circuit is connected to the first input end of the surplus power recovery storage control circuit, and the second output end of the surplus power recovery storage circuit is connected to the first input end of the surplus power recycling control circuit;

[0011] The second input terminal of the surplus power recovery and storage control circuit is connected to the first output terminal of the controller;

[0012] The second input terminal of the surplus power recycling control circuit is connected to the second output terminal of the controller, and the second output terminal of the surplus power recycling control circuit is connected to the first input terminal of the controller; the third output terminal of the controller is connected to the input terminal of the rectifier and voltage regulator module;

[0013] Among them, the controller is used to receive spark signals, bus real-time voltage signals and residual power storage voltage signals, and coordinate the operation of the residual power recovery and storage circuit, the residual power recovery and storage control circuit and the residual power recycling control circuit by generating control signals; the residual power recovery and storage circuit is used to quickly recover and store the bus residual power after the spark occurs; the residual power recovery and storage control circuit is used to monitor the bus voltage in real time, and dynamically reduce the bus voltage to the target value by adjusting the switching frequency of the residual power recovery and storage circuit; the residual power recycling control circuit is used to gradually release the stored electric energy to the bus after the spark lockout ends, to ensure a smooth transition of the bus voltage and realize the recycling of residual power.

[0014] Optionally, the excess power recovery and storage circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a first diode D1, a first capacitor Ch and a first reactor L1;

[0015] The first end of the first MOS transistor Q1 is connected to the first output end of the surplus power recovery and storage circuit, the second end of the first MOS transistor Q1 is connected to the second output end of the rectifier and voltage regulator module, and the third end of the first MOS transistor Q1 is connected to the first end of the first diode D1 and the first end of the first reactor L1 respectively;

[0016] A first end of the second MOS transistor Q2 is connected to the first output end of the controller, a second end of the second MOS transistor Q2 is connected to the second end of the first diode D1 and the first end of the first capacitor Ch respectively, and a third end of the second MOS transistor Q2 is connected to the second end of the filter inductor L;

[0017] The second end of the first reactor L1 is connected to the second end of the filter inductor L, and the second end of the first capacitor Ch is connected to the second output end of the rectifier and voltage regulator module.

[0018] Optionally, the surplus power recovery control circuit includes a first voltage sampling and storage circuit, a first voltage sampling and tracking control circuit, and a second voltage sampling and tracking control circuit;

[0019] The first input terminal of the first voltage sampling and storage circuit is connected to the first target connection terminal, the first output terminal of the first voltage sampling and tracking control circuit is connected to the first input terminal of the first voltage sampling and tracking control circuit and the first input terminal of the second voltage sampling and tracking control circuit respectively, and the second output terminal of the first voltage sampling and tracking control circuit is connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively;

[0020] The third input terminal of the first voltage sampling and tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the first voltage sampling and tracking control circuit is connected to the second output terminal of the controller, the first output terminal of the first voltage sampling and tracking control circuit is connected to the first input terminal of the residual power recycling control circuit, and the second output terminal of the first voltage sampling and tracking control circuit is connected to the first terminal of the first MOS transistor Q1;

[0021] The third input terminal of the second voltage sampling and tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the second voltage sampling and tracking control circuit is connected to the third output terminal of the first voltage sampling and tracking control circuit, the first output terminal of the second voltage sampling and tracking control circuit is connected to the second input terminal of the first voltage sampling and storage circuit, and the second output terminal of the second voltage sampling and tracking control circuit is connected to the third input terminal of the first voltage sampling and storage circuit;

[0022] The first target connection end is a connection end between the second end of the first reactor L1 and the second end of the filter inductor L.

[0023] Optionally, the first voltage sampling and storage circuit includes a first low-pass filter, a first operational amplifier U1, a first transistor VT1, a second operational amplifier U2, and a second transistor VT2;

[0024] The first low-pass filter includes a third resistor R3 and a first capacitor C1, a first end of the third resistor R3 is connected to the first target connection end, and a second end of the third resistor R3 is connected to the first end of the first capacitor C1 and the non-inverting input end of the first operational amplifier U1 respectively;

[0025] The inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1; the output terminal of the first operational amplifier U1 is respectively connected to the first terminal of the fourth resistor R4, the first input terminal of the first voltage sampling and tracking control circuit, and the first input terminal of the second voltage sampling and tracking control circuit; the second terminal of the fourth resistor R4 is connected to the first terminal of the first transistor VT1;

[0026] The second end of the first transistor VT1 is connected to the first end of the fifth resistor R5, the first end of the second capacitor C2 and the non-inverting input end of the second operational amplifier U2 respectively; the third end of the first transistor VT1 is connected to the first output end of the second voltage sampling and tracking control circuit;

[0027] The inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is also connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively;

[0028] The second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded;

[0029] The second end of the fifth resistor R5 is connected to the first end of the second transistor VT2, the second end of the second transistor VT2 is grounded, and the third end of the second transistor VT2 is connected to the second output end of the second voltage sampling and tracking control circuit.

[0030] Optionally, the first voltage sampling and tracking control circuit includes a third operational amplifier U3, a first comparator U4, a first inverter U5, a first AND gate U6 and a second AND gate U7;

[0031] The non-inverting input terminal of the third operational amplifier U3 is respectively connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the inverting input terminal of the third operational amplifier U3 is respectively connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9, and the output terminal of the third operational amplifier U3 is respectively connected to the second end of the ninth resistor R9 and the first end of the eleventh resistor R11; the second end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U2, and the second end of the seventh resistor R7 is grounded; the second end of the eighth resistor R8 is connected to the first end of the adjustable resistor RP2, the second end of the adjustable resistor RP2 is connected to the 5V voltage output terminal, the third end of the adjustable resistor RP2 is connected to the first end of the twelfth resistor R12, and the second end of the twelfth resistor R12 is grounded;

[0032] The non-inverting input terminal of the first comparator U4 is connected to the second end of the eleventh resistor R11 and the first end of the third capacitor C3, respectively; the inverting input terminal of the first comparator U4 is connected to the first end of the tenth resistor R10; the output terminal of the first comparator U4 is connected to the first end of the thirteenth resistor R13 and the first end of the first inverter U5, respectively; the second end of the third capacitor C3 is grounded; the second end of the tenth resistor R10 is connected to the output end of the first operational amplifier U1 and the first input end of the residual power recycling control circuit, respectively; and the second end of the thirteenth resistor R13 is connected to the 5V voltage output terminal.

[0033] The second end of the first inverter U5 is connected to the first input end of the first AND gate U6; the second input end of the first AND gate U6 is connected to the first output end of the controller, and the first output end of the controller is used to output a spark generation signal; the output end of the first AND gate U6 is connected to the first input end of the second AND gate U7;

[0034] The second input end of the second AND gate U7 is connected to the second output end of the controller, and the second output end of the controller is used to output the fixed-frequency PWM1 signal; the output end of the second AND gate U7 is connected to the first end of the first MOS transistor Q1.

[0035] Optionally, the second voltage sampling and tracking control circuit includes a fourth operational amplifier U8, a third AND gate U9, a first OR gate U10 and a second inverter U11;

[0036] The non-inverting input terminal of the fourth operational amplifier U8 is connected to the first end of the fifteenth resistor R15, the inverting input terminal of the fourth operational amplifier U8 is connected to the first end of the fourteenth resistor R14, and the output terminal of the fourth operational amplifier U8 is respectively connected to the first input terminal of the third AND gate U9 and the first end of the sixteenth resistor R16; the second end of the fifteenth resistor R15 is connected to the output terminal of the second operational amplifier U2, the second end of the fourteenth resistor R14 is connected to the output terminal of the first operational amplifier U1, and the second end of the sixteenth resistor R16 is connected to the 5V voltage output terminal;

[0037] The second input end of the third AND gate U9 is connected to the third end of the first transistor VT1 and the output end of the second inverter U11 respectively, and the output end of the third AND gate U9 is connected to the first input end of the first OR gate U10; the input end of the second inverter U11 is connected to the first output end of the controller;

[0038] The second input terminal of the first OR gate U10 is connected to the output terminal of the first AND gate U6 , and the output terminal of the first OR gate U10 is connected to the third terminal of the second transistor VT2 .

[0039] Optionally, the surplus power recycling control circuit includes a second voltage sampling and storage circuit, a third voltage sampling and tracking control circuit, and a fourth voltage sampling and tracking control circuit;

[0040] The first input terminal of the second voltage sampling and storage circuit is connected to the second target connection terminal, and the output terminal of the second voltage sampling and storage circuit is connected to the first input terminal of the third voltage sampling and tracking control circuit and the first input terminal of the fourth voltage sampling and tracking control circuit respectively;

[0041] The second input terminal of the third voltage sampling and tracking control circuit is connected to the first output terminal of the first voltage sampling and tracking control circuit, the third input terminal of the third voltage sampling and tracking control circuit is connected to the first output terminal of the controller, and the first output terminal of the third voltage sampling and tracking control circuit is connected to the first terminal of the second MOS transistor Q2;

[0042] The second input terminal of the fourth voltage sampling and tracking control circuit is connected to the second output terminal of the third voltage sampling and tracking control circuit, the third input terminal of the fourth voltage sampling and tracking control circuit is connected to the second output terminal of the controller, and the output terminal of the fourth voltage sampling and tracking control circuit is connected to the second input terminal of the second voltage sampling and storage circuit;

[0043] The second target connection end is a connection end between the second end of the second MOS transistor Q2 and the second end of the first diode D1 .

[0044] Optionally, the second voltage sampling and storage circuit includes a second low-pass filter and a fifth operational amplifier U12;

[0045] The second low-pass filter includes a twentieth resistor R20 and a fifth capacitor C5, wherein a first end of the twentieth resistor R203 is connected to the second target connection end, and a second end of the twentieth resistor R20 is connected to a first end of the fifth capacitor C5 and a non-inverting input end of the fifth operational amplifier U12, respectively; and a second end of the fifth capacitor C5 is grounded.

[0046] The inverting input terminal of the fifth operational amplifier U12 is connected to the output terminal of the fifth operational amplifier U12, and the output terminal of the fifth operational amplifier U12 is connected to the first terminal of the twenty-first resistor R21 and the first input terminal of the fourth voltage sampling and tracking control circuit respectively;

[0047] The second end of the twenty-first resistor R21 is respectively connected to the first end of the twenty-second resistor 22, the first end of the sixth capacitor C6, and the first input end of the third voltage sampling and tracking control circuit; the other end of the twenty-second resistor 22 is connected to the first end of the third transistor VT3, the second end of the third transistor VT3 is grounded, and the third end of the third transistor VT3 is connected to the output end of the fourth voltage sampling and tracking control circuit; the second end of the sixth capacitor C6 is grounded.

[0048] Optionally, the third voltage sampling and tracking control circuit includes a sixth operational amplifier U13, a seventh operational amplifier U14 and a fourth AND gate U15;

[0049] The non-inverting input terminal of the sixth operational amplifier U13 is connected to the second end of the twenty-first resistor R21, the inverting input terminal of the sixth operational amplifier U13 is connected to the output terminal of the sixth operational amplifier U13, and the output terminal of the sixth operational amplifier U13 is respectively connected to the first end of the twenty-fourth resistor R24 ​​and the second input terminal of the fourth voltage sampling and tracking control circuit;

[0050] The non-inverting input terminal of the seventh operational amplifier U14 is connected to the second end of the twenty-fourth resistor R24 ​​and the first end of the seventh capacitor C7, respectively; the inverting input terminal of the seventh operational amplifier U14 is connected to the first end of the twenty-third resistor R23; the output terminal of the seventh operational amplifier U14 is connected to the first input terminal of the fourth AND gate U15; the second end of the seventh capacitor C7 is grounded; and the second end of the twenty-third resistor R23 is connected to the output terminal of the first operational amplifier U1.

[0051] The second input terminal of the fourth AND gate U15 is connected to the first output terminal of the controller, and the output terminal of the fourth AND gate U15 is connected to the first input terminal of the controller.

[0052] Optionally, the fourth voltage sampling and tracking control circuit includes a second comparator U17, a fifth AND gate U18 and a third inverter U19;

[0053] The non-inverting input terminal of the second comparator U17 is connected to the first end of the fifteenth resistor R15; the inverting input terminal of the second comparator U17 is connected to the first end of the fourteenth resistor R14; the output terminal of the second comparator U17 is connected to the first end of the sixteenth resistor R16 and the first input terminal of the fifth AND gate U18 respectively; the second end of the fifteenth resistor R15 is connected to the output terminal of the sixth operational amplifier U13, and the second end of the fourteenth resistor R14 is connected to the output terminal of the fifth operational amplifier U12; the second end of the sixteenth resistor R16 is connected to the 5V voltage output terminal;

[0054] The second input terminal of the fifth AND gate U18 is connected to the output terminal of the third inverter U19, and the output terminal of the fifth AND gate U18 is connected to the third terminal of the third transistor VT3;

[0055] An input terminal of the third inverter U19 is connected to the first output terminal of the controller.

[0056] The present invention has at least the following beneficial effects:

[0057] The present invention provides a post-spark bus residual power recovery and utilization circuit. By efficiently recovering, storing, and recycling the residual power after a spark discharge, the circuit effectively addresses the problems of increased bus voltage, untimely residual power consumption, and delayed system response in the prior art. First, the circuit uses a residual power recovery and storage circuit to quickly transfer excess energy from the bus filter capacitor C0 to the storage capacitor after a spark occurs. This prevents a rapid increase in bus voltage caused by continuous power supply from the filter inductor L and reverse charging of the inductive load, thereby preventing secondary breakdown, arcing, and other damage to the equipment caused by bus overvoltage, ensuring stable operation of the electrostatic precipitator. Second, the residual power recovery and storage control circuit monitors and adjusts the bus voltage in real time, using PWM signals to precisely control the residual power recovery process, dynamically reducing the bus voltage to a target range, and avoiding equipment failures caused by unstable bus voltage. Furthermore, after the spark lockout ends, the residual power recycling control circuit gradually releases the stored energy to the bus, preventing sudden increases or fluctuations in bus voltage while also recycling the residual power, reducing energy waste, and improving energy efficiency. The present invention also uses the unified coordinated management of the controller to collect spark signals, bus voltage signals, and residual power storage signals in real time, dynamically adjusting the residual power recovery and release process to ensure rapid system response and voltage stability. In summary, while solving the problem of increased bus voltage after spark discharge, the present invention achieves efficient utilization of residual power and dynamic and stable control of bus voltage, comprehensively improving the operating efficiency and reliability of the electrostatic precipitator, effectively overcoming the limitations of existing technologies, and representing significant technological advancement and practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] To more clearly illustrate the prior art and the present invention, the following briefly introduces the drawings required for describing the prior art and the embodiments of the present invention. Obviously, the drawings described below are merely illustrative, and those skilled in the art can derive other drawings based on the provided drawings without inventive effort.

[0059] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which the present invention can be implemented. Any structural modifications, changes in proportions, or adjustments in sizes should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention.

[0060] Figure 1 This is a circuit principle block diagram of a power supply circuit in the prior art;

[0061] Figure 2A circuit principle block diagram of a power supply circuit and a surplus power recovery circuit provided in an embodiment of the present invention;

[0062] Figure 3 A circuit schematic diagram of a surplus power recovery and storage circuit provided by an embodiment of the present invention;

[0063] Figure 4 A circuit schematic diagram of a surplus power recovery and storage control circuit provided by an embodiment of the present invention;

[0064] Figure 5 A circuit schematic diagram of a surplus power recycling control circuit provided by an embodiment of the present invention;

[0065] Figure 6 This is a functional block diagram of a surplus power recycling control circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0067] In the description of the present invention, unless otherwise specified, "plurality" means two or more. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are intended to distinguish the objects referred to. For schemes with a sequential flow, this terminology does not necessarily need to be understood as describing a specific order or sequence. For schemes with device structures, this terminology does not distinguish between the degree of importance, positional relationship, etc.

[0068] In addition, the terms "comprise", "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that have been explicitly listed, but may also include other steps or units that are not explicitly listed but are inherent to these processes, methods, products or apparatuses, or steps or units that are added based on further optimization solutions conceived by the present invention.

[0069] Below, the implementation background of the technical solution provided in the embodiment of this application is introduced.

[0070] As a key equipment for removing smoke and dust from production waste gas, electrostatic precipitator has become an essential facility in thermal power plants, steel mills, etc., and the market demand is strong.

[0071] An electrostatic precipitator is a purification device that uses electrostatic field forces to remove suspended particles entrained in airflow. Under the action of high-voltage electric field forces, the charged dust is adsorbed on the dust collecting electrode, reducing the concentration of particulate matter in the exhaust flue gas, thereby achieving the purpose of improving air quality and reducing environmental pollution. Compared with other dust removal equipment, the electrostatic precipitator has the advantages of high-efficiency dust removal effect, low energy consumption operation state, low equipment operation resistance and large-scale flue gas treatment capacity.

[0072] During electrostatic precipitator operation, the dust composition, temperature and humidity, and the cathode and anode inside the precipitator are affected by numerous uncontrollable factors, which can cause changes in withstand voltage and spark flashover, also known as discharge, within the precipitator. When this occurs, a prompt judgment must be made and the power module must be shut down to stop supplying power to the precipitator. During this process, the bus voltage continues to rise after positive charging at the rectifier and reverse charging at the inductive load, due to the inability to immediately disconnect the power supply at the rectifier and voltage regulator, and the sudden disconnection of the inductive load. This increased bus voltage is greater than the bus voltage at the time of discharge. When the spark lockout period expires and the load is about to be reconnected, direct power cannot be supplied at this bus voltage to prevent secondary breakdown, which could reduce dust removal efficiency and cause overvoltage damage to the inverter unit and load-side components.

[0073] At present, the existing domestic electrostatic precipitator power supply equipment handles the increase in bus voltage after sparking:

[0074] A discharge resistor or a controllable discharge circuit is connected in parallel to the bus filter capacitor end. During the spark lockout period, the bus voltage is consumed by the resistor or the controllable discharge circuit.

[0075] After the spark lockout time is over, the inverter circuit is opened first, and the bus voltage is reduced by connecting the load. After the bus voltage is reduced, the front-end rectifier voltage regulation circuit is opened.

[0076] According to the above commonly used methods for dealing with the increase in bus voltage after a spark, it can be seen that they all reduce the bus voltage consumption by connecting a discharge resistor or a controllable discharge circuit and by connecting a rear-end load. This is at the expense of dust removal efficiency and waste of electric energy to prevent secondary breakdown and ensure the stability of load-end components. It fails to fundamentally solve the problem of the bus voltage continuing to increase due to various factors after a spark occurs.

[0077] like Figure 1As shown, in the first power supply equipment processing method mentioned above, since the front-end rectifier and voltage regulator module cannot be shut down immediately after the spark occurs, the bus filter capacitor C0 continues to be charged after the spark, thereby increasing the bus voltage. Even if it is shut down immediately, due to the existence of the filter inductor L in the circuit, the magnetic energy stored in the inductor continues to power the bus filter capacitor after the spark occurs, thereby continuing to increase the bus voltage; if the rectifier and voltage regulator module operates at the rated value when the spark occurs, the bus voltage will definitely exceed the rated DC540V after the spark. The impact of the bus voltage increase after the spark on the main circuit components is not solved. The only way is to improve the selection standards of the components to ensure the stable operation of the circuit, and open the controllable discharge circuit during the spark lockout period to achieve the purpose of reducing the bus voltage. However, the resulting energy waste is inevitable, and the method of connecting a parallel discharge resistor is even more of a continuous waste of energy.

[0078] The second power supply equipment processing method mentioned above waits for the spark lockout time to end and then uses the method of connecting to the load end to lower the bus voltage. Although it can reduce the bus voltage to a certain extent, it cannot guarantee that secondary breakdown can be prevented, and even "arcing" may occur. Once secondary breakdown or "arcing" occurs, the dust removal efficiency may continue to decline, the stability of equipment components, and the waste of electric energy may be affected; and the amount of bus reduction by this method is not controllable, and the random changes at the load end are very likely to cause the bus voltage to be suddenly "evacuated". At this time, turning on the front-end rectifier and voltage regulation part may easily cause the bus to oscillate, affecting the output of the secondary voltage and thus affecting the dust removal efficiency of the dust collector, and affecting the stability of the components.

[0079] All of the above treatment methods cannot effectively deal with the increase in bus voltage after sparks. They can only ensure the stability of the circuit by selecting higher capacitors. Even so, it is difficult to guarantee the service life of components. They all reduce the bus voltage by wasting electric energy. They all sacrifice dust removal efficiency to prevent secondary breakdown and other conditions. This will inevitably reduce dust removal efficiency, waste electric energy and affect the stability of circuit operation.

[0080] Therefore, during the operation of existing electrostatic precipitators, the increase in bus voltage after spark discharge, the untimely consumption of bus voltage and the delayed response have become problems that need to be solved urgently.

[0081] Next, some specific embodiments and drawings are used to describe in detail how the present application solves the problems of increased bus voltage after spark discharge, untimely consumption of bus voltage and delayed response during the operation of the above-mentioned existing electrostatic precipitator.

[0082] like Figure 2As shown, an embodiment of the present application provides a post-spark bus residual electricity recovery and utilization circuit, which is applied to the power supply circuit of an electrostatic precipitator. The power supply circuit includes a rectifier and voltage regulation module, a filter inductor L, a bus filter capacitor C0 and a load module. The input end of the rectifier and voltage regulation module is used to access a 380V AC voltage, the first output end of the rectifier and voltage regulation module is connected to the first end of the filter inductor L, the second end of the filter inductor L is respectively connected to the first end of the bus filter capacitor C0 and the first input end of the load module, the second output end of the rectifier and voltage regulation module and the second end of the bus filter capacitor C0 are respectively connected to the second input end of the load module.

[0083] The surplus power recycling circuit includes a controller, a surplus power recycling storage circuit, a surplus power recycling storage control circuit and a surplus power recycling control circuit.

[0084] The first input end of the surplus power recovery and storage circuit is connected to the second end of the filter inductor L, the second input end of the surplus power recovery and storage circuit is connected to the first output end of the surplus power recovery and storage control circuit, and the third input end of the surplus power recovery and storage circuit is connected to the first output end of the surplus power recycling control circuit; the first output end of the surplus power recovery and storage circuit is connected to the first input end of the surplus power recovery and storage control circuit, and the second output end of the surplus power recovery and storage circuit is connected to the first input end of the surplus power recycling control circuit.

[0085] The second input end of the surplus power recovery and storage control circuit is connected to the first output end of the controller.

[0086] The second input end of the surplus power recycling control circuit is connected to the second output end of the controller, and the second output end of the surplus power recycling control circuit is connected to the first input end of the controller; the third output end of the controller is connected to the input end of the rectifier and voltage regulation module.

[0087] Among them, the controller is used to receive spark signals, bus real-time voltage signals and residual power storage voltage signals, and coordinate the operation of the residual power recovery and storage circuit, the residual power recovery and storage control circuit and the residual power recycling control circuit by generating control signals; the residual power recovery and storage circuit is used to quickly recover and store the bus residual power after the spark occurs; the residual power recovery and storage control circuit is used to monitor the bus voltage in real time, and dynamically reduce the bus voltage to the target value by adjusting the switching frequency of the residual power recovery and storage circuit; the residual power recycling control circuit is used to gradually release the stored electric energy to the bus after the spark lockout ends, to ensure a smooth transition of the bus voltage and realize the recycling of residual power.

[0088] Among them, this application discloses a circuit for recycling excess power in busbar after spark. Figure 2As shown: a surplus power recovery and storage circuit is connected in parallel before the filter capacitor C1, and a surplus power recovery and storage control circuit and a surplus power recycling control circuit are matched at the same time.

[0089] The circuit is currently used to control the recovery and recycling of excess power on the bus after a spark in a high-voltage electrostatic precipitator power supply. When a discharge occurs inside the electrostatic precipitator, since the rectifier and voltage regulator modules are mostly three-phase fully controlled bridge rectifiers composed of thyristors, and a filter inductor L is usually connected in series after the rectifier and voltage regulator module for filtering, the thyristors cannot be turned off in time after the spark, and the magnetic energy stored in the filter inductor L will continue to supply power to the bus filter capacitor C0. When the discharge occurs, the IGBT is suddenly turned off, cutting off the rear-end inductive load module (rectifier transformer), and the load module will cause reverse charging of the bus filter capacitor C0 through the IGBT freewheeling diode. In this way, the bus filter capacitor C0 is delayed by the thyristor shutdown and the power supply of the filter inductor L, as well as the reverse charging of the inductive load, causing the bus voltage value after the spark to be higher than the bus voltage given by the system. Its characteristic is that after the spark signal appears, the bus voltage will increase by a certain value and remain unchanged. Based on this characteristic, the circuit is applied to a high-voltage electrostatic precipitator power supply, which can achieve the stabilization of the bus voltage after the spark and the collection of the bus residual electricity. This process can effectively prevent the bus voltage from being forced to rise after the spark, prevent damage to the components of the rectifier and voltage regulator module, the bus filter capacitor C0, and the inverter module, and recycle and store the residual electricity, and reduce the bus voltage value to an ideal preset value according to system requirements, so as to achieve energy saving, reduce bus ripple, improve dust collection efficiency, and prevent secondary breakdown while ensuring circuit stability.

[0090] The rectifier and voltage regulator module receives 380V AC power, rectifies it, and outputs a stable DC voltage. The output of the rectifier and voltage regulator module is connected to the bus filter capacitor C0 through the filter inductor L, providing a smooth voltage for the power bus.

[0091] The bus filter capacitor C0 is used to filter and stabilize the bus voltage and is connected to the load module to ensure the normal operation of the load.

[0092] The input of the excess power recovery and storage circuit is connected to the output of the filter inductor L, and is also connected to the excess power recovery and storage control circuit and the excess power recycling control circuit. Its core components include storage capacitors, switching devices (such as MOS transistors), diodes, and reactors, which can quickly store excess power on the bus and convert it into reusable electrical energy.

[0093] The excess power recovery and storage control circuit samples the bus voltage signal in real time, compares it with the target voltage value, and realizes dynamic adjustment of the bus voltage by controlling the switching frequency and duty cycle in the excess power recovery and storage circuit.

[0094] After the spark lockout time ends, the residual power recycling control circuit gradually releases the electric energy stored in the residual power recovery storage circuit to the bus, realizing the recycling of residual power and ensuring a smooth transition of the bus voltage.

[0095] When a spark occurs: After the spark signal is triggered, the controller turns off the rectifier and voltage regulator module and stops supplying power to the bus. At the same time, the residual power recovery and storage control circuit controls the switching device action in the residual power recovery and storage circuit, and quickly transfers the residual power in the bus filter capacitor C0 to the storage capacitor, reducing the bus voltage to the target range.

[0096] During spark lockout: the residual power recovery storage circuit continuously recovers residual power from the bus, and the controller dynamically adjusts the recovery frequency based on the real-time sampled bus voltage signal to ensure that the bus voltage is stable within a safe range.

[0097] After spark arrest, the controller uses the residual power recycling control circuit to gradually release the energy in the storage capacitor to the busbar, while restarting the rectifier and voltage regulator module to ensure a smooth recovery of the busbar voltage. The release process gradually increases the duty cycle of the PWM signal to prevent busbar voltage fluctuations or sudden increases.

[0098] The present invention cooperates with the residual electricity recovery storage circuit and the residual electricity recovery storage control circuit to quickly transfer the residual electricity on the bus to the storage capacitor after a spark occurs, thereby avoiding the bus voltage from rising rapidly due to the continuous power supply of the filter inductor and the reverse charging of the inductive load, thereby effectively avoiding the secondary breakdown or arcing of the equipment that may be caused by the excessively high bus voltage, and protecting the normal operation of the electrostatic precipitator.

[0099] During the spark lockout period, the residual power recovery and storage circuit dynamically and continuously recovers excess energy from the busbar and stores it in capacitors, avoiding energy waste. At the same time, after the spark lockout period expires, the residual power recycling control circuit gradually releases the stored energy to the busbar, recycling the residual power and improving energy efficiency.

[0100] This invention uses a residual energy recovery and storage control circuit and controller to sample the bus voltage in real time, compare it with a preset target voltage, and dynamically adjust the operating state of the residual energy recovery and storage circuit to ensure that the bus voltage remains within a safe range. After spark arrest, the residual energy recycling control circuit gradually releases the stored energy through a PWM signal, ensuring a smooth transition of the bus voltage, avoiding sudden surges or overshoots, and improving system voltage stability.

[0101] Spark discharges are a common phenomenon in electrostatic precipitators. Improper handling can lead to equipment damage and reduced dust removal efficiency. This invention addresses the issues of increased bus voltage and untimely consumption after spark discharges through a highly efficient excess power recovery and utilization mechanism. This improves the reliability and stability of electrostatic precipitators, while ensuring equipment safety and extending their service life.

[0102] Compared to existing technologies, this invention achieves rapid bus voltage regulation through the controller's real-time control and feedback mechanism, avoiding bus voltage fluctuations or instability caused by system response delays. The excess power recovery and release processes are precisely controlled by PWM signals, ensuring rapid response and stable operation of the entire system.

[0103] The present invention reduces the waste of electric energy by efficiently recovering and recycling the surplus electricity, avoids the problem of equipment damage caused by spark discharge, reduces equipment maintenance and operation costs, and improves the economic benefits of the system.

[0104] The present invention provides a post-spark bus residual power recovery and utilization circuit. By efficiently recovering, storing, and recycling the residual power after a spark discharge, the circuit effectively addresses the problems of increased bus voltage, untimely residual power consumption, and delayed system response in the prior art. First, the circuit uses a residual power recovery and storage circuit to quickly transfer excess energy from the bus filter capacitor C0 to the storage capacitor after a spark occurs. This prevents a rapid increase in bus voltage caused by continuous power supply from the filter inductor L and reverse charging of the inductive load, thereby preventing secondary breakdown, arcing, and other damage to the equipment caused by bus overvoltage, ensuring stable operation of the electrostatic precipitator. Second, the residual power recovery and storage control circuit monitors and adjusts the bus voltage in real time, using PWM signals to precisely control the residual power recovery process, dynamically reducing the bus voltage to a target range, and avoiding equipment failures caused by unstable bus voltage. Furthermore, after the spark lockout ends, the residual power recycling control circuit gradually releases the stored energy to the bus, preventing sudden increases or fluctuations in bus voltage while also recycling the residual power, reducing energy waste, and improving energy efficiency. The present invention also uses the unified coordinated management of the controller to collect spark signals, bus voltage signals, and residual power storage signals in real time, dynamically adjusting the residual power recovery and release process to ensure rapid system response and voltage stability. In summary, while solving the problem of increased bus voltage after spark discharge, the present invention achieves efficient utilization of residual power and dynamic and stable control of bus voltage, comprehensively improving the operating efficiency and reliability of the electrostatic precipitator, effectively overcoming the limitations of existing technologies, and representing significant technological advancement and practical application value.

[0105] like Figure 3As shown, in a possible embodiment, the excess power recovery and storage circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a first diode D1, a first capacitor Ch and a first reactor L1.

[0106] The first end of the first MOS transistor Q1 is connected to the first output end of the surplus power recovery and storage circuit, the second end of the first MOS transistor Q1 is connected to the second output end of the rectifier and voltage regulator module, and the third end of the first MOS transistor Q1 is respectively connected to the first end of the first diode D1 and the first end of the first reactor L1.

[0107] A first end of the second MOS transistor Q2 is connected to the first output end of the controller, a second end of the second MOS transistor Q2 is connected to the second end of the first diode D1 and the first end of the first capacitor Ch respectively, and a third end of the second MOS transistor Q2 is connected to the second end of the filter inductor L.

[0108] The second end of the first reactor L1 is connected to the second end of the filter inductor L, and the second end of the first capacitor Ch is connected to the second output end of the rectifier and voltage regulator module.

[0109] It should be noted that, by collecting the real-time voltage values ​​of points A (first target connection end) and B (second target connection end), the residual power recovery and storage control circuit will promptly collect the increased bus voltage caused by the delayed shutdown of the rectifier and voltage regulation part and the continued power supply of the filter inductor L after the spark occurs, as well as the increased bus voltage caused by the continuous current reverse charging due to the sudden disconnection of the inductive load, into the residual power recovery and storage circuit, so as to ensure the stability of the bus voltage. Moreover, through this control circuit, the bus voltage can be reduced to an ideal preset voltage value, without wasting electric energy, and preventing secondary breakdown and "arcing" phenomena when the rear-end load is connected again; when the spark lockout time ends, the inverter module is turned on, and the electric energy of the capacitor Ch in the residual power recovery and storage circuit is supplied to the bus through the residual power recycling control circuit until the electric energy in the residual power recovery circuit can no longer support the bus voltage, and the rectifier and voltage regulation part is opened in time to ensure the stability of the bus voltage, thereby realizing the recovery and recycling of the bus residual power after the spark is controlled.

[0110] The residual power recovery and storage circuit is an H-type circuit consisting of two NMOS tubes Q1 and Q2, a diode D1, a capacitor Ch, and a reactor L1. When there is no spark, Q1 tube is closed and Q2 tube remains open. The storage capacitor Ch is connected in parallel with the bus filter capacitor C1 to filter the rectified bus. When a spark occurs, Q2 tube is turned off and Q1 tube is turned on. The electrical energy in the filter capacitor C1 is converted into the magnetic energy of L1, and then Q1 tube is turned off. The magnetic energy of L1 is converted into electrical energy through the diode D1 and stored in the storage capacitor Ch. In this way, Q1 tube is turned on and off at a fixed frequency (according to Resonant frequency formula, the specific switching frequency is determined by the values ​​of L1 and C1), after the voltage on the bus filter capacitor C1, that is, the voltage on the bus, is reduced to the ideal preset value, the Q1 tube is turned off, so that the residual power of the bus after the spark occurs is transferred to the storage capacitor Ch; after the spark lockout time ends, the rectifier and voltage regulation module is not turned on temporarily, but the switch of the Q2 tube is controlled at a fixed frequency with a gradually increasing duty cycle, so that the power in the storage capacitor Ch is gradually charged to the bus, so as to realize the recycling of the residual power after the spark occurs; when the voltage of Ch can no longer support the bus voltage, the rectifier and voltage regulation part is turned on in time to ensure the stability of the bus voltage.

[0111] like Figure 4 As shown, in a possible embodiment, the residual power recovery control circuit includes a first voltage sampling and storage circuit, a first voltage sampling and tracking control circuit, and a second voltage sampling and tracking control circuit;

[0112] The first input terminal of the first voltage sampling and storage circuit is connected to the first target connection terminal, the first output terminal of the first voltage sampling and tracking control circuit is connected to the first input terminal of the first voltage sampling and tracking control circuit and the first input terminal of the second voltage sampling and tracking control circuit respectively, and the second output terminal of the first voltage sampling and tracking control circuit is connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively;

[0113] The third input terminal of the first voltage sampling and tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the first voltage sampling and tracking control circuit is connected to the second output terminal of the controller, the first output terminal of the first voltage sampling and tracking control circuit is connected to the first input terminal of the residual power recycling control circuit, and the second output terminal of the first voltage sampling and tracking control circuit is connected to the first terminal of the first MOS transistor Q1;

[0114] The third input terminal of the second voltage sampling and tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the second voltage sampling and tracking control circuit is connected to the third output terminal of the first voltage sampling and tracking control circuit, the first output terminal of the second voltage sampling and tracking control circuit is connected to the second input terminal of the first voltage sampling and storage circuit, and the second output terminal of the second voltage sampling and tracking control circuit is connected to the third input terminal of the first voltage sampling and storage circuit;

[0115] The first target connection end is a connection end between the second end of the first reactor L1 and the second end of the filter inductor L.

[0116] like Figure 4 As shown, in a possible embodiment, the first voltage sampling and storage circuit includes a first low-pass filter, a first operational amplifier U1, a first transistor VT1, a second operational amplifier U2 and a second transistor VT2;

[0117] The first low-pass filter includes a third resistor R3 and a first capacitor C1, a first end of the third resistor R3 is connected to the first target connection end, and a second end of the third resistor R3 is connected to the first end of the first capacitor C1 and the non-inverting input end of the first operational amplifier U1 respectively;

[0118] The inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1; the output terminal of the first operational amplifier U1 is respectively connected to the first terminal of the fourth resistor R4, the first input terminal of the first voltage sampling and tracking control circuit, and the first input terminal of the second voltage sampling and tracking control circuit; the second terminal of the fourth resistor R4 is connected to the first terminal of the first transistor VT1;

[0119] The second end of the first transistor VT1 is connected to the first end of the fifth resistor R5, the first end of the second capacitor C2 and the non-inverting input end of the second operational amplifier U2 respectively; the third end of the first transistor VT1 is connected to the first output end of the second voltage sampling and tracking control circuit;

[0120] The inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is also connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively;

[0121] The second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded;

[0122] The second end of the fifth resistor R5 is connected to the first end of the second transistor VT2, the second end of the second transistor VT2 is grounded, and the third end of the second transistor VT2 is connected to the second output end of the second voltage sampling and tracking control circuit.

[0123] like Figure 4 As shown, in a possible embodiment, the first voltage sampling and tracking control circuit includes a third operational amplifier U3, a first comparator U4, a first inverter U5, a first AND gate U6 and a second AND gate U7;

[0124] The non-inverting input terminal of the third operational amplifier U3 is respectively connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the inverting input terminal of the third operational amplifier U3 is respectively connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9, and the output terminal of the third operational amplifier U3 is respectively connected to the second end of the ninth resistor R9 and the first end of the eleventh resistor R11; the second end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U2, and the second end of the seventh resistor R7 is grounded; the second end of the eighth resistor R8 is connected to the first end of the adjustable resistor RP2, the second end of the adjustable resistor RP2 is connected to the 5V voltage output terminal, the third end of the adjustable resistor RP2 is connected to the first end of the twelfth resistor R12, and the second end of the twelfth resistor R12 is grounded;

[0125] The non-inverting input terminal of the first comparator U4 is connected to the second end of the eleventh resistor R11 and the first end of the third capacitor C3, respectively; the inverting input terminal of the first comparator U4 is connected to the first end of the tenth resistor R10; the output terminal of the first comparator U4 is connected to the first end of the thirteenth resistor R13 and the first end of the first inverter U5, respectively; the second end of the third capacitor C3 is grounded; the second end of the tenth resistor R10 is connected to the output end of the first operational amplifier U1 and the first input end of the residual power recycling control circuit, respectively; and the second end of the thirteenth resistor R13 is connected to the 5V voltage output terminal.

[0126] The second end of the first inverter U5 is connected to the first input end of the first AND gate U6; the second input end of the first AND gate U6 is connected to the first output end of the controller, and the first output end of the controller is used to output a spark generation signal; the output end of the first AND gate U6 is connected to the first input end of the second AND gate U7;

[0127] The second input end of the second AND gate U7 is connected to the second output end of the controller, and the second output end of the controller is used to output the fixed-frequency PWM1 signal; the output end of the second AND gate U7 is connected to the first end of the first MOS transistor Q1.

[0128] like Figure 4 As shown, in a possible embodiment, the second voltage sampling and tracking control circuit includes a fourth operational amplifier U8, a third AND gate U9, a first OR gate U10 and a second inverter U11;

[0129] The non-inverting input terminal of the fourth operational amplifier U8 is connected to the first end of the fifteenth resistor R15, the inverting input terminal of the fourth operational amplifier U8 is connected to the first end of the fourteenth resistor R14, and the output terminal of the fourth operational amplifier U8 is respectively connected to the first input terminal of the third AND gate U9 and the first end of the sixteenth resistor R16; the second end of the fifteenth resistor R15 is connected to the output terminal of the second operational amplifier U2, the second end of the fourteenth resistor R14 is connected to the output terminal of the first operational amplifier U1, and the second end of the sixteenth resistor R16 is connected to the 5V voltage output terminal;

[0130] The second input end of the third AND gate U9 is connected to the third end of the first transistor VT1 and the output end of the second inverter U11 respectively, and the output end of the third AND gate U9 is connected to the first input end of the first OR gate U10; the input end of the second inverter U11 is connected to the first output end of the controller;

[0131] The second input terminal of the first OR gate U10 is connected to the output terminal of the first AND gate U6 , and the output terminal of the first OR gate U10 is connected to the third terminal of the second transistor VT2 .

[0132] like Figure 4It can be seen that the bus voltage at point A is taken out through the DC voltage sampling board and then passes through the low-pass filter composed of the residual power recovery storage control circuit resistor R3 and capacitor C1; it enters the operational amplifier U1-3, U1-2 and U1-6 to form follower 1 to enhance the driving ability of the DC voltage sampling signal. The output end of U1-6 of follower 1 is the real-time bus voltage sampling value at point A (due to the lag of the low-pass filter, the so-called real-time bus voltage value here is delayed compared with the actual bus voltage value); the output end U1-6 of follower 1 is connected to the C collector of transistor VT1 through resistor R4, and the E emitter of transistor VT1 is connected to the storage of bus voltage sampling. The upper end of capacitor C2 and the base of transistor VT1 are controlled by the spark signal. When there is no spark, the spark signal is at a low level and is connected to the B base of transistor VT1 through inverter U11, so that transistor VT1 remains turned on. The voltage on the bus sampling storage capacitor C2 is the bus voltage. Due to the existence of the front-end low-pass filter (low-pass filter signal hysteresis), this voltage is the bus voltage at the previous moment. After the spark occurs, the B base of transistor VT1 is controlled to disconnect VT1, and the bus voltage at the moment before the spark is stored on capacitor C2; the upper end of resistor R5 is connected to the storage capacitor C2 and connected to U2-3, and the lower end of resistor R5 is connected to the C base of transistor VT2. The electrodes are connected and connected in parallel with the C2 capacitor to form a controllable discharge loop; the operational amplifier U2-3 is connected to the E emitter of the transistor VT1, the upper end of the resistor R5, and the upper end of the storage capacitor C2, and the operational amplifiers U2-2 and U2-6 are connected to form a follower 2 to enhance the driving capability and anti-interference capability; after the output of the follower 2 is transmitted through the resistor R6 and the upper end of the resistor R7, it is connected to U3-3, the lower end of the resistor R7 is grounded, the resistor R8 and one end of the resistor R9 are connected to U3-2, and the other end of the resistor R9 is connected to U3-6. The resistors R6, R7, R8, R9 and the amplifier U3 form a subtractor, and the adjustable resistor RP2 is connected to the resistor R12 and connected to the other end of the resistor R8. , forming a step-down difference circuit, and the step-down difference is independently adjusted by the adjustable resistor RP2; the bus voltage stored in C2 and the step-down difference circuit pass through the subtractor circuit to obtain the ideal preset target bus voltage value; the output end of U3-6 is connected to the comparator U4-5 through the resistor R11, and U4-4 is connected to U1-6. The resistors R10, R11 and the operational amplifier U4 form a comparator, and the preset target bus voltage value output by the subtractor is compared with the real-time bus voltage value at point A through the U4 comparator. When the target bus voltage value is less than the real-time bus voltage value, the comparator outputs a low level, and when the target voltage value is greater than or equal to the real-time bus voltage value, the comparator outputs a high level;The comparison result is output to the U5 inverter through U4-2 and connected to the input of the U6 AND gate. The spark generation signal output by the CPU is connected to the other input of the U6 AND gate. When the spark occurs, the bus voltage has not yet dropped to the preset target bus voltage value. The output of the U6 AND gate is connected to the input of the U7 AND gate at a high level. The other input of the U7 AND gate is connected to the PWM1 output by the CPU. In this way, the output of the U7 AND gate uses the PWM1 to control the closing and conduction of the Q1 tube in the residual power recovery storage circuit (the frequency of PWM1 is calculated by the inductor L1 and the filter capacitor C1 in the residual power recovery storage circuit) to realize the residual power recovery and storage function of the control bus. Otherwise, the output of the U6 AND gate is connected to the input of the U7 AND gate at a low level; the output of the U7 AND gate stops outputting PWM1 and disconnects the Q1 tube in the residual power recovery storage circuit. In addition, the output of follower 1's U1-6 is connected to op amp U8-4 via resistor R14, and the output of follower 2's U2-6 is connected to op amp U8-5 via resistor R15. Resistors R14, R15, and op amp U8 form a comparator. When the voltage of follower 2's storage capacitor C2 is higher than the real-time bus voltage at point A of front-end follower 1, comparator U8-2 outputs a high level, which is connected to the two inputs of AND gate U9, via the non-sparking signal, through NOT gate U11. This determines whether the real-time bus voltage is lower than the voltage of storage capacitor C2 in the non-sparking state. The output of AND gate U9 is high, and together with the output of comparator U4-2 (when the bus power reaches a preset value after a spark occurs), it is connected to the two inputs of OR gate U10. This controls the base B of transistor VT2 in both the sparking and non-sparking states, thereby controlling the voltage in storage capacitor C2 and achieving bus voltage tracking control in both the sparking and non-sparking states.

[0133] like Figure 5 As shown, in a possible embodiment, the residual power recycling control circuit includes a second voltage sampling and storage circuit, a third voltage sampling and tracking control circuit, and a fourth voltage sampling and tracking control circuit;

[0134] The first input terminal of the second voltage sampling and storage circuit is connected to the second target connection terminal, and the output terminal of the second voltage sampling and storage circuit is connected to the first input terminal of the third voltage sampling and tracking control circuit and the first input terminal of the fourth voltage sampling and tracking control circuit respectively;

[0135] The second input terminal of the third voltage sampling and tracking control circuit is connected to the first output terminal of the first voltage sampling and tracking control circuit, the third input terminal of the third voltage sampling and tracking control circuit is connected to the first output terminal of the controller, and the first output terminal of the third voltage sampling and tracking control circuit is connected to the first terminal of the second MOS transistor Q2;

[0136] The second input terminal of the fourth voltage sampling and tracking control circuit is connected to the second output terminal of the third voltage sampling and tracking control circuit, the third input terminal of the fourth voltage sampling and tracking control circuit is connected to the second output terminal of the controller, and the output terminal of the fourth voltage sampling and tracking control circuit is connected to the second input terminal of the second voltage sampling and storage circuit;

[0137] The second target connection end is a connection end between the second end of the second MOS transistor Q2 and the second end of the first diode D1 .

[0138] like Figure 5 As shown, in a possible embodiment, the second voltage sampling and storage circuit includes a second low-pass filter and a fifth operational amplifier U12;

[0139] The second low-pass filter includes a twentieth resistor R20 and a fifth capacitor C5, wherein a first end of the twentieth resistor R203 is connected to the second target connection end, and a second end of the twentieth resistor R20 is connected to a first end of the fifth capacitor C5 and a non-inverting input end of the fifth operational amplifier U12, respectively; and a second end of the fifth capacitor C5 is grounded.

[0140] The inverting input terminal of the fifth operational amplifier U12 is connected to the output terminal of the fifth operational amplifier U12, and the output terminal of the fifth operational amplifier U12 is connected to the first terminal of the twenty-first resistor R21 and the first input terminal of the fourth voltage sampling and tracking control circuit respectively;

[0141] The second end of the twenty-first resistor R21 is respectively connected to the first end of the twenty-second resistor 22, the first end of the sixth capacitor C6, and the first input end of the third voltage sampling and tracking control circuit; the other end of the twenty-second resistor 22 is connected to the first end of the third transistor VT3, the second end of the third transistor VT3 is grounded, and the third end of the third transistor VT3 is connected to the output end of the fourth voltage sampling and tracking control circuit; the second end of the sixth capacitor C6 is grounded.

[0142] like Figure 5 As shown, in a possible embodiment, the third voltage sampling and tracking control circuit includes a sixth operational amplifier U13, a seventh operational amplifier U14 and a fourth AND gate U15;

[0143] The non-inverting input terminal of the sixth operational amplifier U13 is connected to the second end of the twenty-first resistor R21, the inverting input terminal of the sixth operational amplifier U13 is connected to the output terminal of the sixth operational amplifier U13, and the output terminal of the sixth operational amplifier U13 is respectively connected to the first end of the twenty-fourth resistor R24 ​​and the second input terminal of the fourth voltage sampling and tracking control circuit;

[0144] The non-inverting input terminal of the seventh operational amplifier U14 is connected to the second end of the twenty-fourth resistor R24 ​​and the first end of the seventh capacitor C7, respectively; the inverting input terminal of the seventh operational amplifier U14 is connected to the first end of the twenty-third resistor R23; the output terminal of the seventh operational amplifier U14 is connected to the first input terminal of the fourth AND gate U15; the second end of the seventh capacitor C7 is grounded; and the second end of the twenty-third resistor R23 is connected to the output terminal of the first operational amplifier U1.

[0145] The second input terminal of the fourth AND gate U15 is connected to the first output terminal of the controller, and the output terminal of the fourth AND gate U15 is connected to the first input terminal of the controller.

[0146] like Figure 5 As shown, in a possible embodiment, the fourth voltage sampling and tracking control circuit includes a second comparator U17, a fifth AND gate U18 and a third inverter U19;

[0147] The non-inverting input terminal of the second comparator U17 is connected to the first end of the fifteenth resistor R15; the inverting input terminal of the second comparator U17 is connected to the first end of the fourteenth resistor R14; the output terminal of the second comparator U17 is connected to the first end of the sixteenth resistor R16 and the first input terminal of the fifth AND gate U18 respectively; the second end of the fifteenth resistor R15 is connected to the output terminal of the sixth operational amplifier U13, and the second end of the fourteenth resistor R14 is connected to the output terminal of the fifth operational amplifier U12; the second end of the sixteenth resistor R16 is connected to the 5V voltage output terminal;

[0148] The second input terminal of the fifth AND gate U18 is connected to the output terminal of the third inverter U19, and the output terminal of the fifth AND gate U18 is connected to the third terminal of the third transistor VT3;

[0149] An input terminal of the third inverter U19 is connected to the first output terminal of the controller.

[0150] like Figure 5It can be seen that the voltage at point B is taken out through the DC voltage sampling board and passes through the low-pass filter composed of R20 and C5; it enters the operational amplifier U12-3, and the operational amplifiers U12-2 and U12-6 are connected to form follower 3 to enhance the signal driving ability of the output end of U12-6. The output end of U11-6 of follower 3 is the real-time voltage value of point B (because of the hysteresis of the low-pass filter, the so-called real-time voltage value here has a certain delay compared with the actual bus voltage value); the output end of U12-6 of follower 3 is connected to the upper end of the storage capacitor C6 through the resistor R21, and the lower end of the resistor R22 is connected to the collector C of the transistor VT3 and is connected in parallel with the storage capacitor C6 to form A controllable discharge loop is formed, the upper end of the resistor R22 is connected to the storage capacitor C6 and connected to the operational amplifier U13-3, and the operational amplifier U13-2 and U13-6 are connected to form a follower 4 to improve the signal driving ability and anti-interference ability of this point. The output end of U13-6 of the follower 4 is the bus voltage stored by the storage capacitor C6; the voltage value stored in the capacitor C6 and the real-time voltage value of point B output by U12-6 are respectively connected to the comparator composed of resistors R15, R14, and operational amplifier U17 for comparison. When the bus voltage value stored in the capacitor C6 is greater than the real-time voltage value of point B, the comparator U17-2 outputs a high level to the input end of the AND gate U18. In the absence of fire When the spark occurs, the spark signal outputs a high level to the other input of the AND gate U18 through the NOT gate U19. The output of the AND gate U18 is connected to the B base of the transistor VT3 to control the opening of the transistor VT3 and discharge the voltage of the bus voltage storage capacitor C6. When the bus voltage value stored in C6 is less than or equal to the real-time voltage value of point B, the comparator U17-2 outputs a low level to the input of the AND gate U18. The AND gate U18 outputs a low level to the B base of the transistor VT3 to control the transistor VT3 to turn off, so as to achieve the purpose of real-time tracking of the voltage at point B when there is no spark. At the same time, the output of the follower 4 U13-6, that is, the voltage value stored in the storage capacitor C6, passes through the resistor R24 enters the operational amplifier U14-5, and the real-time bus voltage value at point A in the "excess power recovery control circuit" enters the operational amplifier U13-4 through the resistor R23. The resistors R23, R24, and the operational amplifier U13 form a comparator connected to the input end of the AND gate U15. If the voltage value stored in the capacitor C6, that is, the real-time voltage value at point B, is greater than the real-time bus voltage value at point A in the "excess power recovery control circuit", the comparator U14-2 outputs a high level. If the voltage value stored in the capacitor C6, that is, the real-time voltage value at point B, is less than or equal to the real-time bus voltage value at point A in the "excess power recovery control circuit", U14-2 outputs a low level. This signal is used to determine the status of excess power recycling.The spark lockout signal is connected to the other input of AND gate U15. When the spark lockout time expires and the load needs to be reconnected, the voltage stored in capacitor C6 must be greater than the real-time bus voltage at point A in the "residual energy recovery control circuit." The high-level output of AND gate U15 is connected to the CPU. The CPU controls PWM2, which automatically increases its duty cycle at a certain frequency, to control the on and off of transistor Q2 in the "residual energy recovery storage circuit." This resupplies the energy stored in Ch in the "residual energy recovery storage circuit" to the bus for recycling. When the voltage stored in capacitor C6, i.e., the real-time bus voltage at point B, is less than or equal to the real-time bus voltage at point A in the "residual energy recovery control circuit," i.e., the voltage at point B is the same as the voltage at point A, the rectifier and voltage regulator module is activated, thereby recycling the post-spark residual energy and preventing bus voltage fluctuations and reducing bus voltage ripple.

[0151] The embodiment of the present application provides a post-spark busbar residual power recovery circuit that can be widely used in high-power power supplies in industrial production situations and can be combined with a CPU to be applied to different power supply control systems. Figure 6 shown.

[0152] The present invention is based on a surplus power recovery storage circuit, a surplus power recovery control circuit and a surplus power recycling control circuit, thereby realizing the recycling of surplus power in the bus after a spark. Moreover, due to the existence of the surplus power recovery storage circuit and the surplus power recovery control circuit, when a spark occurs, the electric energy originally charged to the bus is charged to the capacitor Ch at point B through the reactor L1, and the bus voltage will not increase, thereby effectively ensuring the stable operation and service life of the components in the loop. Because the surplus power recovery control circuit can accurately track the bus voltage and preset the ideal bus voltage reduction range as needed, secondary breakdown will not occur when power is re-powered after a spark, thereby improving the dust collection efficiency. Because the surplus power recycling control circuit effectively utilizes the surplus power of the bus after the spark, when the spark ends, the surplus power in the storage circuit is recycled to the bus, thereby achieving the purpose of energy saving.

[0153] Specifically, the present application provides a post-spark bus residual electricity recovery and utilization circuit, which uses a residual electricity recovery storage circuit to store the residual electricity of the bus after the spark, thereby solving the problem of increased bus voltage after the spark; in addition, the residual electricity recovery control circuit is used to accurately and effectively control the post-spark bus voltage; the residual electricity recovery control circuit is used to accurately track the bus voltage; the residual electricity recycling control circuit is used to realize the recycling of residual electricity; and the residual electricity recycling control circuit is used to accurately track the voltage of the storage capacitor Ch.

[0154] The above specific embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0155] The technical features of the above embodiments can be combined arbitrarily (as long as there is no contradiction in the combination of these technical features). In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope of this specification.

[0156] The present invention has been described in detail and in general terms through a general description and specific embodiments. It should be noted that variations and modifications to these specific embodiments are possible without departing from the spirit of the present invention, and all such variations and modifications are within the scope of protection of this application. Therefore, the scope of protection of this patent application shall be determined by the appended claims.

Claims

1. A post-spark busbar residual electricity recovery circuit, characterized in that: The excess power recovery circuit is applied to the power supply circuit of the electrostatic precipitator, and the power supply circuit includes a rectifier and voltage regulator module, a filter inductor L, a bus filter capacitor C0 and a load module. The input end of the rectifier and voltage regulator module is used to access a 380V AC voltage. The first output end of the rectifier and voltage regulator module is connected to the first end of the filter inductor L, and the second end of the filter inductor L is respectively connected to the first end of the bus filter capacitor C0 and the first input end of the load module. The second output end of the rectifier and voltage regulator module and the second end of the bus filter capacitor C0 are respectively connected to the second input end of the load module; The surplus power recycling circuit includes a controller, a surplus power recovery and storage circuit, a surplus power recovery and storage control circuit, and a surplus power recycling control circuit; The first input end of the surplus power recovery storage circuit is connected to the second end of the filter inductor L, the second input end of the surplus power recovery storage circuit is connected to the first output end of the surplus power recovery storage control circuit, and the third input end of the surplus power recovery storage circuit is connected to the first output end of the surplus power recycling control circuit; the first output end of the surplus power recovery storage circuit is connected to the first input end of the surplus power recovery storage control circuit, and the second output end of the surplus power recovery storage circuit is connected to the first input end of the surplus power recycling control circuit; The second input terminal of the surplus power recovery and storage control circuit is connected to the first output terminal of the controller; The second input terminal of the surplus power recycling control circuit is connected to the second output terminal of the controller, and the second output terminal of the surplus power recycling control circuit is connected to the first input terminal of the controller; the third output terminal of the controller is connected to the input terminal of the rectifier and voltage regulator module; Among them, the controller is used to receive spark signals, bus real-time voltage signals and residual power storage voltage signals, and coordinate the operation of the residual power recovery and storage circuit, the residual power recovery and storage control circuit and the residual power recycling control circuit by generating control signals; the residual power recovery and storage circuit is used to quickly recover and store the bus residual power after the spark occurs; the residual power recovery and storage control circuit is used to monitor the bus voltage in real time, and dynamically reduce the bus voltage to the target value by adjusting the switching frequency of the residual power recovery and storage circuit; the residual power recycling control circuit is used to gradually release the stored electric energy to the bus after the spark lockout ends, to ensure a smooth transition of the bus voltage and realize the recycling of residual power.

2. A post-spark busbar residual electricity recovery circuit according to claim 1, characterized in that: The residual power recovery and storage circuit includes a first MOS transistor Q1, a second MOS transistor Q2, a first diode D1, a first capacitor Ch and a first reactor L1; The first end of the first MOS transistor Q1 is connected to the first output end of the surplus power recovery and storage circuit, the second end of the first MOS transistor Q1 is connected to the second output end of the rectifier and voltage regulator module, and the third end of the first MOS transistor Q1 is connected to the first end of the first diode D1 and the first end of the first reactor L1 respectively; A first end of the second MOS transistor Q2 is connected to the first output end of the controller, a second end of the second MOS transistor Q2 is connected to the second end of the first diode D1 and the first end of the first capacitor Ch respectively, and a third end of the second MOS transistor Q2 is connected to the second end of the filter inductor L; The second end of the first reactor L1 is connected to the second end of the filter inductor L, and the second end of the first capacitor Ch is connected to the second output end of the rectifier and voltage regulator module.

3. A post-spark busbar residual electricity recovery circuit according to claim 2, characterized in that: The residual power recovery control circuit includes a first voltage sampling and storage circuit, a first voltage sampling and tracking control circuit, and a second voltage sampling and tracking control circuit; The first input terminal of the first voltage sampling and storage circuit is connected to the first target connection terminal, the first output terminal of the first voltage sampling and tracking control circuit is connected to the first input terminal of the first voltage sampling and tracking control circuit and the first input terminal of the second voltage sampling and tracking control circuit respectively, and the second output terminal of the first voltage sampling and tracking control circuit is connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively; The third input terminal of the first voltage sampling and tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the first voltage sampling and tracking control circuit is connected to the second output terminal of the controller, the first output terminal of the first voltage sampling and tracking control circuit is connected to the first input terminal of the residual power recycling control circuit, and the second output terminal of the first voltage sampling and tracking control circuit is connected to the first terminal of the first MOS transistor Q1; The third input terminal of the second voltage sampling and tracking control circuit is connected to the first output terminal of the controller, the fourth input terminal of the second voltage sampling and tracking control circuit is connected to the third output terminal of the first voltage sampling and tracking control circuit, the first output terminal of the second voltage sampling and tracking control circuit is connected to the second input terminal of the first voltage sampling and storage circuit, and the second output terminal of the second voltage sampling and tracking control circuit is connected to the third input terminal of the first voltage sampling and storage circuit; The first target connection end is a connection end between the second end of the first reactor L1 and the second end of the filter inductor L.

4. A post-spark busbar residual electricity recovery circuit according to claim 3, characterized in that: The first voltage sampling and storage circuit includes a first low-pass filter, a first operational amplifier U1, a first transistor VT1, a second operational amplifier U2 and a second transistor VT2; The first low-pass filter includes a third resistor R3 and a first capacitor C1, a first end of the third resistor R3 is connected to the first target connection end, and a second end of the third resistor R3 is connected to the first end of the first capacitor C1 and the non-inverting input end of the first operational amplifier U1 respectively; The inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the first operational amplifier U1; the output terminal of the first operational amplifier U1 is respectively connected to the first terminal of the fourth resistor R4, the first input terminal of the first voltage sampling and tracking control circuit, and the first input terminal of the second voltage sampling and tracking control circuit; the second terminal of the fourth resistor R4 is connected to the first terminal of the first transistor VT1; The second end of the first transistor VT1 is connected to the first end of the fifth resistor R5, the first end of the second capacitor C2 and the non-inverting input end of the second operational amplifier U2 respectively; the third end of the first transistor VT1 is connected to the first output end of the second voltage sampling and tracking control circuit; The inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is also connected to the second input terminal of the first voltage sampling and tracking control circuit and the second input terminal of the second voltage sampling and tracking control circuit respectively; The second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded; The second end of the fifth resistor R5 is connected to the first end of the second transistor VT2, the second end of the second transistor VT2 is grounded, and the third end of the second transistor VT2 is connected to the second output end of the second voltage sampling and tracking control circuit.

5. A post-spark busbar residual electricity recovery circuit according to claim 4, characterized in that: The first voltage sampling and tracking control circuit includes a third operational amplifier U3, a first comparator U4, a first inverter U5, a first AND gate U6 and a second AND gate U7; The non-inverting input terminal of the third operational amplifier U3 is respectively connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7, the inverting input terminal of the third operational amplifier U3 is respectively connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9, and the output terminal of the third operational amplifier U3 is respectively connected to the second end of the ninth resistor R9 and the first end of the eleventh resistor R11; the second end of the sixth resistor R6 is connected to the output terminal of the second operational amplifier U2, and the second end of the seventh resistor R7 is grounded; the second end of the eighth resistor R8 is connected to the first end of the adjustable resistor RP2, the second end of the adjustable resistor RP2 is connected to the 5V voltage output terminal, the third end of the adjustable resistor RP2 is connected to the first end of the twelfth resistor R12, and the second end of the twelfth resistor R12 is grounded; The non-inverting input terminal of the first comparator U4 is connected to the second end of the eleventh resistor R11 and the first end of the third capacitor C3, respectively; the inverting input terminal of the first comparator U4 is connected to the first end of the tenth resistor R10; the output terminal of the first comparator U4 is connected to the first end of the thirteenth resistor R13 and the first end of the first inverter U5, respectively; the second end of the third capacitor C3 is grounded; the second end of the tenth resistor R10 is connected to the output end of the first operational amplifier U1 and the first input end of the residual power recycling control circuit, respectively; and the second end of the thirteenth resistor R13 is connected to the 5V voltage output terminal. The second end of the first inverter U5 is connected to the first input end of the first AND gate U6; the second input end of the first AND gate U6 is connected to the first output end of the controller, and the first output end of the controller is used to output a spark generation signal; the output end of the first AND gate U6 is connected to the first input end of the second AND gate U7; The second input end of the second AND gate U7 is connected to the second output end of the controller, and the second output end of the controller is used to output the fixed-frequency PWM1 signal; the output end of the second AND gate U7 is connected to the first end of the first MOS transistor Q1.

6. A post-spark busbar residual electricity recovery circuit according to claim 5, characterized in that: The second voltage sampling and tracking control circuit includes a fourth operational amplifier U8, a third AND gate U9, a first OR gate U10 and a second inverter U11; The non-inverting input terminal of the fourth operational amplifier U8 is connected to the first end of the fifteenth resistor R15, the inverting input terminal of the fourth operational amplifier U8 is connected to the first end of the fourteenth resistor R14, and the output terminal of the fourth operational amplifier U8 is respectively connected to the first input terminal of the third AND gate U9 and the first end of the sixteenth resistor R16; the second end of the fifteenth resistor R15 is connected to the output terminal of the second operational amplifier U2, the second end of the fourteenth resistor R14 is connected to the output terminal of the first operational amplifier U1, and the second end of the sixteenth resistor R16 is connected to the 5V voltage output terminal; The second input end of the third AND gate U9 is connected to the third end of the first transistor VT1 and the output end of the second inverter U11 respectively, and the output end of the third AND gate U9 is connected to the first input end of the first OR gate U10; the input end of the second inverter U11 is connected to the first output end of the controller; The second input terminal of the first OR gate U10 is connected to the output terminal of the first AND gate U6 , and the output terminal of the first OR gate U10 is connected to the third terminal of the second transistor VT2 .

7. A post-spark busbar residual electricity recovery circuit according to claim 3, characterized in that: The residual power recycling control circuit includes a second voltage sampling and storage circuit, a third voltage sampling and tracking control circuit, and a fourth voltage sampling and tracking control circuit; The first input terminal of the second voltage sampling and storage circuit is connected to the second target connection terminal, and the output terminal of the second voltage sampling and storage circuit is connected to the first input terminal of the third voltage sampling and tracking control circuit and the first input terminal of the fourth voltage sampling and tracking control circuit respectively; The second input terminal of the third voltage sampling and tracking control circuit is connected to the first output terminal of the first voltage sampling and tracking control circuit, the third input terminal of the third voltage sampling and tracking control circuit is connected to the first output terminal of the controller, and the first output terminal of the third voltage sampling and tracking control circuit is connected to the first terminal of the second MOS transistor Q2; The second input terminal of the fourth voltage sampling and tracking control circuit is connected to the second output terminal of the third voltage sampling and tracking control circuit, the third input terminal of the fourth voltage sampling and tracking control circuit is connected to the second output terminal of the controller, and the output terminal of the fourth voltage sampling and tracking control circuit is connected to the second input terminal of the second voltage sampling and storage circuit; The second target connection end is a connection end between the second end of the second MOS transistor Q2 and the second end of the first diode D1 .

8. A post-spark busbar residual electricity recovery circuit according to claim 7, characterized in that: The second voltage sampling and storage circuit includes a second low-pass filter and a fifth operational amplifier U12; The second low-pass filter includes a twentieth resistor R20 and a fifth capacitor C5, wherein a first end of the twentieth resistor R203 is connected to the second target connection end, and a second end of the twentieth resistor R20 is connected to a first end of the fifth capacitor C5 and a non-inverting input end of the fifth operational amplifier U12, respectively; and a second end of the fifth capacitor C5 is grounded. The inverting input terminal of the fifth operational amplifier U12 is connected to the output terminal of the fifth operational amplifier U12, and the output terminal of the fifth operational amplifier U12 is connected to the first terminal of the twenty-first resistor R21 and the first input terminal of the fourth voltage sampling and tracking control circuit respectively; The second end of the twenty-first resistor R21 is respectively connected to the first end of the twenty-second resistor 22, the first end of the sixth capacitor C6 and the first input end of the third voltage sampling and tracking control circuit; The other end of the twenty-second resistor 22 is connected to the first end of the third transistor VT3, the second end of the third transistor VT3 is grounded, and the third end of the third transistor VT3 is connected to the output end of the fourth voltage sampling and tracking control circuit; the second end of the sixth capacitor C6 is grounded.

9. A post-spark busbar residual electricity recovery circuit according to claim 8, characterized in that: The third voltage sampling and tracking control circuit includes a sixth operational amplifier U13, a seventh operational amplifier U14 and a fourth AND gate U15; The non-inverting input terminal of the sixth operational amplifier U13 is connected to the second end of the twenty-first resistor R21, the inverting input terminal of the sixth operational amplifier U13 is connected to the output terminal of the sixth operational amplifier U13, and the output terminal of the sixth operational amplifier U13 is respectively connected to the first end of the twenty-fourth resistor R24 ​​and the second input terminal of the fourth voltage sampling and tracking control circuit; The non-inverting input terminal of the seventh operational amplifier U14 is connected to the second end of the twenty-fourth resistor R24 ​​and the first end of the seventh capacitor C7, respectively; the inverting input terminal of the seventh operational amplifier U14 is connected to the first end of the twenty-third resistor R23; the output terminal of the seventh operational amplifier U14 is connected to the first input terminal of the fourth AND gate U15; the second end of the seventh capacitor C7 is grounded; and the second end of the twenty-third resistor R23 is connected to the output terminal of the first operational amplifier U1. The second input terminal of the fourth AND gate U15 is connected to the first output terminal of the controller, and the output terminal of the fourth AND gate U15 is connected to the first input terminal of the controller.

10. A post-spark busbar residual electricity recovery circuit according to claim 9, characterized in that: The fourth voltage sampling and tracking control circuit includes a second comparator U17, a fifth AND gate U18 and a third inverter U19; The non-inverting input terminal of the second comparator U17 is connected to the first terminal of the fifteenth resistor R15; the inverting input terminal of the second comparator U17 is connected to the first terminal of the fourteenth resistor R14; the output terminal of the second comparator U17 is connected to the first terminal of the sixteenth resistor R16 and the first input terminal of the fifth AND gate U18 respectively; the second terminal of the fifteenth resistor R15 is connected to the output terminal of the sixth operational amplifier U13, and the second terminal of the fourteenth resistor R14 is connected to the output terminal of the fifth operational amplifier U12; the second terminal of the sixteenth resistor R16 is connected to the 5V voltage output terminal; The second input terminal of the fifth AND gate U18 is connected to the output terminal of the third inverter U19, and the output terminal of the fifth AND gate U18 is connected to the third terminal of the third transistor VT3; An input terminal of the third inverter U19 is connected to the first output terminal of the controller.

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