A low-barrett error, high linearity low noise wideband amplifier

Abstract

The application discloses a low-barret error, high-linearity and low-noise wideband amplifier, which comprises an input end, a common-source amplifier, a differential current balancer, an OTA, a load circuit and an enhanced source follower; an input signal enters from a P1 port, enters a first common-source amplifier, one-way signal enters the differential current balancer, and another way signal enters a second common-source amplifier and enters the differential current balancer; two-way signals are transmitted to P5 and P6 ports to output differential signals; the OTA detects the common-mode level of P5 and P6, feeds back the bias level of the load circuit to adjust g ds The application realizes high linearity by compensating the residual offset of the distortion components of the source follower and the main common-source amplifier, and reduces the barret error through a triple barret error correction technology. The application realizes the performance of low barret error, high linearity and low noise in the working frequency range of 0.2GHz to 6GHz.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency integrated circuits, in particular to a low-barrel error, high-linearity low-noise wideband amplifier. BACKGROUND

[0002] With the rapid development of 5G technology, wideband solutions are increasingly seen as both economical and efficient, providing high data transmission rates and saving hardware budgets. Compared with the bulky passive barrel transformer structure, the integrated barrel low noise amplifier (LNA) is favored for its compact structure and no insertion loss. However, the gain and phase error of the barrel low noise amplifier will adversely affect the IP2 of the subsequent mixer, ultimately reducing the signal-to-noise ratio of the receiver. On the other hand, improving the linearity performance is increasingly important for the spectral coexistence of multiple wireless protocols and multiple-input / multiple-output (MIMO) applications involving analog / digital beamforming. The concurrent use of these multiple protocols coexists, which will inevitably interfere with the wideband system of 5G communication. Therefore, it is of particular commercial value and technical significance to provide a low-barrel error, high-linearity low-noise amplifier for the 5G communication band.

[0003] Looking back, traditional barrel low noise amplifier technology mostly uses a common-source common-gate classic structure to achieve it. Chinese patent (CN104065346A) discloses a wideband low noise amplifier circuit based on cross-coupled feedback, including a CG input stage, a CS input stage and a resistance load stage. The CG input stage includes NMOS tube M2, the CS input stage includes NMOS tube M 1，4 ; the cross feedback of the CS input stage is used to improve the CG input stage and reduce power consumption. The current multiplexing technology of the CS input stage also saves power consumption. The amplifier can obtain a low noise index while maintaining low power consumption; but the asymmetric device size on the CG-CS two paths makes the delay experienced by the signal significantly different, resulting in a large phase error. Even if good amplitude error control can be obtained by adjusting the g m and R L of the devices on the CG-CS two paths, the overall barrel error still cannot reach the error range and level of the traditional passive transformer barrel; it is also noted that the linearity of the circuit in the above technology is poor and cannot meet the high linearity requirements of the current 5G communication wideband system.

[0004] As described above, the existing barrel low noise amplifier has poor linearity and high barrel error, which cannot meet the requirements of high linearity and low barrel error of today's 5G communication wideband system. Therefore, the present application provides a low-barrel error, high-linearity low-noise wideband amplifier with low-barrel error and high-linearity advantages. SUMMARY

[0005] The application discloses a low-barrett error, high linearity and low-noise wideband amplifier, which comprises an input end, a common source amplifier, a differential current balancer, an OTA, a load circuit and an enhanced source follower.

[0006] The input end comprises a resistor R s , a port P1, a capacitor C0, an inductor L0, a resistor R f and a capacitor C f .

[0007] The common source amplifier comprises a first common source amplifier and a second common source amplifier, and the first common source amplifier and the second common source amplifier have the same structure; the first common source amplifier is provided with ports A and B on both sides; the second common source amplifier is provided with ports C and M on both sides; and a node X is arranged in the middle of the first common source amplifier and the second common source amplifier.

[0008] The differential current balancer is provided with ports D and E and ports F and G on both sides; and a node Y is arranged between the port E of the differential current balancer and the port M of the second common source amplifier.

[0009] The OTA is provided with ports P2, P3 and P4 on both sides; the port P4 is connected with a port P5 and a port P6 respectively; R L，cm is arranged between the port P4 and the port P5, and R L，cm1 is arranged between the port P4 and the port P6; and a node Z is arranged between the port P6 and the port G of the differential current balancer.

[0010] The load circuit is provided with ports T and V on both sides.

[0011] The enhanced source follower is provided with ports H, J and K on both sides.

[0012] One end of the input end resistor R s receives an input signal V s , the other end of the input end resistor R f is connected with one end of a capacitor C0 and connected to the port P1; the other end of the capacitor C0 is grounded; one end of the input end resistor R f is connected with one end of a capacitor C f and connected to the port P1, and the other end of the capacitor C f is connected with the H end of the enhanced source follower; one end of the input end inductor L0 is connected with the port P1, and the other end of the input end inductor L0 is connected with the A end of the first common source amplifier.

[0013] The J end of the enhanced source follower is connected with the port P5 of the OTA, the K end of the enhanced source follower is connected with the node Z, and the node Z is connected with another output port P6.

[0014] The B end of the first common source amplifier is connected with node X, the C end of the second common source amplifier is connected with node X, and the M end of the second common source amplifier is connected with node Y.

[0015] The D end of the differential current balancer is connected with node X, the E end of the differential current balancer is connected with node Y, the F end of the differential current balancer is connected with output port P5, and the G end of the differential current balancer is connected with node Z.

[0016] One end of the resistor R L，cm is connected with port P5, and the other end is connected with port P4 of the OTA; one end of the resistor R L，cm1 is connected with port P6, and the other end is connected with port P4 of the OTA; port P3 of the OTA is connected with power voltage V ref , and port P2 is connected with the load circuit.

[0017] The T end of the load circuit is connected with output port P5, and the V end of the load circuit is connected with another output port P6.

[0018] The input signal V s comes from P1 port, is transmitted through port A into the first common source amplifier through the B port, is transmitted to the D port into the differential current balancer, is transmitted through port C into the second common source amplifier through the Y node to the E port into the differential current balancer, is transmitted through the F and G ports of the differential current balancer to P5 and P6 ports, is transmitted through P5 and P6 ports to P4 port into the OTA, is transmitted through P2 port into the load circuit, is transmitted through the T and V ports of the load circuit, and is output as V O signal through P5 and P6 ports; meanwhile, the output V O signal is transmitted through J and K ports into the enhanced source follower, is transmitted through the H port of the enhanced source follower, and reaches P1 port to form feedback.

[0019] Preferably, the common source amplifier comprises: NMOS tube M n1 , NMOS tube M n2 , PMOS tube M p1 , PMOS tube M p2 , capacitor C1, capacitor C2, resistor R1, and resistor R2.

[0020] One end of the capacitor C1 is connected with one end of the capacitor C2 and is connected to port A / C, the other end of the capacitor C1 is connected with one end of the resistor R1 and the gate end of the PMOS tube M p1～2 , the other end of the resistor R1 is connected with power voltage V b1 , and the PMOS tube M p1～2The source terminal is connected to a power supply voltage of 1.2V, and the PMOS transistor M... p1～2 Drain terminal and NMOS transistor M n1～2 The drain terminal is connected and connected to port B / M, the NMOS transistor M n1～2 The source terminal is grounded, and the other end of the capacitor C2 is connected to one end of the resistor R2 and the NMOS transistor M. n1～2 The gate terminals are connected, and the other end of the resistor R2 is connected to the power supply voltage V. b0 .

[0021] Preferably, the differential current balancer includes: NMOS transistor M3, NMOS transistor M4, capacitor C6, capacitor C7, resistor R6, and resistor R7;

[0022] One end of capacitor C6 is connected to the gate terminal of NMOS transistor M3 and one end of resistor R6, the other end of capacitor C6 is connected to the source terminal of NMOS transistor M4, and the other end of resistor R6 is connected to one end of resistor R7 and connected to the power supply voltage V. b2 The other end of the resistor R7 is connected to one end of the capacitor C7 and the gate of the NMOS transistor M4. The other end of the capacitor C7 is connected to the source of the NMOS transistor M3. The drain of the NMOS transistor M3 is connected to port F. The source of the NMOS transistor M3 is connected to port D. The drain of the NMOS transistor M4 is connected to port G. The source of the NMOS transistor M4 is connected to port E.

[0023] Preferably, the OTA includes: NMOS transistors M0, M1, M2, and M6, PMOS transistors M3, M4, and M5, and capacitor C. L，cm Capacitor C m Capacitor C z Capacitor C L Resistance R m Resistance R z ;

[0024] The capacitor C L，cm One end of the capacitor is connected to the gate terminal of the NMOS transistor M1 and then connected to port P4. L，cm The other end is grounded. The source of NMOS transistor M1 is connected to the drain of NMOS transistor M0 and the source of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the drain of PMOS transistor M3 and the gate of PMOS transistor M3. The source of PMOS transistor M3 is connected to a power supply voltage of 1.2V. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4. The source of PMOS transistor M4 is connected to a power supply voltage of 1.2V. The drain of PMOS transistor M4 is connected to the gate of PMOS transistor M5 and the drain of NMOS transistor M2. The gate of NMOS transistor M2 is connected to a power supply voltage of V. ref The gate terminal of the NMOS transistor M0 is connected to the power supply voltage V.b0，ota The source terminal of the NMOS transistor M0 is grounded, the source terminal of the PMOS transistor M5 is connected to a power supply voltage of 1.2V, and the resistor R... m One end of the resistor is connected to the gate terminal of the PMOS transistor M5, and the resistor R m The other end is connected to capacitor C m One end of the capacitor C is connected to the capacitor C. m The other end is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and the capacitor C L One end of the capacitor is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and then connected to port P2. L The other end of the capacitor C is grounded. z One end of the capacitor is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6. z The other end is connected to resistor R z One end of the resistor R is connected to the gate terminal of the NMOS transistor M6. z The other end is connected to the power supply voltage V. b1，ota The source terminal of the NMOS transistor M6 is grounded.

[0025] Preferably, the load circuit includes: PMOS transistor M7, PMOS transistor M8, resistor R5, and capacitor C. L，cmp Capacitor C R，cmp ;

[0026] The capacitor C L，cmp One end of the capacitor is connected to the source terminal of the PMOS transistor M7, and the source terminal of the PMOS transistor M7 is connected to a power supply voltage of 1.2V. L，cmp The other end of the resistor is connected to the drain of PMOS transistor M7 and to port T. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8 and to port P2. One end of the resistor R5 is connected to capacitor C. R，cmp One end of the resistor R5 is connected to the drain of the PMOS transistor M8, and the other end is connected to port V. The capacitor C R，cmp The other end is connected to the source terminal of PMOS transistor M8, which is connected to a power supply voltage of 1.2V.

[0027] Preferably, the enhanced source follower includes: NMOS transistor M5, NMOS transistor M7, capacitor C3, capacitor C4, resistor R3, and resistor R4;

[0028] One end of capacitor C3 is connected to port J and serves as one output port V. o+ The other end of capacitor C3 is connected to one end of resistor R3 and the gate terminal of NMOS transistor M5, and the other end of resistor R3 is connected to the power supply voltage V. b4The drain of NMOS transistor M5 is connected to a power supply voltage of 1.2V. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M7 and connected to port H. The source of NMOS transistor M7 is grounded. One end of capacitor C4 is connected to port K and serves as another output port V. o- The other end of capacitor C4 is connected to one end of resistor R4 and the gate terminal of NMOS transistor M7, and the other end of resistor R4 is connected to the power supply voltage V. b3 .

[0029] Compared with the prior art, the technical solution of this application has the following technical effects:

[0030] This invention uses a triple balun error correction technique to achieve low balun error by setting a reasonable differential current balancer M. 3～4 The dimensions are preset with a non-unity gain Vy / Vx ratio to mitigate the impact of output load resistance asymmetry on gain balance and reduce gain amplitude error. A current differential balancer is used to forward the Vy / Vx signal and further correct its amplitude and phase errors. An additional capacitor C is used at the circuit output load. L，cmp Capacitor C R，cmp Resistance R R，cmp The component compensates for the high-frequency phase error caused by the different parasitic delays of the X and Y paths.

[0031] This invention utilizes a source follower to implicitly eliminate the distortion component of the main transistor, effectively improving the linearity of the low-noise amplifier.

[0032] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0033] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0035] Figure 1 This is a diagram of the architecture of the present invention;

[0036] Figure 2 This is a schematic diagram of the first and second common-source amplifier circuits of the present invention;

[0037] Figure 3 This is a schematic diagram of the differential current balancer circuit of the present invention;

[0038] Figure 4 This is a schematic diagram of the OTA circuit of the present invention;

[0039] Figure 5 This is a schematic diagram of the load circuit of the present invention;

[0040] Figure 6 This is a schematic diagram of the enhanced source follower circuit of the present invention;

[0041] Figure 7 To enhance the source follower, V i Convert to I sf Equivalent circuit diagram;

[0042] Figure 8 This is a schematic diagram of the circuit used in this invention to analyze distortion sources;

[0043] Figure 9 The OTA of this invention generates an unbalanced noise voltage V. no+ / - Circuit diagram;

[0044] Figure 10 Z, the present invention L，cl Z R，cl Z L，ol Z R，ol Impedance diagram;

[0045] Figure 11 This is the gain error diagram of the present invention;

[0046] Figure 12 This is the phase error diagram of the present invention;

[0047] Figure 13 This is a simulated NF diagram of the CMFB under different capacitor configurations in this invention;

[0048] Figure 14 This is the third-order distortion diagram of the present invention;

[0049] Figure 15 The results of S11, gain, NF, and IIP3 of this invention are shown in the figure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0051] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0052] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0053] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" in this article describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it are in an "or" relationship.

[0054] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0055] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0056] Example 1

[0057] This embodiment mainly describes a broadband amplifier with low balun error, high linearity, and low noise, such as... Figure 1 As shown, it includes: input terminal, common source amplifier, differential current balancer, OTA, load circuit and enhancement source follower;

[0058] The input terminal includes a resistor R. s Port P1, capacitor C0, inductor L0, resistor R f and capacitor C f ;

[0059] The common-source amplifier includes a first common-source amplifier and a second common-source amplifier, which have the same structure. The first common-source amplifier has ports A and B on both sides; the second common-source amplifier has ports C and M on both sides; and a node X is set between the first and second common-source amplifiers.

[0060] Ports D and E and ports F and G are set on both sides of the differential current balancer; a node Y is set between port E of the differential current balancer and port M of the second common source amplifier.

[0061] Ports P2, P3, and P4 are configured on both sides of the OTA; port P4 is connected to ports P5 and P6 respectively; an R is configured between port P4 and port P5. L，cm R is set between port P4 and port P6 L，cm1 A node Z is set between port P6 and port G of the differential current balancer.

[0062] Ports T and V are set on both sides of the load circuit;

[0063] The enhanced source follower has ports H, J, and K on both sides;

[0064] Input resistor R s One end receives the input signal V s The other end is connected to one end of capacitor C0 and then to port P1; the other end of capacitor C0 is grounded; the input resistor R f One end is connected to capacitor C f One end is connected to port P1, and the other end is connected to capacitor C. f The other end is connected to the H terminal of the enhancement source follower; one end of the input inductor L0 is connected to port P1, and the other end is connected to the A terminal of the first common source amplifier.

[0065] The J terminal of the enhanced source follower is connected to port P5 of the OTA, the K terminal of the enhanced source follower is connected to node Z, and node Z is connected to another output port P6.

[0066] The B terminal of the first common-source amplifier is connected to node X, the C terminal of the second common-source amplifier is connected to node X, and the M terminal of the second common-source amplifier is connected to node Y.

[0067] The D terminal of the differential current balancer is connected to node X, the E terminal of the differential current balancer is connected to node Y, the F terminal of the differential current balancer is connected to the output port P5, and the G terminal of the differential current balancer is connected to node Z.

[0068] resistor R L，cm One end is connected to port P5, and the other end is connected to port P4 of the OTA; resistor R L，cm1 One end is connected to port P6, and the other end is connected to port P4 of the OTA; port P3 of the OTA is connected to the power supply voltage V. ref Port P2 is connected to the load circuit;

[0069] The T terminal of the load circuit is connected to the output port P5, and the V terminal of the load circuit is connected to another output port P6.

[0070] Input signal V s The signal enters from port P1, passes through port A to the first common-source amplifier, and is then transmitted through port B. One signal is transmitted to port D and enters the differential current balancer. The other signal enters the second common-source amplifier via port C, is transmitted through the Y node to port E and enters the differential current balancer, and is then transmitted through ports F and G of the differential current balancer to ports P5 and P6. From ports P5 and P6, the signal is transmitted to port P4 and enters the OTA circuit. Finally, the signal is transmitted through port P2 to the load circuit, and from the load circuit's T and V ports, it is output via ports P5 and P6. O Signal; simultaneously output V O The signal is transmitted through ports J and K into the enhancement source follower, and then through port H of the enhancement source follower to reach port P1 to form feedback.

[0071] Furthermore, such as Figure 2 As shown, the common-source amplifier includes: an NMOS transistor M n1 NMOS transistor M n2 PMOS transistor M p1 PMOS transistor M p2 Capacitor C1, Capacitor C2, Resistor R1, Resistor R2;

[0072] One end of capacitor C1 is connected to one end of capacitor C2 and then to port A / C. The other end of capacitor C1 is connected to one end of resistor R1 and PMOS transistor M. p1～2 The gate terminals are connected, and the other end of resistor R1 is connected to the power supply voltage V. b1 PMOS transistor M p1～2 The source is connected to a power supply voltage of 1.2V, and the PMOS transistor is M. p1～2Drain terminal and NMOS transistor M n1～2 The drain is connected and connected to port B / M, NMOS transistor M. n1～2 The source terminal is grounded, and the other end of capacitor C2 is connected to one end of resistor R2 and NMOS transistor M. n1～2 The gate terminals are connected, and the other end of resistor R2 is connected to the power supply voltage V. b0 .

[0073] Furthermore, such as Figure 3 As shown, the differential current balancer includes: NMOS transistor M3, NMOS transistor M4, capacitor C6, capacitor C7, resistor R6, and resistor R7.

[0074] One end of capacitor C6 is connected to the gate terminal of NMOS transistor M3 and one end of resistor R6. The other end of capacitor C6 is connected to the source terminal of NMOS transistor M4. The other end of resistor R6 is connected to one end of resistor R7 and connected to the power supply voltage V. b2 The other end of resistor R7 is connected to one end of capacitor C7 and the gate of NMOS transistor M4. The other end of capacitor C7 is connected to the source of NMOS transistor M3. The drain of NMOS transistor M3 is connected to port F. The source of NMOS transistor M3 is connected to port D. The drain of NMOS transistor M4 is connected to port G. The source of NMOS transistor M4 is connected to port E.

[0075] Furthermore, such as Figure 4 As shown, OTA includes: NMOS transistors M0, M1, M2, and M6, PMOS transistors M3, M4, and M5, and capacitor C. L，cm Capacitor C m Capacitor C z Capacitor C L Resistance R m Resistance R z ;

[0076] Capacitor C L，cm One end is connected to the gate terminal of NMOS transistor M1 and then to port P4, capacitor C L，cm The other end is grounded. The source of NMOS transistor M1 is connected to the drain of NMOS transistor M0 and the source of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the drain of PMOS transistor M3 and the gate of PMOS transistor M3. The source of PMOS transistor M3 is connected to a power supply voltage of 1.2V. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4. The source of PMOS transistor M4 is connected to a power supply voltage of 1.2V. The drain of PMOS transistor M4 is connected to the gate of PMOS transistor M5 and the drain of NMOS transistor M2. The gate of NMOS transistor M2 is connected to a power supply voltage of V. ref The gate terminal of the NMOS transistor M0 is connected to the power supply voltage V. b0，ota The source of NMOS transistor M0 is grounded, the source of PMOS transistor M5 is connected to a power supply voltage of 1.2V, and resistor R...m One end is connected to the gate terminal of PMOS transistor M5, and resistor R m The other end is connected to capacitor C m One end is connected to capacitor C m The other end is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and capacitor C L One end is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and then connected to port P2. Capacitor C L The other end is grounded, capacitor C z One end is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and capacitor C z The other end is connected to resistor R z One end is connected to the gate terminal of NMOS transistor M6, and resistor R z The other end is connected to the power supply voltage V. b1，ota The source terminal of NMOS transistor M6 is grounded.

[0077] Furthermore, such as Figure 5 As shown, the load circuit includes: PMOS transistor M7, PMOS transistor M8, resistor R5, and capacitor C. L，cmp Capacitor C R，cmp ;

[0078] Capacitor C L，cmp One end is connected to the source of PMOS transistor M7, and the source of PMOS transistor M7 is connected to a power supply voltage of 1.2V. Capacitor C L，cmp The other end is connected to the drain of PMOS transistor M7 and to port T. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8 and to port P2. One end of resistor R5 is connected to capacitor C. R，cmp One end of the resistor R5 is connected to the drain of the PMOS transistor M8, and the other end is connected to port V. Capacitor C... R，cmp The other end is connected to the source terminal of PMOS transistor M8, which is connected to a power supply voltage of 1.2V.

[0079] Furthermore, such as Figure 6 As shown, the enhancement-mode source follower includes: NMOS transistor M5, NMOS transistor M7, capacitor C3, capacitor C4, resistor R3, and resistor R4;

[0080] One end of capacitor C3 is connected to port J and serves as one output port V. o+ The other end of capacitor C3 is connected to one end of resistor R3 and the gate terminal of NMOS transistor M5, and the other end of resistor R3 is connected to the power supply voltage V. b4 The drain of NMOS transistor M5 is connected to a 1.2V power supply. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M7 and then connected to port H. The source of NMOS transistor M7 is grounded. One end of capacitor C4 is connected to port K and serves as another output port V.o- The other end of capacitor C4 is connected to one end of resistor R4 and the gate terminal of NMOS transistor M7, and the other end of resistor R4 is connected to the power supply voltage V. b3 .

[0081] This embodiment demonstrates that the CMOS integrated passive mixer has significant advantages in miniaturization and high integration, making it more ideal for broadband system applications in the new 5G communication FR3 band. CMOS technology has strong compatibility with digital circuits, which facilitates the implementation of logic control for multi-phase digital clocks, reduces manufacturing costs, and enhances market competitiveness. The ultra-wideband and ultra-high linearity performance advantages of the CMOS integrated passive mixer enable it to be adjusted according to different application requirements and adapt to various frequency communication requirements.

[0082] Example 2

[0083] This embodiment, based on Embodiment 1, describes in detail an optimized scheme for a broadband amplifier with low balun error, high linearity, and low noise, specifically including:

[0084] like Figure 1 As shown, in the circuit of this application, the asymmetry of the output impedance at both ends of the output terminal will disrupt the balance of the balun. By adding a feedback loop, the difference in output impedance at both ends can be significantly reduced. Specifically, as shown... Figure 10 The simulation results shown indicate that the impedance Z across the closed loop is at 1 GHz. L，cl and Z R，cl The impedances are 175Ω and 135Ω respectively, while the impedances Z at both ends of the open loop are... L，ol and Z R，ol The resistance Z of the output port is 238Ω and 166Ω respectively. L，cl and Z R，cl It became more balanced, mitigating gain error;

[0085] This invention designs a triple balun error correction to achieve low balun error, by setting a reasonable NMOS transistor M in the differential current balancer. 3～4 The dimensions are preset with a non-unity gain Vy / Vx ratio, such as... Figure 1 As shown, this mitigates the impact of unbalanced load resistance at the circuit output port on gain balance, thus reducing gain amplitude error; as Figure 3 As shown, a current differential balancer is used to cross-couple the Vy / Vx signals to further correct the amplitude and phase errors of Vy / Vx and propagate them towards the load. When the input signal passes through the first and second common-source amplifiers in sequence, two signal paths, X and Y, are generated. Due to the different parasitic capacitance distributions of the two paths, the phase delay of the signals obtained from the X and Y paths differs at high frequencies. To overcome this problem, an additional capacitor C is added at the output load of the circuit. L，cmp Capacitor CR，cmp Resistance R R，cmp The component is used to compensate for the high-frequency phase error caused by the different parasitic delays of the X and Y paths; as mentioned above, by presetting a certain proportion of V y / V x The triple correction of current balancer and high-frequency delay compensation ensures the overall output balance and achieves low balun error.

[0086] like Figure 11 The simulation results of the gain error are shown in the figure for the frequency range of 0.1-10GHz. It can be seen that the gain error is less than 0.5dB.

[0087] like Figure 12 Simulation results of phase error are given for frequencies ranging from 0.1 to 10 GHz, showing that the simulated phase error is less than 0.5 degrees.

[0088] The role of the source follower is to provide the low impedance required for matching the input port of the main amplifier after feedback. The following analysis shows that its nonlinearity can also be used to eliminate the distortion component of the main transistor. Previous studies have often ignored the source follower, which is referred to here as implicit distortion cancellation.

[0089] The equivalent principle diagram of the enhanced source follower of the present invention is shown below. Figure 7 As shown, it can be treated as an equivalent device to analyze the input voltage V. i Converted to output current i sf The relationship, specifically, the current i sf Voltage V i The relationship is: Among them G sf G are first-order linear coefficients. sf ′ are second-order linear coefficients, G sf "" represents the third-order linear coefficients. Simulations show that the second-order and third-order linear coefficients are negative in polarity, and the nonlinearity becomes more pronounced when driving small loads, such as... Figure 14 As shown.

[0090] Figure 8 A simplified circuit diagram for analyzing distortion sources is shown. The DCB, acting as a current buffer, does not produce additional distortion and can be ignored in the analysis. The resulting input-output relationship and third-order distortion term are shown in the following formulas:

[0091] V o =C1V s +C2V s 2 +C3V s 3 (1)

[0092]

[0093]

[0094] pass Figure 14 The simulation results show that G sf Since the '' value is negative, both terms in the numerator of C3 are negative, resulting in a cancellation effect. Note that the ESF's distortion cancellation term for the main transistor M1 has an amplitude ratio of approximately 2A for the three components. 3 v,se G sf " / A 3 v,se g″ ds / g″ m1 ESF distortion multiplied by the cube of the voltage gain means that only a small ESF is needed to cancel out the distortion, thereby minimizing additional parasitics. This can be achieved by adjusting the size of the ESF and the load resistance (R). f +R s To adjust the nonlinear coefficient G sf However, this will have a negative impact on input matching and NF.

[0095] In practice, ESF is preset to an overdistorted state, while as an additional degree of design freedom, the active load provides a compensating distortion component to compensate for the offset between ESF and M1. Load distortion is expressed through the output level V. ref The control is dynamically adjusted to adapt to gain changes at different frequencies and second-order interaction effects not shown in the equations. If the traditional method is used, the PMOS size change controlled by bit switches to adjust the load distortion will introduce additional parasitic effects, which is not conducive to the high linearity of the broadband. The PMOS transistor M7 uses an LVT device to save the load voltage margin. The load of this invention adopts an active PMOS load combined with a CMFB module, which can control the output DC level under a limited power supply voltage to obtain the best linearity.

[0096] like Figure 4 The diagram shown is a schematic representation of the circuit principle of the OTA of the present invention. Figure 9 The CM noise source V of the OTA is shown. n，OTA It appears at the differential output terminal, generating an unbalanced noise voltage V. no+ / - V no+ / - These two noise voltages are further combined into a single noise signal at the output of the enhancement-mode source follower, which then reaches the input CS stage. Correspondingly, differential feedback noise is generated in the X / Y paths, ultimately combining with the previous V... no+ / -The superposition of these components can alleviate the CM noise imbalance to some extent. A more effective way to solve this CM-DM noise conversion problem is to absorb CM noise in the CM path rather than leaking it into the DM path. To achieve the above goal, this technical solution adopts a two-stage OTA structure.

[0097] The first stage is designed for low noise, while the second stage, which drives a larger capacitive load, helps absorb KT / C noise. Meanwhile, the CM resistor R... L，cm The noise will also be amplified by the OTA and manifest as asymmetrical CM noise at the output; to counteract this effect, a capacitor C is added. L，cm To shorten the distance from CM to ground, Millor compensation is used to maintain gain stability, while C z / R z The zero-point contribution roughly compensates for the CM capacitor C L，cm and resistance R L，cm The extreme point.

[0098] like Figure 13 As shown, the simulated NF results for different capacitor configurations inside the CMFB are presented at frequencies from 0 to 10 GHz. It can be seen that after the noise conversion of the CM-DM is suppressed, the NF decreases by 0.67 dB, and the final NF performance is 2-3.6 dB.

[0099] This embodiment provides a low balun error, high linearity, and low-noise broadband amplifier implemented using 65nm process technology. Figure 1 In this circuit, Rf: 350Ω and Cf: 80fF combine to generate high-frequency poles, improving the matching bandwidth; L0: 0.55nH and C0: 180fF construct a π-type network, which also improves the matching bandwidth. The circuit ultimately consumes 14.8mW at a 1.2V power supply, and its operating frequency covers the 0.2-6GHz 5G communication band. Test results for the balun low-noise amplifier at the 0.2-6GHz frequency range show that S... 11 Less than -10dB, gain is 17-19.5dB, minimum NF is 2.8dB, and average IIP3 is greater than 2.5dBm.

[0100] Example 3

[0101] This embodiment, based on Embodiment 1, details a low-balun error, high-linearity, low-noise broadband amplifier. Figure 1 The overall topology implementation effect;

[0102] like Figure 10 As shown, Z is given for frequencies ranging from 0.1 to 10 GHz. L，cl Z R，cl Z L，ol Z R，olThe impedance simulation results show that at 1 GHz, Z L，cl Z R，cl Z L，ol Z R，ol The impedance values ​​are 175Ω, 135Ω, 238Ω, and 166Ω, respectively.

[0103] like Figure 11 As shown, the simulation results of gain error are given when the frequency is 0.1-10GHz. It can be seen that the final simulated gain error is less than 0.1dB. It can also be clearly seen that the triple error correction technology has a gradual correction effect on the balun error, and that Vy / Vx is preset to around 1.8dB, rather than the ideal unity gain.

[0104] like Figure 12 As shown, the simulation results of phase error are given for frequencies from 0.1 to 10 GHz. It can be seen that the final simulated phase error is much less than 0.5 degrees. It also shows the ability of triple error correction technology to gradually correct the phase error of the balun. Taking the 6 GHz frequency point as an example, the phase error reduction trend is: 35.6°->4.5°->0.1°.

[0105] like Figure 13 As shown, the simulated noise reduction factor (NF) for different capacitor configurations inside the CMFB is presented at frequencies from 0 to 10 GHz. It can be seen that after the noise conversion effect of CM-DM is suppressed, the NF decreases by 0.67 dB, and the final NF simulation results are 2-3.6 dB.

[0106] like Figure 14 As shown, the simulation results of third-order distortion are presented when the input voltage is between -0.3V and 0.3V. It can be seen that G sf "Negative;

[0107] like Figure 15 As shown, S is given for frequencies between 0-7 GHz. 11 Measurement and simulation results of Gain, NF, and IIP3. The measurement results show that S 11 Less than -10dB, Gain is 17-19.5dB, NF minimum is 2.8dB. When measuring IIP3, the tone interval is 10MHz, the amplitude is -40dBm, it fluctuates between -1.4-8.3dBm, the average value of the entire passband is greater than 2.5dBm, while the simulated level is only -5dBm when using a diode to short the PMOS load.

[0108] This embodiment demonstrates, through the aforementioned technical effects, that the IIP3 linearity of this technical solution has a significant advantage. Figure 15The balun error measurement results of this invention are given: gain error <0.5dB, phase error <1°. Such low balun error is comparable to the balun error level of any passive transformer. However, this solution avoids the drawbacks of passive baluns such as large size and insertion loss, making this technical solution of high scientific value and technological breakthrough significance.

[0109] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any changes, modifications, substitutions, integrations, and parameter changes made to these embodiments within the spirit and principles of the present invention, without departing from the principles and spirit of the present invention, through conventional substitutions or to achieve the same function, fall within the scope of protection of the present invention.

Claims

1. A broadband amplifier with low balun error, high linearity, and low noise, characterized in that, include: Input terminal, common-source amplifier, differential current balancer, OTA, load circuit and enhancement-mode source follower; The input terminal includes a resistor R. s Port P1, capacitor C0, inductor L0, resistor R f and capacitor C f ; The common-source amplifier includes a first common-source amplifier and a second common-source amplifier, which have the same structure. Ports A and B are provided on both sides of the first common-source amplifier. Ports C and M are provided on both sides of the second common-source amplifier. Node X is provided between the first common-source amplifier and the second common-source amplifier. The differential current balancer has ports D and E on both sides and ports F and G on both sides; a node Y is set between port E of the differential current balancer and port M of the second common source amplifier. The OTA is equipped with ports P2, P3, and P4 on both sides; port P4 is connected to ports P5 and P6 respectively; an R is provided between port P4 and port P5. L，cm An R is set between port P4 and port P6. L，cm1 A node Z is set between port P6 and port G of the differential current balancer. Ports T and V are provided on both sides of the load circuit; The enhanced source follower has ports H, J, and K on both sides; Input resistor R s One end receives the input signal V s The other end is connected to one end of capacitor C0 and then to port P1; the other end of capacitor C0 is grounded; the input resistor R f One end is connected to capacitor C f One end is connected to port P1, and the other end is connected to capacitor C. f The other end is connected to the H terminal of the enhancement source follower; one end of the input inductor L0 is connected to port P1, and the other end is connected to the A terminal of the first common source amplifier; The J terminal of the enhanced source follower is connected to port P5 of the OTA, the K terminal of the enhanced source follower is connected to node Z, and node Z is connected to another output port P6. The B terminal of the first common-source amplifier is connected to node X, the C terminal of the second common-source amplifier is connected to node X, and the M terminal of the second common-source amplifier is connected to node Y. The D terminal of the differential current balancer is connected to node X, the E terminal of the differential current balancer is connected to node Y, the F terminal of the differential current balancer is connected to output port P5, and the G terminal of the differential current balancer is connected to node Z. The resistor R L，cm One end of the resistor is connected to port P5, and the other end is connected to port P4 of the OTA; the resistor R L，cm1 One end is connected to port P6, and the other end is connected to port P4 of the OTA; the OTA port P3 is connected to the power supply voltage V. ref The port P2 is connected to the load circuit; The T terminal of the load circuit is connected to the output port P5, and the V terminal of the load circuit is connected to another output port P6. The input signal V s The signal enters from port P1, passes through port A to the first common-source amplifier, and is then transmitted through port B. One signal is transmitted to port D and enters the differential current balancer. The other signal enters the second common-source amplifier via port C, is transmitted through the Y node to port E and enters the differential current balancer, and is then transmitted through ports F and G of the differential current balancer to ports P5 and P6. From ports P5 and P6, the signal is transmitted to port P4 and enters the OTA circuit. Finally, the signal is transmitted through port P2 to the load circuit, and from the load circuit's T and V ports, it is output via ports P5 and P6. O Signal; simultaneously output V O The signal is transmitted through ports J and K into the enhancement source follower, and then through port H of the enhancement source follower to reach port P1 to form feedback.

2. The low balun error, high linearity, and low noise broadband amplifier according to claim 1, characterized in that, The common-source amplifier includes: an NMOS transistor M n1 NMOS transistor M n2 PMOS transistor M p1 PMOS transistor M p2 Capacitor C1, Capacitor C2, Resistor R1, Resistor R2; One end of capacitor C1 is connected to one end of capacitor C2 and then connected to port A / C. The other end of capacitor C1 is connected to one end of resistor R1 and PMOS transistor M. p1～2 The gate terminals are connected, and the other end of the resistor R1 is connected to the power supply voltage V. b1 The PMOS transistor M p1～2 The source terminal is connected to a power supply voltage of 1.2V, and the PMOS transistor M... p1～2 Drain terminal and NMOS transistor M n1～2 The drain terminal is connected and connected to port B / M, the NMOS transistor M n1～2 The source terminal is grounded, and the other end of the capacitor C2 is connected to one end of the resistor R2 and the NMOS transistor M. n1～2 The gate terminals are connected, and the other end of the resistor R2 is connected to the power supply voltage V. b0 .

3. The low balun error, high linearity, and low noise broadband amplifier according to claim 1, characterized in that, The differential current balancer includes: NMOS transistor M3, NMOS transistor M4, capacitor C6, capacitor C7, resistor R6, and resistor R7. One end of capacitor C6 is connected to the gate terminal of NMOS transistor M3 and one end of resistor R6, the other end of capacitor C6 is connected to the source terminal of NMOS transistor M4, and the other end of resistor R6 is connected to one end of resistor R7 and connected to the power supply voltage V. b2 The other end of the resistor R7 is connected to one end of the capacitor C7 and the gate of the NMOS transistor M4. The other end of the capacitor C7 is connected to the source of the NMOS transistor M3. The drain of the NMOS transistor M3 is connected to port F. The source of the NMOS transistor M3 is connected to port D. The drain of the NMOS transistor M4 is connected to port G. The source of the NMOS transistor M4 is connected to port E.

4. The low balun error, high linearity, and low noise broadband amplifier according to claim 1, characterized in that, The OTA includes: NMOS transistors M0, M1, M2, and M6, PMOS transistors M3, M4, and M5, and capacitor C. L，cm Capacitor C m Capacitor C z Capacitor C L Resistance R m Resistance R z ; The capacitor C L，cm One end of the capacitor is connected to the gate terminal of the NMOS transistor M1 and then connected to port P4. L，cm The other end is grounded. The source of NMOS transistor M1 is connected to the drain of NMOS transistor M0 and the source of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the drain of PMOS transistor M3 and the gate of PMOS transistor M3. The source of PMOS transistor M3 is connected to a power supply voltage of 1.2V. The gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4. The source of PMOS transistor M4 is connected to a power supply voltage of 1.2V. The drain of PMOS transistor M4 is connected to the gate of PMOS transistor M5 and the drain of NMOS transistor M2. The gate of NMOS transistor M2 is connected to a power supply voltage of V. ref The gate terminal of the NMOS transistor M0 is connected to the power supply voltage V. b0，ota The source terminal of the NMOS transistor M0 is grounded, the source terminal of the PMOS transistor M5 is connected to a power supply voltage of 1.2V, and the resistor R... m One end of the resistor is connected to the gate terminal of the PMOS transistor M5, and the resistor R m The other end is connected to capacitor C m One end of the capacitor C is connected to the capacitor C. m The other end is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and the capacitor C L One end of the capacitor is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6, and then connected to port P2. L The other end of the capacitor C is grounded. z One end of the capacitor is connected to the drain of PMOS transistor M5 and the drain of NMOS transistor M6. z The other end is connected to resistor R z One end of the resistor R is connected to the gate terminal of the NMOS transistor M6. z The other end is connected to the power supply voltage V. b1，ota The source terminal of the NMOS transistor M6 is grounded.

5. A low balun error, high linearity, low noise broadband amplifier according to claim 1, characterized in that, The load circuit includes: PMOS transistor M7, PMOS transistor M8, resistor R5, and capacitor C. L，cmp Capacitor C R，cmp ; The capacitor C L，cmp One end of the capacitor is connected to the source terminal of the PMOS transistor M7, and the source terminal of the PMOS transistor M7 is connected to a power supply voltage of 1.2V. L，cmp The other end of the resistor is connected to the drain of PMOS transistor M7 and to port T. The gate of PMOS transistor M7 is connected to the gate of PMOS transistor M8 and to port P2. One end of the resistor R5 is connected to capacitor C. R，cmp One end of the resistor R5 is connected to the drain of the PMOS transistor M8, and the other end is connected to port V. The capacitor C R，cmp The other end is connected to the source terminal of PMOS transistor M8, which is connected to a power supply voltage of 1.2V.

6. The low balun error, high linearity, and low noise broadband amplifier according to claim 1, characterized in that, The enhanced source follower includes: NMOS transistor M5, NMOS transistor M7, capacitor C3, capacitor C4, resistor R3, and resistor R4; One end of capacitor C3 is connected to port J and serves as one output port V. o+ The other end of capacitor C3 is connected to one end of resistor R3 and the gate terminal of NMOS transistor M5, and the other end of resistor R3 is connected to the power supply voltage V. b4 The drain of NMOS transistor M5 is connected to a power supply voltage of 1.2V. The source of NMOS transistor M5 is connected to the drain of NMOS transistor M7 and connected to port H. The source of NMOS transistor M7 is grounded. One end of capacitor C4 is connected to port K and serves as another output port V. o- The other end of capacitor C4 is connected to one end of resistor R4 and the gate terminal of NMOS transistor M7, and the other end of resistor R4 is connected to the power supply voltage V. b3 .

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