FlexE-based rate conversion method and device

Abstract

The invention discloses a FlexE-based rate conversion method and device. The FlexE-based rate conversion method comprises the following steps: firstly, acquiring a downstream back pressure signal and a preset output time slot number; determining an output permission according to the number of the input time slots and the number range of the output time slots; then, refreshing the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the number of preset output time slots; reading time slot data and outputting time slot data with corresponding bit width according to output permission, downstream back pressure signals, the number of input time slots, the number of to-be-output time slots, the number of maximum output time slots and the number of preset output time slots, thereby realizing a variable speed function of any rate and improving the flexibility of customer bandwidth selection; meanwhile, due to the fact that the two-stage assembly mode is adopted for the output time slot data, complex design codes can be avoided, and time sequence pressure can be obviously reduced when FPGA implementation is adopted.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular to a rate conversion method and device based on FlexE. Background Art

[0002] With the continuous improvement of Ethernet port bandwidth, the Optical Internet Forum released the FlexE protocol (FlexEthernet) in 2016. For physical interfaces with a rate greater than or equal to 50G, they can be used individually or in bundles, and then the total bandwidth can be allocated to one or more customers. The ports on which each customer's data is transmitted are configurable, and the transmission bandwidth can also be adjusted according to actual needs, and is no longer limited to the fixed port rate defined by the IEEE802.3 protocol. To achieve the above-mentioned bandwidth flexibility, the time slot data conversion must be flexible, that is, converting the fixed rate of the customer MAC into a variable rate corresponding to different time slot numbers.

[0003] Taking into account that excessive flexibility will increase the difficulty of implementation and is not conducive to the occupation of hardware resources, the Optical Internet Forum defines customer optional rates as 10Gb / s, 40 Gb / s and N*25Gb / s. That is, in addition to 10Gb / s and 40 Gb / s, the granularity of its customer rate is 25Gb / s, which is larger than the defined time slot granularity of 5Gb / s. With the expansion of business scenarios and the advancement of electronic technology, it is entirely possible that subsequent protocol versions will adjust the customer's optional rate to N*5Gb / s to keep it consistent with the time slot granularity. When the granularity is 25Gb / s, due to the large granularity, there are not many optional customer rates. Only 6 can be enumerated on a 100G port, namely 10Gb / s, 40 Gb / s, 25 Gb / s, 50 Gb / s, 75 Gb / s, and 100 Gb / s. Even if another 100G port is added, only 4 rates will be added. At present, cases can be written for all enumerated target rates, and the corresponding case is selected for execution when switching rates. However, if the granularity is reduced to 5Gb / s, there will be 20 rates on only one 100G port. Adding another 100G port requires another 20 rates. If the enumeration method is still used, the large increase in cases will lead to lengthy code in the development stage, and it will not be easy to expand later, and resource usage will also increase. If FPGA is used for implementation, it will also increase timing pressure. The enumeration method is obviously not suitable for this application scenario. Summary of the invention

[0004] The purpose of the present invention is to design a rate conversion method based on FlexE in order to solve the above problems.

[0005] The present invention achieves the above-mentioned purpose through the following technical solutions: The rate conversion method based on FlexE includes the following steps: Obtain downstream back pressure signal and preset output time slot number; determining output permission based on the number of input time slots and the maximum number of output time slots; Refresh the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots; The time slot data is read in and the time slot data of the corresponding bit width is output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots.

[0006] In one embodiment, the step of reading the time slot data according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots is specifically: When the number of time slots to be output is less than the preset number of output time slots, the sum of the number of time slots to be output and the number of input time slots is greater than the maximum number of output time slots, the output permission is valid and the downstream back pressure signal is not detected, determine to read in the time slot data; Or, when the number of time slots to be output is less than the preset number of output time slots and the sum of the number of time slots to be output and the number of input time slots is less than or equal to the maximum number of output time slots, it is determined to read in the time slot data.

[0007] In one embodiment, the output time slot data is assembled using two levels of cache.

[0008] In one embodiment, the step of outputting time slot data of corresponding bit width according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots is specifically: When the output permission is valid and the downstream back pressure signal is not detected, comparing the number of time slots to be output and the preset number of time slots to be output; When the number of time slots to be output is greater than or equal to the preset number of output time slots, generating first-level data assembly control information to determine output time slot data; Or, when the number of time slots to be output is less than the preset number of output time slots and the sum of the number of time slots to be output and the number of input time slots is greater than or equal to the preset number of output time slots, primary and secondary data assembly control information is generated to determine the output time slot data.

[0009] In one embodiment, the step of refreshing the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots is specifically: When the output permission is valid and the downstream back pressure signal is not detected, if remainder ≥ do_num, the number of time slots to be output is updated to remainder-do_num; if (remainder+a) ≥ do_num, the number of time slots to be output is updated to remainder+a-do_num; otherwise, the number of time slots to be output is updated to remainder+a; When the output permission is invalid or the downstream back pressure signal is detected, if remainder<do_num and remainder+a≤b, the number of time slots to be output is updated to remainder+a; otherwise, the number of time slots to be output remains unchanged; Among them, remainder is the number of time slots to be output, do_num is the preset number of output time slots, a is the number of input time slots, and b is the maximum number of output time slots.

[0010] The present invention further proposes a rate conversion device based on FlexE, which is used to implement the above-mentioned rate conversion method based on FlexE. The rate conversion device based on FlexE includes: A speed control unit, the speed control unit being used to output a corresponding speed control signal according to the number of input time slots, the number of time slots to be output, the preset number of output time slots and the downstream back pressure signal; The speed change execution unit is used to receive the speed change control signal output by the speed change control unit, and read the time slot data and output the time slot data of the corresponding bit width according to the speed change control signal. The beneficial effects of the present invention are: The rate conversion method based on FlexE first obtains the downstream back pressure signal and the preset number of output time slots; then determines the output permission based on the number of input time slots and the maximum number of output time slots; then, refreshes the number of time slots to be output based on the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots; then, reads the time slot data and outputs the time slot data of the corresponding bit width based on the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots, thereby realizing the speed change function of any rate and improving the flexibility of customer bandwidth selection. At the same time, due to the two-level assembly method for the output time slot data, the lengthy design code can be avoided, and the timing pressure can be significantly reduced when FPGA is used for implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flow chart of the rate conversion method based on FlexE of the present invention; Figure 2A schematic diagram of the relationship between FlexE and the IEEE Ethernet model in the FlexE-based rate conversion method of the present invention; Figure 3 It is a schematic diagram of the structure of the first-level data cache array of the rate conversion method based on FlexE of the present invention; Figure 4 A schematic diagram of assembling output data based on the second-level data cache of the rate conversion method based on FlexE of the present invention; Figure 5 It is a structural schematic diagram of a rate conversion device based on FlexE of the present invention. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0015] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0016] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0017] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0018] FlexE (Flex Ethernet) is a technology based on high-speed Ethernet interfaces, such as Figure 2 As shown in the figure, the implementation method is to embed the Shim layer in the PCS layer (Physical Coding Sublayer) and realize flexible configuration of customer bandwidth by globally scheduling the 66b code block. Since the Shim layer schedules the 66b code block, it is embedded next to the 64b / 66b codec module and the 64b / 66b codec module is moved to the MAC side. The 66b code block is a data unit with a bit width of 66 bits. It is the result of encoding 64-bit data and 8-bit control signals on the xMII interface. It exists in Ethernet interfaces with a rate of 5G and above.

[0019] FlexE uses the concept of time slots to schedule 66b code blocks. Taking a 100G FlexE instance as an example, it is divided into 20 5G time slots, numbered 0 to 19 in the instance. Each of the 20 consecutive 66b code blocks occupies one time slot. If the FlexE group contains two 100G physical ports or one 200G physical port, it can carry two 100G FlexE instances, so the number of time slots is 20*2=40.

[0020] Taking the 100G FlexE group as an example, the number of time slots is 20, numbered 0~19. If a customer occupies 2 time slots (can be any 2 time slots from 0~19), then the available bandwidth is 5G*2=10G. The subsequent bandwidth is insufficient, and the customer applies to increase it to 35G, so 7 time slots are allocated to the customer. However, the bandwidth supported by the customer MAC is usually very large, so as to ensure that the customer bandwidth can be adjusted within a larger range; still taking the 100G FlexE group as an example, the processing capacity of the customer MAC is 100Gb / s, which can occupy 20 time slots, but because the customer may actually only need 35G bandwidth, the Shim layer allocates 7 time slots to it, so it is necessary to convert 20 time slots into 7 time slots, which requires speed change processing. Based on this scenario where the rate needs to be dynamically converted, this application proposes a rate conversion method based on FlexE.

[0021] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0022] like Figure 1-5 As shown, the rate conversion method based on FlexE includes the following steps: Obtain downstream back pressure signal and preset output time slot number; determining output permission based on the number of input time slots and the maximum number of output time slots; Refresh the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots; The time slot data is read in and the time slot data of the corresponding bit width is output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots.

[0023] In one embodiment, the step of reading the time slot data according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots is specifically: When the number of time slots to be output is less than the preset number of output time slots, the sum of the number of time slots to be output and the number of input time slots is greater than the maximum number of output time slots, the output permission is valid and the downstream back pressure signal is not detected, determine to read in the time slot data; Or, when the number of time slots to be output is less than the preset number of output time slots and the sum of the number of time slots to be output and the number of input time slots is less than or equal to the maximum number of output time slots, it is determined to read in the time slot data.

[0024] In one embodiment, the output time slot data is assembled using two levels of cache.

[0025] In one embodiment, the step of outputting time slot data of corresponding bit width according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots is specifically: When the output permission is valid and the downstream back pressure signal is not detected, comparing the number of time slots to be output and the preset number of time slots to be output; When the number of time slots to be output is greater than or equal to the preset number of output time slots, generating first-level data assembly control information to determine output time slot data; Or, when the number of time slots to be output is less than the preset number of output time slots and the sum of the number of time slots to be output and the number of input time slots is greater than or equal to the preset number of output time slots, primary and secondary data assembly control information is generated to determine the output time slot data.

[0026] In one embodiment, the step of refreshing the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots is specifically: When the output permission is valid and the downstream back pressure signal is not detected, if remainder ≥ do_num, the number of time slots to be output is updated to remainder-do_num; if (remainder+a) ≥ do_num, the number of time slots to be output is updated to remainder+a-do_num; otherwise, the number of time slots to be output is updated to remainder+a; When the output permission is invalid or the downstream back pressure signal is detected, if remainder<do_num and remainder+a≤b, the number of time slots to be output is updated to remainder+a; otherwise, the number of time slots to be output remains unchanged; Among them, remainder is the number of time slots to be output, do_num is the preset number of output time slots, a is the number of input time slots, and b is the maximum number of output time slots.

[0027] In this embodiment, the rate conversion method based on FlexE includes the following steps: Step 1: Determine the output permission according to the number of input time slots and the maximum number of output time slots. The output permission is do_permit (data output permit). Data can be output only when the output permission is valid. The number of input time slots is recorded as a, and the maximum number of output time slots is recorded as b. The relationship between the two is b=a*n, where n is a positive integer. Taking the 100GFlexE group as an example, its total number of time slots is 20. Since the maximum number of output time slots output in one clock cycle does not exceed the total number of time slots, b is 20. Since 20*66bit=1320bit, the bit width is large. When designing digital circuits, using a large bit width will consume more hardware resources, so it is generally only used locally. For example, the maximum output of 20 time slots here is locally used. After being processed by the downstream module, it is generally compressed and output. The number of input time slots a at the transmission entrance is generally compressed, and is usually consistent with the number of output time slots of the downstream module. Compressing the data bit width means increasing the processing clock frequency. Different chips can support different maximum clock frequencies, depending on the situation. If a is selected as 10, then n is 2. The output permission do_permit is determined by the n value. Data is allowed to be output once every n clock cycles, which can ensure that the output rate matches the input rate. The use of output permission makes it easier for downstream modules to directly compress the number of output time slots to restore the number of input time slots a, avoiding the use of FIFO (First In First Out) cache and occupying RAM (Random Access Memory) resources.

[0028] Step 2: While determining the bit width of the first-level cache register, mark the time slot position number of the cache register. The first-level cache register is marked as l1_buffer; the first-level data cache is an array structure, containing n rows, each row can store a time slot data, so its bit width is a*66bit. Every time a time slot data is input, all the data in the array moves back one row, that is, the input data is stored in the first row, and the original data in the first row is transferred to the second row, and so on. When there is no data input, the data in the array remains unchanged. In addition, the time slot storage space in the array needs to be numbered, such as Figure 3 As shown, the first row is from 0 to (a-1), the second row is from a to (2a-1), and so on.

[0029] Step 3: Determine the relationship between the current remaining number of output time slots to be output and the preset number of output time slots, and determine whether data needs to be read in according to the output permission do_permit and the downstream backpressure situation; the current remaining number of output time slots to be output is denoted as remainder, the preset number of output time slots is denoted as do_num, and the downstream backpressure signal is denoted as do_ready. It can be understood that when remainder is less than do_num, data reading is started, which is a necessary condition; in addition, it is also necessary to determine whether (remainder + a) is greater than b, because the first-level buffer can only store b time slot data, and there are remainder time slot data to be output that have not been output. If a time slot data is read in but the output permission do_permit is invalid or the downstream backpressure causes the data not to be output, then the first-level buffer will overflow and data will be lost. Therefore, one beat of data can be read in only when (remainder + a) > b, do_permit is valid, and there is no downstream backpressure signal; if (remainder + a) < b, then one beat of data is directly read in.

[0030] Step 4: Determine the relationship between the current remaining number of time slots to be output and the preset number of output time slots, and determine whether to output data according to the output permission do_permit and the downstream back pressure signal do_ready; wherein the output permission do_permit is valid and the downstream back pressure signal do_ready is valid as necessary conditions for outputting data; based on the necessary conditions, when remainder is greater than or equal to do_num, the data in the first-level cache is directly used for output, and three control signals are generated, namely, the first-level output enable s1do_enable, the first-level output cache time slot position s1do_buff_loc and the first-level output time slot number s1do_length, wherein s1do_buff_loc is the time slot position number in the first-level cache array, and when s1do_enable is valid, its value is (r emainder-1), and the value of s1do_length directly takes do_num; if remainder is less than do_num, but (remainder+a) is greater than or equal to do_num, then another control signal is generated, that is, the secondary output enable s2do_enable. At this time, it is also necessary to consider whether remainder is 0. If it is 0, s1do_enable needs to be set to invalid. If remainder is not 0, s1do_enable is still valid, s1do_buff_loc is still (remainder-1), and the value of s1do_length takes remainder; in addition, when lossless speed change, the downstream module needs to use the effective bit width of the output data, so do_num needs to be output synchronously with other output control signals. It should be noted that the "generation" of the output control signal in this embodiment refers to validity.

[0031] Step 5: Refresh the remaining number of time slots to be output, remainder. Since the reading and output of time slot data can be performed simultaneously, remainder will be controlled by the reading and output of time slot data. One type is the scenario that satisfies the output data, that is, the remainder refresh when do_permit and do_ready are both valid: first, if remainder ≥ do_num, the direct output condition is met, then remainder is refreshed to (remainder-do_num); secondly, if (remainder+a) ≥ do_num, then remainder is refreshed to (remainder+a-do_num); finally, if neither of the above two conditions is met, then remainder is refreshed to (remainder+a), because the remaining number of time slots must be supplemented in time when it is insufficient for output, otherwise it may cause interruption. The other is the scenario where the output data is not satisfied, that is, the remainder is refreshed when at least one of do_permit and do_ready is invalid: first, remainder<do_num must be satisfied, and secondly, (remainder+a)≤b must be satisfied, that is, to ensure that the first-level cache array does not overflow. Only when both conditions are met can the remainder be refreshed to (remainder+a).

[0032] Step 6: The first step of the two-step assembly of the output time slot data in this embodiment is to update the second-level cache register according to the first-level output control signal. Specifically, the second-level cache register is marked as l2_buffer. l2_buffer needs to store b time slot data, so its bit width is the same as l1_buffer, which is also b*66bit, but it is no longer defined as an array here. When s1do_enable is valid, all the time slot data on the numbers 0~s1do_buff_loc in l1_buffer are stored in l2_buffer, and the storage needs to be aligned to the highest bit of l2_buffer. Since only part of the data in l1_buffer may be stored in l2_buffer, it is necessary to store the part that does not store l1_buffer data in Ethernet idle time slots to avoid outputting time slots with incorrect formats when the customer time slot changes. If s1do_enable is invalid, l2_buffer remains unchanged. It should be noted that only the s1do_length time slots adjacent to the s1do_buff_loc number from 0 to s1do_buff_loc are data that need to be output, so not all data stored in l2_buffer need to be output, and the part that does not need to be output may be replaced. Even if it is not replaced, the downstream module will only process valid data according to do_num, so the excess data does not constitute an impact.

[0033] Step 7: The second step of the two-step assembly output time slot data in this embodiment is to output the client data and the effective data bit width according to the primary and secondary output control signals. Specifically, Figure 4 As shown in the figure, when s2do_enable is valid, the customer data is assembled and output according to s1do_length, otherwise the data in l2_buffer is directly output as customer data. When assembly is required, the operation mode is to replace part of the data in l2_buffer with the latest read data and then output it as customer data. If s1do_length is 0, the first a time slot data of l2_buffer are replaced with the read data and then output as customer data. If s1do_length is 1, the highest-order time slot data is not replaced, and the subsequent a time slot data are replaced. And so on. If s1do_length is large and the number of time slots to be replaced is less than a, the latest read-in data high-order time slot data is used as replacement data. Since the output data is delayed by two clock cycles relative to s1do_enable and s2do_enable, the do_num passed to the downstream module also needs to be delayed by two clock cycles to ensure that the data intercepted by the downstream module is correct when lossless speed change is required. It should be noted that this step is performed in the next clock cycle of the first step of assembling the output time slot data in two steps, so the s2do_enable and s1do_length used are not the original signals, but are delayed by one beat relative to the first step of assembling the output time slot data in two steps; in addition, the read-in data also needs to be delayed by one clock cycle accordingly, and the time slot data of the first row in l1_buffer is actually used to replace the l2_buffer assembled output customer data.

[0034] The rate conversion method based on FlexE of the present invention first obtains the downstream back pressure signal and the preset number of output time slots; then determines the output permission according to the number of input time slots and the maximum number of output time slots; then, refreshes the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots; then, reads the time slot data and outputs the time slot data of the corresponding bit width according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots, thereby realizing the speed change function of any rate and improving the flexibility of customer bandwidth selection. At the same time, due to the two-level assembly method for the output time slot data, the lengthy design code can be avoided, and the timing pressure can be significantly reduced when FPGA is used for implementation.

[0035] The present invention also proposes a FlexE-based rate conversion device, which is used to implement the above-mentioned FlexE-based rate conversion method; the specific steps of the FlexE-based rate conversion method refer to the above-mentioned embodiments. Since the FlexE-based rate conversion device adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which are not repeated here one by one.

[0036] In one embodiment, the FlexE-based rate conversion device includes: A speed control unit, the speed control unit being used to output a corresponding speed control signal according to the number of input time slots, the number of time slots to be output, the preset number of output time slots and the downstream back pressure signal; The speed change execution unit is used to receive the speed change control signal output by the speed change control unit, and read the time slot data and output the time slot data of the corresponding bit width according to the speed change control signal.

[0037] In this embodiment, the rate conversion device based on FlexE can be implemented by a transmission, which includes a speed change control unit and a speed change execution unit. The speed change control unit outputs a corresponding speed change control signal according to the number of input time slots and the number of time slots to be output, the preset number of output time slots and the downstream back pressure signal, wherein the speed change control signal includes an input control signal and an output control signal. Specifically, the speed change execution unit reads the time slot data from the upstream module according to the input control signal, and outputs the time slot data of the corresponding bit width to the downstream module according to the output control signal, thereby realizing arbitrary rate speed change to improve the flexibility of customer bandwidth selection; wherein, the maximum number of output time slots can be switched arbitrarily between 1 and the maximum number of output time slots, and the transmission can respond dynamically, and then output the time slot data according to the new number of time slots to be output.

[0038] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A rate conversion method based on FlexE, characterized in that: The FlexE-based rate conversion method includes the following steps: Obtain downstream back pressure signal and preset output time slot number; determining output permission based on the number of input time slots and the maximum number of output time slots; Refresh the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots; The time slot data is read in and the time slot data of the corresponding bit width is output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots.

2. The rate conversion method based on FlexE according to claim 1, characterized in that: The step of reading the time slot data according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output, the maximum number of output time slots and the preset number of output time slots is specifically: When the number of time slots to be output is less than the preset number of time slots to be output, the sum of the number of time slots to be output and the number of input time slots is greater than the maximum number of time slots to be output, the output permission is valid and the downstream back pressure signal is not detected, determining to read in the time slot data; Or, when the number of time slots to be output is less than the preset number of output time slots and the sum of the number of time slots to be output and the number of input time slots is less than or equal to the maximum number of output time slots, it is determined to read in the time slot data.

3. The rate conversion method based on FlexE according to claim 1, characterized in that: The output time slot data is assembled using two-level cache.

4. The rate conversion method based on FlexE according to claim 3, characterized in that: The step of outputting time slot data of corresponding bit width according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots is specifically: When the output permission is valid and the downstream back pressure signal is not detected, comparing the number of time slots to be output and the preset number of time slots to be output; When the number of time slots to be output is greater than or equal to the preset number of output time slots, generating first-level data assembly control information to determine output time slot data; Or, when the number of time slots to be output is less than the preset number of output time slots and the sum of the number of time slots to be output and the number of input time slots is greater than or equal to the preset number of output time slots, primary and secondary data assembly control information is generated to determine the output time slot data.

5. The rate conversion method based on FlexE according to claim 1, characterized in that: The step of refreshing the number of time slots to be output according to the output permission, the downstream back pressure signal, the number of input time slots, the number of time slots to be output and the preset number of output time slots is specifically: When the output permission is valid and the downstream back pressure signal is not detected, if remainder≥do_num, the number of time slots to be output is updated to remainder-do_num; if (remainder+a)≥do_num, the number of time slots to be output is updated to remainder+a-do_num; Otherwise, the number of time slots to be output is updated to remainder+a; When the output permission is invalid or the downstream back pressure signal is detected, if remainder<do_num and remainder+a≤b, the number of time slots to be output is updated to remainder+a; otherwise, the number of time slots to be output remains unchanged; Among them, remainder is the number of time slots to be output, do_num is the preset number of output time slots, a is the number of input time slots, and b is the maximum number of output time slots.

6. A rate conversion device based on FlexE, characterized in that: The FlexE-based rate conversion device is used to implement the FlexE-based rate conversion method according to any one of claims 1 to 5, and the FlexE-based rate conversion device includes: A speed control unit, the speed control unit being used to output a corresponding speed control signal according to the number of input time slots, the number of time slots to be output, the preset number of output time slots and the downstream back pressure signal; The speed change execution unit is used to receive the speed change control signal output by the speed change control unit, and read the time slot data and output the time slot data of the corresponding bit width according to the speed change control signal.

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