Equipment debugging method and device, equipment, equipment system and medium

Abstract

The invention discloses an equipment debugging method and device, equipment, an equipment system and a medium, and relates to the technical field of communication, and the method comprises the steps: obtaining network card information of target equipment after the target equipment is powered on, and recognizing a target network card supporting a shared network port from all network cards of the target equipment based on the network card information; if the target network card is identified for the first time, controlling a preset control device in the target equipment to be switched to a target interface channel so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of a sideband interface of the network controller; and accessing the data transceiving signal appearing in the target interface channel to a preset control device so that the preset control device performs spectral analysis on the data transceiving signal, and debugging a clock phase offset meeting a preset function requirement based on a spectral analysis result. According to the scheme, the clock phase offset meeting the preset requirement is debugged, and accurate time sequence matching of the clock signal and the data signal is achieved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a device debugging method, device, device, device system and medium. Background Art

[0002] Since the NCSI (Network Controller Sideband Interface) protocol is mainly used to support out-of-band management of servers. It defines a sideband interface that enables the management controller of the server (such as the baseboard management controller) to communicate efficiently with the network controller (network card). This communication mechanism does not rely on the main operating system of the server, so the network device can still be managed and monitored when the operating system is unavailable. Therefore, during the operation of the server, NCSI is crucial to its management and monitoring. However, in the relevant technology, for the communication between the server and the network card device, if NCSI is used, an external clock input is required, and the clock and data signals need to have a phase offset so that the chips of both communicating parties can complete data sampling. The external clock input needs to be designed for the board routing, sort out the link length of the CLK (Clock) from the CLK Buffer to the master and slave chips respectively, and calculate the phase offset according to the NCSI protocol, and burn it offline into the EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0003] It can be seen that how to achieve precise timing matching between clock signals and data signals is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a device debugging method, apparatus, device, device system and medium, which can solve the problem of inaccurate timing matching between clock signals and data signals.

[0005] In a first aspect, the present invention discloses a device debugging method, which is applied to a management controller, comprising:

[0006] When the target device is powered on, the network card information of the target device is obtained, and based on the network card information, a target network card that supports a shared network port is identified from each network card of the target device;

[0007] If the target network card is identified for the first time, the preset control device in the target device is controlled to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of the network controller sideband interface;

[0008] The data transceiver signal appearing in the target interface channel is connected to a preset control device so that the preset control device performs spectrum analysis on the data transceiver signal and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result.

[0009] Optionally, after the target device is powered on, obtain the network card information of the target device, including:

[0010] When the target device is powered on, the presence information of each expansion card on the target device identified and reported by the preset control component is obtained;

[0011] The network card information of the target device is read from the expansion card through a preset communication bus according to the in-place information.

[0012] Optionally, identifying a target network card that supports a shared network port from each network card of the target device based on the network card information includes:

[0013] Parse and determine whether there is a support mark for supporting shared network ports in the network card information;

[0014] If it exists, the corresponding network card is determined to be a target network card that supports the shared network port.

[0015] Optionally, after determining that the corresponding network card is a target network card that supports a shared network port, the process further includes:

[0016] Matching the unique identification of the target network card with the unique identification of each historical network card;

[0017] If the matching result is a matching result in which the unique identification of the historical network card is consistent with the unique identification of the target network card, it is determined that the identification result of the target network card is not the first identification result.

[0018] Optionally, after determining that the identification result of the target network card is not the first identification result, the method further includes:

[0019] Reading a target clock phase offset corresponding to a unique identification of the target network card from a preset memory;

[0020] Sending the target clock phase offset to a preset control device so that the preset control device sets the state of the initial communication link between the target network card and the management controller to a ready state by using a communication strategy constructed based on the target clock phase offset;

[0021] Performing a stability verification process for the initial communication link to obtain corresponding verification results;

[0022] Adjusting a clock phase offset of an initial communication link based on the verification result;

[0023] Or, the initial communication link is determined as the target communication link based on the verification result.

[0024] Optionally, the communication strategy constructed based on the target clock phase offset sets the state of the initial communication link between the target network card and the management controller to a ready state, including:

[0025] By presetting the clock management circuit of the control device and adjusting the phase offset of the clock signal between the target network card and the management controller according to the target clock phase offset, a corresponding communication strategy is obtained, and the state of the initial communication link between the target network card and the management controller is set to a ready state.

[0026] Optionally, a stability verification process for the initial communication link is performed to obtain a corresponding verification result, including:

[0027] Determining whether the number of data packets sent and the number of data packets received through the initial communication link within a preset time range are the same;

[0028] If they are not the same, a readjustment instruction is sent to the preset control device, so that the preset control device re-adjusts a new clock phase offset according to the readjustment instruction and the communication timing requirements of the communication link protocol;

[0029] The step of sending the target clock phase offset to the preset control device is jumped and executed until the stability verification is passed, and the current clock phase offset is output as the clock phase offset that meets the preset functional requirements.

[0030] Optionally, the data transceiver signal appearing in the target interface channel is connected to a preset control device so that the preset control device performs spectrum analysis on the data transceiver signal, and debugs a clock phase offset that meets preset functional requirements based on the spectrum analysis result, including:

[0031] Added a spectrum analysis component for spectrum analysis in the preset control device;

[0032] Connecting the data transmission signal and the data reception signal transmitted through the target interface channel to the spectrum analysis component, so that the spectrum analysis component can determine the data transmission time point and the data reception time point from the data transmission signal and the data reception signal respectively;

[0033] The spectrum analysis component is used to calculate the data transmission delay according to the data sending time point and the data receiving time point, and then the clock phase offset is determined by using the data transmission delay and the internal reference clock of the target device;

[0034] Through a preset control device and according to the clock phase offset, the phase offset of the clock signal between the target network card and the management controller is directly increased and / or reduced to obtain a clock phase offset that meets the preset functional requirements, and the clock phase offset that meets the preset functional requirements is reported to the management controller through a preset communication bus.

[0035] In a second aspect, the present invention discloses a device debugging apparatus, which is applied to a management controller, comprising:

[0036] The information acquisition module is used to acquire the network card information of the target device after the target device is powered on, and identify the target network card that supports the shared network port from the network cards of the target device based on the network card information;

[0037] A channel switching module is used to control a preset control device in the target device to switch to a target interface channel if the target network card is identified for the first time, so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of a sideband interface of a network controller;

[0038] The offset adjustment module is used to connect the data receiving and transmitting signals appearing in the target interface channel to the preset control device so that the preset control device can perform spectrum analysis on the data receiving and transmitting signals and debug the clock phase offset that meets the preset functional requirements based on the spectrum analysis results.

[0039] In a third aspect, the present invention discloses an electronic device, comprising:

[0040] Memory for storing computer programs;

[0041] The processor is used to execute a computer program to implement the steps of the device debugging method disclosed above.

[0042] In a fourth aspect, the present invention discloses a device system, including a management controller, a network card, a preset control device, and a channel switching device; the channel switching device is used to switch the preset control device to an information transmission channel of a network controller sideband interface;

[0043] Furthermore, the management controller implements the steps of the device debugging method disclosed above by executing the computer program.

[0044] In a fifth aspect, the present invention discloses a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the device debugging method disclosed above are implemented.

[0045] It can be seen that the present invention discloses a device debugging method, which is applied to a management controller, including: when the target device is powered on, obtaining the network card information of the target device, and identifying the target network card that supports the shared network port from the network cards of the target device based on the network card information; if the target network card is identified for the first time, controlling the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is the information transmission channel of the network controller sideband interface; connecting the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal, and debugging the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0046] It can be seen from the above technical solution that by quickly determining whether the network card is identified for the first time, and then taking different operation procedures, it automatically switches to the appropriate target interface channel for the first identification, instead of adopting a fixed single link management method; after identifying the target network card that is inserted for the first time, the management controller controls the preset control device in the target device to switch to the corresponding target interface channel, establishes a communication link between the target network card and the management controller, and connects the data transceiver signal generated by the communication link to the preset control device for spectrum analysis, so as to obtain the adjusted clock signal offset, thereby meeting the communication timing requirements between the management controller and the target network card, achieving precise matching of the clock signal and the data signal, ensuring that the data can be accurately sampled at the appropriate clock edge, and reducing communication errors caused by timing mismatch; moreover, the preset control device can analyze the adjusted clock signal offset and report it to the management controller, and the management controller can record the offset information, and directly call the corresponding clock signal offset when the same network card is identified subsequently, avoiding repeated complex debugging processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A flow chart of a device debugging method provided by an embodiment of the present invention;

[0049] Figure 2 A flow chart of a specific device debugging method provided by an embodiment of the present invention;

[0050] Figure 3 A circuit design diagram of a CPLD replacing a CLK Buffer provided in an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the structure of a device debugging apparatus provided by an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of the structure of a device system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0056] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0057] Since the NCSI protocol is mainly used to support out-of-band management of servers. It defines a sideband interface that enables the management controller of the server (such as the baseboard management controller) to communicate efficiently with the network controller (network card). This communication mechanism does not rely on the main operating system of the server, so the network equipment can still be managed and monitored when the operating system is unavailable. Therefore, during the operation of the server, NCSI is crucial to its management and monitoring. However, in the relevant technology, for the communication process between the server and the network card device, if NCSI is used, an external clock input is required, and the clock and data signals need to have a phase offset so that the chips of both communicating parties can complete data sampling. The external clock input needs to be designed for the wiring on the board during the line design, and the link length from the CLK Buffer to the master and slave chips is sorted out, and the phase offset is calculated according to the NCSI protocol, and burned into the EEPROM offline.

[0058] To this end, the present invention provides a device debugging solution that can achieve precise timing matching of clock signals and data signals.

[0059] Reference Figure 1As shown, the present invention provides a device debugging method, which is applied to a management controller, comprising:

[0060] Step S11: when the target device is powered on, the network card information of the target device is obtained, and based on the network card information, a target network card that supports a shared network port is identified from among the network cards of the target device.

[0061] In this embodiment, after the target device is powered on, the presence information of each expansion card on the target device identified and reported by the preset control device is obtained; it can be understood that the target device is a server, the management controller is specifically a baseboard management controller BMC (Board Management Controller), and the preset control device is a CPLD (Complex Programmable Logic Device). Therefore, after the server is powered on, the BMC sends instructions to control the CPLD, and the CPLD further identifies and reports the presence information of each expansion card on the server, that is, the CPLD identifies the #PRSNT signal of each expansion card to determine whether these expansion cards have been correctly installed in the slot of the server, that is, whether they are "in place", where the expansion cards may include but are not limited to: OCP (Open Compute Project) standard cards and PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) standard cards.

[0062] In this embodiment, the network card information of the target device is read from the expansion card according to the in-place information and through the preset communication bus. It is understandable that after the CPLD determines the in-place status of the OCP and PCIE standard cards, it will send these in-place information to the BMC. In this way, the BMC can know which expansion cards have been installed in the server, and can further configure and manage them, such as loading the corresponding driver or allocating system resources. Then the BMC reads the network card information from the expansion card through the preset communication bus I2C (Inter-Integrated Circuit, a two-way two-wire synchronous serial bus) and the in-place information of the expansion card. Specifically, the BMC sends specific query commands to each in-place standard card, and these commands follow a certain communication protocol. For example, for OCP and PCIE standard cards that meet industry standards, they all have specified device identification registers or information storage areas. The query command sent by the BMC can read the information in these areas to determine the type, function and other details of the standard card, that is, the network card information.

[0063] In this embodiment, the network card information is parsed and determined whether there is a support identifier for supporting the shared network port; if there is, the corresponding network card is determined to be a target network card that supports the shared network port. It can be understood that after the BMC reads the network card information, it parses the network card information to identify whether it contains the network card function. This involves the interpretation of the device function code or specific configuration register. Specifically, the network card information format returned by the expansion card is usually organized according to a certain standard or a format customized by the expansion card manufacturer. In the network card information, there will be some specific bits or fields used to identify whether the device supports the shared port function. For example, there may be a specific byte in which the combination of some bits (such as bits 3-5) indicates the support of the shared port. If the binary value of these bits is "010", it means that the shared port is supported, while "000" means that it is not supported. The BMC determines whether the expansion card supports the shared port by identifying these specific bit combinations.

[0064] In order to accurately determine whether the network card is the target network card, the BMC will also combine the technical documentation of the device and related industry protocol standards. Different network card manufacturers will follow different identification methods, but generally they will explain in the technical documentation how to determine whether various functions are supported through the returned device information. For example, for expansion cards that comply with a specific industry standard (such as a specific version of the PCIE network card standard), the document will clearly specify the identification location and format supported by the shared port. By referring to these documents and standards, the BMC can accurately determine whether the network card supports the shared port from the information returned by the device, and then determine the target network card.

[0065] In this embodiment, after determining that the corresponding network card is the target network card, the unique identity of the target network card is matched with the unique identity of each historical network card; if the matching result is a matching result in which the unique identity of the historical network card is consistent with the unique identity of the target network card, then the identification result of the target network card is determined to be a non-first identification result. It can be understood that there is an area inside the BMC to store historical network card information. When the network card is identified through the I2C bus to support the shared port function, the BMC will compare the unique identity of the network card (such as device ID, MAC address, specific hardware version number, etc.) with the stored historical network card information. By comparing this information one by one, it can be determined whether the network card has been identified before. For example, if the device ID of the newly identified network card is exactly the same as the device ID of a certain network card that has been recorded, then it can be preliminarily determined that this network card is not identified for the first time.

[0066] In this embodiment, if it is not the first time that the network card is identified, the target clock phase offset corresponding to the unique identification of the target network card is read from the preset memory; the target clock phase offset is sent to the preset control device, so that the preset control device uses the communication strategy constructed based on the target clock phase offset to set the state of the initial communication link between the target network card and the management controller to the ready state; it can be understood that after calling the corresponding CLK phase offset strategy, that is, the target clock phase offset, from the preset memory, the BMC will send this offset to the CPLD. After receiving the offset, the CPLD constructs a corresponding communication strategy to set the state of the initial communication link between the target network card and the management controller to the ready state. Among them, the specific process of constructing the communication strategy is as follows:

[0067] By presetting the clock management circuit of the control device and adjusting the phase offset of the clock signal between the target network card and the management controller according to the target clock phase offset, the corresponding communication strategy is obtained, and the state of the initial communication link between the target network card and the management controller is set to the ready state. It can be understood that the CPLD uses its internal clock management circuit (such as a clock buffer or a phase-locked loop) to adjust the clock phase offset between the master and slave chips (BMC and the target network card) to obtain the communication strategy. In this way, the clock synchronization of the communication link is set to the valid state of the historical record, providing suitable clock conditions for subsequent data transmission.

[0068] In this embodiment, a stability verification process for the initial communication link is executed to obtain a corresponding verification result; the clock phase offset of the initial communication link is adjusted based on the verification result; or, the initial communication link is determined to be the target communication link based on the verification result. Specifically, it is determined whether the number of data packets sent through the initial communication link within a preset time range is the same as the number of data packets received; if they are not the same, a readjustment instruction is sent to the preset control device so that the preset control device can re-debug a new clock phase offset according to the readjustment instruction and in accordance with the communication timing requirements of the communication link protocol; the step of sending the target clock phase offset to the preset control device is jumped and executed until the stability verification is passed, and the current clock phase offset is output as the clock phase offset that meets the preset functional requirements. It is understandable that the stability verification of the initial communication link in the ready state is performed, and the stability verification is network packet loss detection and functional stress detection to evaluate whether the communication link can work stably and efficiently when the CLK offset recorded before the application is applied. Specifically, when the shared network port is connected, the specific data format message is included in the data packet. When the shared port is detected to be connected, the packet loss mechanism detection is continuously performed, and no packet loss for 1 hour is set to be considered as passing the network function stress test. If a packet loss problem is detected during the stress test, the BMC sends an instruction to the CPLD to make a secondary adjustment within the NCSI protocol timing range, and then perform a stress test until the network function stress test passes and is considered to be normal. The CLK offset at this time is written into the preset memory, avoiding the need for multiple complex network function tests like related technologies.

[0069] Step S12: If the target network card is identified for the first time, control the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of the network controller sideband interface.

[0070] In this embodiment, the unique identification of the target network card is matched with the unique identification of each historical network card; if the matching result is that there is no matching result in which the unique identification of the historical network card is consistent with the unique identification of the target network card, then the identification result of the target network card is determined to be the first identification result, and then the BMC issues an instruction to the CPLD to switch the NCSI path, so that the BMC and the target network card establish a communication link, and the shared port path is connected. The NCSI path is the target interface channel.

[0071] Step S13: connecting the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal, and debugs the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0072] In this embodiment, a spectrum analysis component for spectrum analysis is added to the preset control device; the data transmission signal and the data receiving signal transmitted through the target interface channel are connected to the spectrum analysis component, so that the spectrum analysis component can determine the data transmission time point and the data receiving time point from the data transmission signal and the data receiving signal respectively; the data transmission delay is calculated by the spectrum analysis component according to the data transmission time point and the data receiving time point, and then the clock phase offset is determined by using the data transmission delay and the internal reference clock of the target device; the phase offset of the clock signal between the target network card and the management controller is directly increased and / or decreased according to the clock phase offset through the preset control device to obtain the clock phase offset that meets the preset functional requirements, and the clock phase offset that meets the preset functional requirements is reported to the management controller through the preset communication bus. It can be understood that the CPLD directly accesses the TX_EN (Transmit Enable, data transmission signal) and RX_CRSDV (Receive Carrier Sense and DataValid, data receiving signal) through the target interface channel, and the signal spectrum analysis component newly added by the CPLD determines the data transmission time point and the data receiving time point from the data transmission signal and the data receiving signal respectively, and the difference between the two time points reflects the delay of the data transmission process.

[0073] It should be noted that since data transmission depends on the clock signal for synchronization, this delay is compared with the expected transmission time of the clock signal to obtain the phase offset of the clock signal. For example, in ideal NCSI communication, according to the clock signal and the data transmission timing specified by the protocol (such as the setup time of data rising before clock rising ≥4ns, and the hold time of clock rising before data falling ≤2ns, and one clock cycle is 20ns), the data should be sampled at a specific clock edge. However, if the actual data transmission time determined by TX_EN and RX_CRSDV does not meet this ideal situation, then the time difference from the ideal situation is the offset of the clock signal relative to the normal timing. It reflects the degree of asynchrony between the clock signals of the master and slave chips, and provides a key quantitative basis for the subsequent CPLD to adjust the clock phase.

[0074] Furthermore, the data transmission delay and the internal reference clock of the server can be used to obtain the quantified value of the clock phase offset. First, the internal reference clock provides an accurate time reference for the data transmission delay. Since the internal reference clock has a stable period and frequency, the delay of data transmission relative to the clock period can be determined by comparing the data transmission delay with the period of the internal reference clock.

[0075] For example, assume that the internal reference clock period is T and the data transmission delay is Δt. If Δt is greater than a portion of a clock period T (such as within the establishment time range specified by the NCSI protocol where the data rise precedes the clock rise), then this excess time portion is a manifestation of the clock offset. In this way, the data transmission delay is converted into a quantized value of the clock offset relative to the internal reference clock, providing a specific numerical basis for the subsequent adjustment of the phase of the clock signal.

[0076] In addition to quantifying the clock phase offset, the phase adjustment direction and amplitude of the clock signal can also be determined. If the data transmission delay causes the data to arrive at the receiving end earlier than the ideal clock edge (according to the NCSI protocol requirements), it means that the clock signal is relatively lagging, and the clock phase offset needs to be increased internally by the CPLD, that is, a positive phase adjustment is performed, and the adjustment amplitude is determined by the comparison of the data transmission delay and the internal reference clock cycle. Conversely, if the data transmission delay causes the data to arrive at the receiving end later than the ideal clock edge, the clock signal is relatively advanced, and the clock phase offset needs to be reduced, that is, a negative phase adjustment is performed. This analysis based on data transmission delay and internal reference clock can accurately guide the CPLD to adjust the phase of the clock signal between the master and slave chips to meet the timing requirements of the NCSI protocol, and then debug the appropriate CLK phase offset, which directly acts on CLK0 / CLK1 / CLK2 internally.

[0077] In addition, for the calculation of clock phase offset, in addition to the above-mentioned spectrum analysis component, different working conditions are taken into account in the calculation scope of clock phase offset, and algorithms based on machine learning or artificial intelligence are used to predict and adjust the CLK phase offset. By training a large amount of clock data, these algorithms may be able to more accurately predict the optimal CLK phase offset under different working conditions, thereby improving the stability and performance of the system. Specifically, a large amount of clock data is collected from the existing system. These data should include CLK signal parameters under different working conditions, such as clock frequency, phase, operating temperature, load conditions, etc. These data will be used as training data to help the algorithm learn the relationship between CLK phase offset and various working conditions. Sensors and data acquisition devices can be used to obtain these parameters to ensure the accuracy and integrity of the data. For example, a high-precision frequency meter is used to measure the clock frequency, and a temperature sensor is used to measure the operating temperature. Then, feature extraction is performed on the collected data. For the calculation of CLK phase offset, relevant features may include: The rate of change of clock frequency: reflects the fluctuation of the clock frequency in different time periods. The correlation between temperature and clock frequency: temperature has an impact on the clock frequency, and this correlation is extracted as a feature. Relationship between load change and clock phase: Different loads may cause changes in clock phase, and the load change is used as a feature. Then the data is normalized so that the data with different features are at the same level, and the data is mapped to the range of 0 to 1 to facilitate subsequent algorithm processing. Considering that multiple factors (temperature, load, frequency change, etc.) interact to affect the clock phase offset, the deep learning network can learn more complex mapping relationships. Select a neural network model (such as a multi-layer perceptron, a deep learning network) as the initial model, and divide the preprocessed data into a training set and a validation set. The training set is used to train the model, and the validation set is used to evaluate the performance of the model. Use the training set to train the selected model, and adjust the parameters of the model by minimizing the loss function (such as mean square error, MSE). Use the back propagation algorithm to update the weights and biases of the network. During the training process, constantly monitor the performance of the model on the validation set to prevent overfitting. If the error of the model on the validation set begins to rise, it means that overfitting may have occurred, and measures need to be taken, such as adding regularization terms and adjusting the complexity of the model. When the model performance reaches a satisfactory level, the model is deployed to the actual system. During system operation, the real-time clock data is used as the input of the model, and the model outputs the predicted CLK phase offset. The system adjusts the CLK phase offset according to the model prediction results to achieve precise control of the clock and improve the stability and performance of the system.

[0078] In this embodiment, after the clock phase offset that meets the preset functional requirements is reported to the BMC via I2C, the BMC will send this offset to the CPLD. After receiving the offset, the CPLD constructs a corresponding communication strategy to set the state of the initial communication link between the target network card and the management controller to the ready state, and then jumps to the aforementioned publicly disclosed stability verification process.

[0079] Reference Figure 2 As shown, the present invention discloses a specific device debugging method process, and the specific steps are as follows:

[0080] 1. The server is powered on, and the CPLD recognizes that the OCP and PCIE card #PRSNT are in place, and reports the presence information to the BMC.

[0081] 2. The BMC obtains the network card information through the I2C bus, identifies which network card supports the shared port function, and determines whether this is the first time the network card is used:

[0082] ① If it is not the first recognition, the corresponding CLK phase shift strategy is directly called from the EEPROM and sent to the CPLD;

[0083] ②If it is the first time recognition, proceed to step 3.

[0084] 3. The BMC instructs the CPLD to switch the NCSI path, so that the BMC main control chip and the network card slave device establish a link, and the shared port path is connected.

[0085] 4.CPLD performs logic according to the instructions issued by BMC:

[0086] ① If there is only the instruction for first identification of the network card, the CPLD directly debugs the appropriate CLK phase offset through the TX_EN and RX_CRSDV accessed by the master and slave chips, through the signal spectrum analysis module and the timing requirements of the clock and data in the NCSI protocol, and directly acts on CLK0 / CLK1 / CLK2 internally;

[0087] ② If it is identified that the BMC issues a re-debugging instruction due to packet loss, a new CLK phase offset is re-debugged according to the disable logic issued by the BMC.

[0088] 5. CPLD reports the CLK phase offset to BMC, and BMC writes it into EEPROM to record the binding relationship between the network card and it.

[0089] 6. Then the BMC instruction packet loss mechanism is detected, and the network function stress test at a specific time is used to determine whether the current CLK phase offset meets the functional requirements.

[0090] 7. If the requirements are not met, a re-debugging instruction is issued and the process returns to step 4-② to continue.

[0091] If the requirements are met, confirm that the binding relationship in step 5 is valid and the logic ends.

[0092] In this way, by replacing CLK Buffer with CPLD, ISO Switch (Isolation Switch) is extended by more than one design, CPLD has built-in signal spectrum analysis module and logic, BMC designs the logic of network card chip recognition memory mechanism, network packet loss detection and functional pressure mechanism, which can effectively improve the R&D investment caused by manual calculation, return board testing and repeated adjustments after the shared port link design, and save single board costs.

[0093] like Figure 3 , taking the dual-shared port server design as an example. Delete the CLK Buffer, EEPROM and the 50M crystal oscillator, and replace them with CPLD and 25M crystal oscillator input. Add a signal spectrum analysis module inside the CPLD; refer to the NCSI test method and principle (the actual signal data transmission is through NCSI_Data, TX_EN and RX_CRSDV are used as the signals for the sender and receiver to indicate when the data is sent and received), and connect the NCSI signal, TX_EN and RX_CRSDV, to the CPLD without affecting the original communication link, as the signal input for signal spectrum analysis and adjustment of phase offset. According to the spectrum analysis module, the CPLD parses the CLK offset of the master and slave chips, directly increases or decreases the phase offset internally, and realizes the adjustment; and reports the adjusted offset to the BMC through the I2C bus.

[0094] BMC has two mechanisms built into the logic. One is the network card chip identification and memory mechanism. When the server is powered on for the first time with a network card, after the BMC identifies the specific chip of the network card through the I2C link, the CLK clock offset adjusted by the CPLD is written into the EEPROM as a fixed matching relationship. The next time such a network card is identified, the corresponding offset strategy can be directly called. The second is the shared port packet loss mechanism detection; a specific data format message is enclosed in a data packet. When the BMC detects that the shared port is connected, it continues to perform packet loss mechanism detection, and sets 1 hour of no packet loss to be considered as passing the network function stress test. If a packet loss problem is detected during the stress test, the BMC sends a command to the CPLD to make a secondary adjustment within the NCSI protocol timing range, and then perform the stress test; until the network function stress test passes, it is considered to be normal, and the CLK clock offset at this time is written into the EEPROM.

[0095] It can be seen that the present invention discloses a device debugging method, which is applied to a management controller, including: when the target device is powered on, obtaining the network card information of the target device, and identifying the target network card that supports the shared network port from the network cards of the target device based on the network card information; if the target network card is identified for the first time, controlling the preset control device in the target device to switch to the target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is the information transmission channel of the network controller sideband interface; connecting the data transceiver signal appearing in the target interface channel to the preset control device, so that the preset control device performs spectrum analysis on the data transceiver signal, and debugging the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0096] It can be seen from the above technical solution that by quickly determining whether the network card is identified for the first time, and then taking different operation procedures, it automatically switches to the appropriate target interface channel for the first identification, instead of adopting a fixed single link management method; after identifying the target network card that is inserted for the first time, the management controller controls the preset control device in the target device to switch to the corresponding target interface channel, establishes a communication link between the target network card and the management controller, and connects the data transceiver signal generated by the communication link to the preset control device for spectrum analysis, so as to obtain the adjusted clock signal offset, thereby meeting the communication timing requirements between the management controller and the target network card, achieving precise matching of the clock signal and the data signal, ensuring that the data can be accurately sampled at the appropriate clock edge, and reducing communication errors caused by timing mismatch; moreover, the preset control device can analyze the adjusted clock signal offset and report it to the management controller, and the management controller can record the offset information, and directly call the corresponding clock signal offset when the same network card is identified subsequently, avoiding repeated complex debugging processes.

[0097] Reference Figure 4 As shown, the present invention also discloses a device debugging apparatus correspondingly, which is applied to a management controller, comprising:

[0098] The information acquisition module 11 is used to acquire the network card information of the target device after the target device is powered on, and identify the target network card that supports the shared network port from the network cards of the target device based on the network card information;

[0099] The channel switching module 12 is used to control the preset control device in the target device to switch to the target interface channel if the target network card is identified for the first time, so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of the network controller sideband interface;

[0100] The offset adjustment module 13 is used to connect the data receiving and transmitting signal appearing in the target interface channel to the preset control device so that the preset control device performs spectrum analysis on the data receiving and transmitting signal and debugs the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

[0101] It can be seen that by quickly determining whether the network card is recognized for the first time, and then taking different operation procedures, it automatically switches to the appropriate target interface channel for the first recognition, instead of adopting a fixed single link management method; after identifying the target network card that is inserted for the first time, the management controller controls the preset control device in the target device to switch to the corresponding target interface channel, establishes a communication link between the target network card and the management controller, and connects the data transceiver signal generated by the communication link to the preset control device for spectrum analysis, so as to obtain the adjusted clock signal offset, thereby meeting the communication timing requirements between the management controller and the target network card, achieving precise matching of clock signals and data signals, ensuring that data can be accurately sampled at the appropriate clock edge, and reducing communication errors caused by timing mismatch; moreover, the preset control device can analyze the adjusted clock signal offset and report it to the management controller, and the management controller can record the offset information, and directly call the corresponding clock signal offset when the same network card is recognized subsequently, avoiding repeated complex debugging processes.

[0102] Furthermore, the present application also discloses an electronic device. Figure 5 is a structural diagram of an electronic device according to an exemplary embodiment. Figure 5 The content in the description cannot be considered as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the device debugging method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0103] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0104] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0105] The operating system 221 is used to manage and control various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the device debugging method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0106] Reference Figure 6 As shown, the present invention also provides a device system, including a management controller, a network card, a preset control device and a channel switching device; the channel switching device is used to switch the preset control device to the information transmission channel of the network controller sideband interface; and the management controller executes a computer program to implement the steps of the device debugging method disclosed above. Specifically, a new ISO Switch chip, that is, a channel switching device, and CPLD controls OCP_RISER_EN for switching the path, which can expand the NCSI link from one to multiple, and enable the BMC to establish interaction with multiple links by itself. The in-place signals of the OCP network card and the PCIE standard card are connected to the CPLD through GPIO (General-Purpose Input / Output Ports) and reported to the BMC. The BMC can automatically identify the logic and switch the corresponding shared port link by itself.

[0107] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the device debugging method disclosed above. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the above embodiments, and no further description will be given here.

[0108] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0109] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0110] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0111] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0112] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A device debugging method, characterized in that: Applicable to management controllers, including: When the target device is powered on, the network card information of the target device is obtained, and based on the network card information, a target network card that supports a shared network port is identified from each network card of the target device; If the target network card is identified for the first time, control a preset control device in the target device to switch to a target interface channel to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of a network controller sideband interface; The data transceiver signal appearing in the target interface channel is connected to the preset control device so that the preset control device performs spectrum analysis on the data transceiver signal and debugs the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

2. The device debugging method according to claim 1, characterized in that: When the target device is powered on, obtaining the network card information of the target device includes: When the target device is powered on, obtaining the presence information of each expansion card on the target device identified and reported by the preset control component; The network card information of the target device is read from the expansion card through a preset communication bus according to the presence information.

3. The device debugging method according to claim 1, characterized in that: The step of identifying a target network card that supports a shared network port from each network card of the target device based on the network card information includes: Parse and determine whether there is a support identifier for supporting a shared network port in the network card information; If it exists, the corresponding network card is determined to be a target network card that supports the shared network port.

4. The device debugging method according to claim 3, characterized in that: After determining that the corresponding network card is a target network card that supports a shared network port, the method further includes: Matching the unique identity of the target network card with the unique identity of each historical network card; If the matching result is a matching result in which the unique identification of the historical network card is consistent with the unique identification of the target network card, it is determined that the identification result of the target network card is not the first identification result.

5. The device debugging method according to claim 4, characterized in that: After determining that the identification result of the target network card is not the first identification result, the method further includes: Reading a target clock phase offset corresponding to the unique identification of the target network card from a preset memory; Sending the target clock phase offset to a preset control device so that the preset control device sets the state of the initial communication link between the target network card and the management controller to a ready state by using a communication strategy constructed based on the target clock phase offset; Executing a stability verification process for the initial communication link to obtain a corresponding verification result; Adjusting a clock phase offset of the initial communication link based on the verification result; Or, the initial communication link is determined to be a target communication link based on the verification result.

6. The device debugging method according to claim 5, characterized in that: The communication strategy constructed based on the target clock phase offset sets the state of the initial communication link between the target network card and the management controller to a ready state, including: The phase offset of the clock signal between the target network card and the management controller is adjusted according to the target clock phase offset through the clock management circuit of the preset control device to obtain a corresponding communication strategy, and the state of the initial communication link between the target network card and the management controller is set to a ready state.

7. The device debugging method according to claim 5, characterized in that: The performing of the stability verification process of the initial communication link to obtain a corresponding verification result includes: Determining whether the number of data packets sent and the number of data packets received through the initial communication link within a preset time range are the same; If they are not the same, a readjustment instruction is sent to the preset control device, so that the preset control device re-adjusts a new clock phase offset according to the readjustment instruction and the communication timing requirements of the communication link protocol; Jump to execute the step of sending the target clock phase offset to the preset control device until the stability verification is passed, and output the current clock phase offset as the clock phase offset that meets the preset functional requirements.

8. The device debugging method according to claim 1, characterized in that: The step of connecting the data transceiver signal appearing in the target interface channel to the preset control device so that the preset control device performs spectrum analysis on the data transceiver signal, and debugging a clock phase offset that meets preset functional requirements based on the spectrum analysis result includes: Adding a spectrum analysis component for spectrum analysis to the preset control device; Connecting the data transmission signal and the data reception signal transmitted through the target interface channel to the spectrum analysis component, so that the spectrum analysis component can determine the data transmission time point and the data reception time point from the data transmission signal and the data reception signal respectively; Calculate the data transmission delay by the spectrum analysis component according to the data sending time point and the data receiving time point, and then determine the clock phase offset by using the data transmission delay and the internal reference clock of the target device; The phase offset of the clock signal between the target network card and the management controller is directly increased and / or decreased through the preset control device and according to the clock phase offset to obtain a clock phase offset that meets the preset functional requirements, and the clock phase offset that meets the preset functional requirements is reported to the management controller through a preset communication bus.

9. A device debugging device, characterized in that: Applicable to management controllers, including: An information acquisition module, used for acquiring the network card information of the target device after the target device is powered on, and identifying the target network card supporting the shared network port from the network cards of the target device based on the network card information; a channel switching module, configured to control a preset control device in the target device to switch to a target interface channel if the target network card is identified for the first time, so as to establish a communication link between the management controller and the target network card; the target interface channel is an information transmission channel of a network controller sideband interface; The offset adjustment module is used to connect the data receiving and transmitting signal appearing in the target interface channel to the preset control device so that the preset control device can perform spectrum analysis on the data receiving and transmitting signal and debug the clock phase offset that meets the preset functional requirements based on the spectrum analysis result.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the device debugging method according to any one of claims 1 to 8.

11. A device system, characterized in that: It includes a management controller, a network card, a preset control device and a channel switching device; the channel switching device is used to switch the preset control device to the information transmission channel of the network controller sideband interface; Furthermore, the management controller implements the steps of the device debugging method according to any one of claims 1 to 8 by executing a computer program.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the device debugging method according to any one of claims 1 to 8 are implemented.

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