SHJ battery with laminated coating structure and preparation method of SHJ battery

Abstract

The invention belongs to the technical field of SHJ batteries, and particularly relates to an SHJ battery with a laminated coating structure and a preparation method thereof, and the SHJ battery with the laminated coating structure comprises an N-type silicon substrate which is provided with a first surface and a second surface corresponding to the first surface; the front amorphous silicon layer is arranged on the first surface; the N-type doped layer is plated on the front amorphous silicon layer; the TSO film layer is overlapped on the first ITO thin film layer to form an ITO / SiON laminated film structure; the first metal electrodes are arranged on the two sides of the TSO film layer to form a plurality of main grids; the back amorphous silicon layer is arranged on the second surface; the P-type doped layer is arranged on the back amorphous silicon layer to form a PN junction; the second ITO thin film layer is deposited on the P-type doping layer; and the second metal electrodes are arranged on the two sides of the first ITO thin film layer to form a plurality of main grids.

Description

Technical Field

[0001] The invention belongs to the technical field of SHJ batteries, and in particular relates to an SHJ battery with a laminated coating structure and a preparation method thereof. Background Art

[0002] In the process of manufacturing HJT cells, adding an ITO film between the electrode and the amorphous silicon layer can effectively increase the collection of carriers. The transparent conductive oxide film has the dual functions of optical transparency and conductivity, plays a key role in the collection of effective carriers, can reduce light reflection, and has a good light trapping effect. It is a good window layer material.

[0003] TSO film has better transmittance and lower reflection, but it is not conductive. If 0BB technology is used directly, the current cannot be transmitted. Currently, ITO on the market is PVD coated with a thickness of about 100nm to form a transparent conductive film, which is then screen-printed to make battery cells. However, the ITO film itself is relatively expensive and has poor short-wave transmittance.

[0004] Therefore, how to improve the short-wave transmittance of the TSO membrane in the SHJ battery is a technical problem that needs to be solved urgently in this field.

[0005] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the invention

[0006] The embodiments of the present disclosure at least provide a SHJ battery having a laminated coating structure and a method for preparing the same.

[0007] In a first aspect, an embodiment of the present disclosure provides a SHJ battery with a stacked coating structure, including: an N-type silicon substrate having a first surface and a second surface corresponding to the first surface; a front amorphous silicon layer, arranged on the first surface; an N-type doped layer, plated on the front amorphous silicon layer; a TSO film layer, superimposed on the first ITO thin film layer, forming an ITO / SiON stacked film structure; a first metal electrode, arranged on both sides of the TSO film layer, forming a plurality of main grids; a back amorphous silicon layer, arranged on the second surface; a P-type doped layer, arranged on the back amorphous silicon layer, forming a PN junction; a second ITO thin film layer, deposited on the P-type doped layer; a second metal electrode, arranged on both sides of the first ITO thin film layer, forming a plurality of main grids.

[0008] In an optional implementation, reinforcement blocks are disposed on the first metal electrode and the second metal electrode; and a gap region exists between the reinforcement blocks adjacently disposed on both sides.

[0009] In an optional embodiment, the size of the reinforcement block is 0.6-1mm*0.1-0.4mm.

[0010] In an optional embodiment, the width of the gap area is 0.8-1.5 cm.

[0011] In an optional implementation, the thickness of the N-type silicon substrate is 110-130 μm.

[0012] In an optional implementation, the thickness of the front amorphous silicon layer is 3-6 nm; the thickness of the back amorphous silicon layer is 3-6 nm.

[0013] In an optional implementation, the thickness of the N-type doping layer is 20-30 nm; the thickness of the P-type doping layer is 20-30 nm.

[0014] In an optional implementation, the thickness of the first ITO thin film layer is 60-80 nm; the thickness of the second ITO thin film layer is 80-100 nm.

[0015] In an optional embodiment, the TSO film layer has a thickness of 20-40 nm.

[0016] In an optional implementation, the thickness of the first metal electrode and the second metal electrode is 10-20 μm.

[0017] In a second aspect, the disclosed embodiment also provides a method for preparing an SHJ battery with a laminated coating structure as described above, comprising the following steps: step S1, double-sided polishing of an N-type silicon substrate; step S2, making a front amorphous silicon layer and an N-type doped layer on the first surface of the N-type silicon substrate, and making a back amorphous silicon layer and a P-type doped layer on the second surface of the N-type silicon substrate; step S3, depositing a first ITO thin film layer and a second ITO thin film layer on the N-type doped layer and the P-type doped layer, respectively; step S4, superimposing a TSO film layer on the first ITO thin film layer to form an ITO / SiON laminated film structure; step S5, opening a number of small holes of 0.6-1mm*0.1*0.4mm on the large stencil corresponding to the silicon wafer position, printing silver paste onto the silicon wafer through the small holes, and obtaining a metal electrode after drying and hardening; wherein the metal electrode is provided with a reinforcing block.

[0018] The beneficial effects of the present invention are that the SHJ battery with a laminated coating structure and the preparation method thereof utilize the high transmittance and low reflectivity of the TSO film to form an ITO / SiON laminated film structure, and achieve direct contact between the welding strip and the auxiliary grid through laser grooving in conjunction with the 0BB wire mesh technology. After providing a reinforcing block with a gap area, the connecting wire is eliminated, the shading area is reduced, the light receiving area is increased, the current of the HJT battery is increased, and ultimately the short-circuit current and efficiency are both improved.

[0019] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic structural diagram of an SHJ battery with a laminated coating structure provided in an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of components of an embodiment provided for an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of components of a comparative example provided in an embodiment of the present disclosure.

[0025] In the figure:

[0026] 1. N-type silicon substrate; 2. Front amorphous silicon layer; 3. Back amorphous silicon layer; 4. N-type doped layer; 5. P-type doped layer; 6. First ITO thin film layer; 7. Second ITO thin film layer; 8. TSO film layer; 9. First metal electrode; 10. Second metal electrode. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0029] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0030] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limited. As used herein, the singular articles "one", "an" and "the" may also be intended to include plural forms, unless it is clearly indicated above that this is not the case. The terms "comprise", "include" and "have" are inclusive, and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0031] The existing public patent 202321710808.X provides a HJT battery with an ITO / SiON laminated film structure, such as Figure 3 As shown, in subsequent use, the cost remains high and the short-wave transmission is affected because a whole section of reinforcement blocks is set.

[0032] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0034] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0035] See also Figure 1 ,like Figure 1 As shown, the embodiment of the present disclosure provides a stacked film structure, including: an SHJ battery with a stacked film structure, including: an N-type silicon substrate, having a first surface and a second surface corresponding to the first surface; a front amorphous silicon layer, arranged on the first surface; an N-type doped layer, plated on the front amorphous silicon layer; a first ITO thin film layer, deposited on the N-type doped layer; a TSO film layer, superimposed on the first ITO thin film layer, forming an ITO / SiON stacked film structure; a first metal electrode, arranged on both sides of the TSO film layer, forming a plurality of main grids; a back amorphous silicon layer, arranged on the second surface; a P-type doped layer, arranged on the back amorphous silicon layer, forming a PN junction; a second ITO thin film layer, deposited on the P-type doped layer; a second metal electrode, arranged on both sides of the first ITO thin film layer, forming a plurality of main grids.

[0036] In some embodiments, specifically, reinforcement blocks are disposed on the first metal electrode and the second metal electrode; and there is a gap area between the reinforcement blocks adjacently disposed on both sides.

[0037] In some embodiments, specifically, the size of the reinforcement block is 0.6-1 mm*0.1-0.4 mm, preferably 0.8 mm*0.4 mm, 0.8 mm*0.2 mm and 0.8 mm*0.1 mm.

[0038] In some embodiments, specifically, the width of the gap area is 0.8-1.5 cm, preferably 0.9 cm, 1 cm and 1.1 cm.

[0039] In some embodiments, specifically, the thickness of the N-type silicon substrate is 110-130 μm.

[0040] In some embodiments, specifically, the thickness of the front amorphous silicon layer is 3-6 nm; the thickness of the back amorphous silicon layer is 3-6 nm.

[0041] In some embodiments, specifically, the thickness of the N-type doping layer is 20-30 nm; the thickness of the P-type doping layer is 20-30 nm.

[0042] In some embodiments, specifically, the thickness of the first ITO thin film layer is 60-80 nm; the thickness of the second ITO thin film layer is 80-100 nm.

[0043] In some embodiments, specifically, the thickness of the TSO film layer is 20-40 nm.

[0044] In some embodiments, specifically, the thickness of the first metal electrode and the second metal electrode is 10-20 μm.

[0045] The disclosed embodiment also provides a method for preparing an SHJ battery with a laminated coating structure as described above, comprising the following steps: step S1, double-sided polishing of an N-type silicon substrate; step S2, forming a front amorphous silicon layer and an N-type doped layer on the first surface of the N-type silicon substrate, and forming a back amorphous silicon layer and a P-type doped layer on the second surface of the N-type silicon substrate; step S3, depositing a first ITO thin film layer and a second ITO thin film layer on the N-type doped layer and the P-type doped layer, respectively; step S4, superimposing a TSO film layer on the first ITO thin film layer to form an ITO / SiON laminated film structure; step S5, opening a number of small holes of 0.6-1mm*0.1*0.4mm on the large stencil corresponding to the silicon wafer position, printing silver paste onto the silicon wafer through the small holes, and obtaining a metal electrode after drying and hardening; wherein the metal electrode is provided with a reinforcing block.

[0046] The embodiment and the comparative example with the same parameter specifications were set, and a silicon wafer with an area of ​​210mm*105mm was selected. The difference was that the reinforcement block of the embodiment was arranged in a segmented manner as described above, and the reinforcement block of the comparative example was arranged in a whole segment as described in Patent 202321710808.X, and the following performance tests were performed:

[0047] 1. Take two groups of ITO filmed silicon wafers and mark them as Example and Comparative Example respectively;

[0048] 2. The embodiments and comparative examples were subjected to 0BB screen printing and cured;

[0049] 3. Coating the front side of the embodiment with TSO film;

[0050] 4. Laser mold the welding strip position of the embodiment;

[0051] 5. Then use a HALM tester to test the battery efficiency of the comparative example and the embodiment.

[0052] For details, please refer to Figure 2 and Figure 3 ,like Figure 2 and Figure 3 As shown, the solder strip and the solder point are directly connected, the difference is that the comparative example has no TSO film and no laser grooving, while the embodiment has a TSO film and laser grooving is used for the solder strip position.

[0053] Specifically, the test results are shown in Table 1 below.

[0054] Table 1 Performance differences between examples and comparative examples

[0055] Isc(A) Average Voc(V) Average FF(%) Average Eff(%) Comparative Example 8.707 0.750 86.06 25.55 Example 8.857 0.751 85.50 25.80

[0056] Among them, Isc is the short-circuit current, Voc is the open-circuit voltage, FF is the fill factor, and Eff is the efficiency. Since there are multiple metal electrodes on the battery, the average value is taken.

[0057] Specifically, by comparing the electrical properties, it is found that the efficiency of the embodiment is about 0.25% higher than that of the comparative example, and the main current is about 150 mA higher, which is related to the smaller shading area and larger light receiving area after the connecting wire is removed.

[0058] Specifically, the battery cells are made into modules, and the module power obtained in the embodiment is about 0.04W higher than that obtained in the comparative example.

[0059] In summary, the SHJ battery with a laminated coating structure and its preparation method utilize the high transmittance and low reflectivity of the TSO film to form an ITO / SiON laminated film structure, and achieve direct contact between the welding strip and the auxiliary grid through laser grooving in conjunction with the 0BB wire mesh technology. After providing a reinforcing block with a gap area, the connecting wire is eliminated, the shading area is reduced, the light receiving area is increased, the current of the HJT battery is increased, and ultimately the short-circuit current and efficiency are improved.

[0060] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A SHJ battery with a laminated coating structure, characterized in that: include: An N-type silicon substrate having a first surface and a second surface corresponding to the first surface; A front amorphous silicon layer, disposed on the first surface; An N-type doped layer, plated on the front amorphous silicon layer; A first ITO thin film layer, deposited on the N-type doped layer; A TSO film layer is stacked on the first ITO film layer to form an ITO / SiON laminated film structure; A first metal electrode is disposed on both sides of the TSO film layer to form a plurality of main grids; a back amorphous silicon layer, disposed on the second surface; A P-type doped layer is disposed on the back amorphous silicon layer to form a PN junction; A second ITO thin film layer, deposited on the P-type doped layer; The second metal electrodes are arranged on both sides of the first ITO film layer to form a plurality of main grids.

2. The SHJ battery with a laminated coating structure as claimed in claim 1, characterized in that: A reinforcement block is provided on the first metal electrode and the second metal electrode; There is a gap area between the reinforcement blocks arranged adjacent to each other on both sides.

3. The SHJ battery with a laminated coating structure as claimed in claim 2, characterized in that: The size of the reinforcement block is 0.6-1mm*0.1-0.4mm.

4. The SHJ battery with a laminated coating structure as claimed in claim 2, characterized in that: The width of the gap area is 0.8-1.5 cm.

5. The SHJ battery with a laminated coating structure as claimed in claim 1, characterized in that: The thickness of the N-type silicon substrate is 110-130 μm; The thickness of the front amorphous silicon layer is 3-6 nm; The thickness of the back amorphous silicon layer is 3-6 nm.

6. The SHJ battery with a laminated coating structure as claimed in claim 1, characterized in that: The thickness of the N-type doping layer is 20-30 nm; The thickness of the P-type doping layer is 20-30 nm.

7. The SHJ battery with a laminated coating structure as claimed in claim 1, characterized in that: The thickness of the first ITO thin film layer is 60-80nm; The thickness of the second ITO thin film layer is 80-100 nm.

8. The SHJ battery with a laminated coating structure as claimed in claim 1, characterized in that: The thickness of the TSO film layer is 20-40 nm.

9. The SHJ battery with a laminated coating structure as claimed in claim 1, characterized in that: The thickness of the first metal electrode and the second metal electrode is 10-20 μm.

10. A method for preparing a SHJ battery having a laminated coating structure according to any one of claims 1 to 9, characterized in that: The steps include: Step S1, double-sided polishing of an N-type silicon substrate; Step S2, forming a front amorphous silicon layer and an N-type doped layer on the first surface of the N-type silicon substrate, and forming a back amorphous silicon layer and a P-type doped layer on the second surface of the N-type silicon substrate; Step S3, depositing a first ITO thin film layer and a second ITO thin film layer on the N-type doped layer and the P-type doped layer respectively; Step S4, stacking a TSO film layer on the first ITO film layer to form an ITO / SiON laminated film structure; Step S5, opening a number of small holes of 0.6-1mm*0.1*0.4mm on the large stencil at positions corresponding to the silicon wafer, printing the silver paste onto the silicon wafer through the small holes, and drying and hardening to obtain metal electrodes; wherein The metal electrode is provided with a reinforcement block.

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