TOPCon battery and preparation method thereof

Abstract

The invention belongs to the technical field of battery preparation, and particularly relates to a TOPCon battery and a preparation method thereof, and the method comprises the steps: carrying out the texturing of a silicon wafer; plating SiOx masks on the two surfaces of the textured silicon wafer; performing SiOx ablation on the silicon wafer plated with the mask by using micro laser, obtaining a grid line contact area on the front surface of the silicon wafer plated with the SiOx mask, and then polishing the grid line contact area by using alkali liquor to obtain a polished structure of the grid line contact area; preparing a boron-doped layer on the front surface of the silicon wafer, and then polishing; depositing a tunneling oxide layer, a doped polycrystalline silicon layer and a phosphorus-doped layer on the back surface of the silicon wafer, and then removing Poly winding plating and cleaning on the back surface of the silicon wafer; a passivation film layer and an anti-reflection film layer are deposited on the front face and the back face of a silicon wafer respectively after cleaning, and then a front face metal electrode and a back face metal electrode are prepared on the front face anti-reflection film layer and the back face anti-reflection film layer. According to the TOPCon battery prepared by the method, the complete planar structure of the contact area is lower in recombination, and the conversion efficiency of the battery is higher.

Description

Technical Field

[0001] The invention belongs to the technical field of battery preparation, and in particular relates to a TOPCon battery and a preparation method thereof. Background Art

[0002] According to the difference of silicon wafers, crystalline silicon cells can be divided into P-type cells and N-type cells. There is no essential difference in the power generation principle of the two cells, both of which are based on PN junction for photogenerated carrier separation. Among them, P-type cells diffuse phosphorus elements on P-type semiconductor materials to form n+ / p-type structure solar cells, which are P-type cells. The manufacturing process of P-type cells is relatively simple and the cost is low. At present, PERC cells are close to the theoretical limit efficiency. N-type cells inject boron elements on N-type semiconductor materials to form p+ / n-type structure solar cells, which are N-type cells. Compared with P-type cells, N-type cells have the advantages of high conversion efficiency, high bifaciality, low temperature coefficient, no light decay, good weak light effect, and longer carrier life.

[0003] The current technologies of N-type cells include TOPCon (tunneling oxide passivation contact), HJT (Heterojunction with Intrinsic Thin-layer), and XBC (cross-back contact cell). Among them, TOPCon stands out among N-type technologies due to its outstanding economic and cost-effective advantages in the short term, and large-scale production capacity is the first to be implemented.

[0004] Among N-type battery technologies, TOPCon technology has developed extremely rapidly. TOPCon batteries use wet technology to prepare the front side into a textured structure with a reflectivity of less than 15%, which is of great help to improve the current, but it will also bring many defects on the surface of the silicon wafer. For example, the current texturing process is to uniformly texturize the surface of the silicon wafer, so that a pyramid velvet surface is formed on the front side of the silicon wafer and a flat surface is formed on the back side. The velvet structure formed in the gate line contact area and the non-contact area is the same, which causes problems in the contact between the gate line and the emitter, which is not conducive to the charge transfer of the gate line part and the excellent contact between the gate line and the silicon wafer. The unevenness of the pyramid will affect the aspect ratio and continuity of the gate line. The bottom of the pyramid often has voids in contact with the gate line, which affects the filling factor. The pyramid structure of the velvet surface also affects the battery passivation, thereby limiting the further improvement of the battery conversion efficiency.

[0005] At present, there are other inventions (application number CN202310103241.8) that change the grain orientation of the heavily doped area by laser etching the heavily doped area under the gate line of the silicon wafer, and laser etch the heavily doped area of ​​the silicon wafer before texturing to form a mixed velvet structure similar to the polished surface + texturing surface. It forms a regular and dense pyramid morphology in the non-contact area, improves the light absorption of the battery, and then improves the short-circuit current and fill factor of the battery, and improves the conversion efficiency of the battery. This method forms a mixed velvet structure under the gate line, and the contact area is still relatively large. In addition, this method uses laser to change the lattice structure of the silicon substrate, which causes greater damage.

[0006] In view of this, it is necessary to provide a TOPCon battery that forms a differentiated velvet structure in the gate line contact area and non-contact area on the silicon wafer surface to meet the requirements of low damage and surface passivation, give full play to the advantages of different areas, and effectively improve the conversion efficiency of the battery. Summary of the invention

[0007] Based on this, the purpose of the present invention is to provide a TOPCon battery and a preparation method thereof, which has solved the problem of low conversion efficiency of TOPCon batteries in the prior art.

[0008] To achieve the above object, the present invention adopts the following technical solution.

[0009] The present invention provides a method for preparing a TOPCon battery, comprising:

[0010] Step 1: Texturing the silicon wafer;

[0011] Step 2: coating the silicon wafer treated in step 1 with SiOx mask on both sides to obtain SiOx masked silicon wafer;

[0012] Step 3: using a micro laser to ablate SiOx on the silicon wafer processed in step 2, obtaining a gate line contact area on the front side of the SiOx-coated mask silicon wafer, and then using an alkaline solution to perform a first polishing on the gate line contact area to obtain a polished structure of the gate line contact area;

[0013] Step 4: After the processing in step 3, a boron-doped layer is prepared on the front side of the silicon wafer, and then the boron-doped layer is polished for a second time;

[0014] Step 5: After the treatment in step 4, a tunneling oxide layer and an intrinsic polysilicon layer are deposited on the back of the silicon wafer, a phosphorus-doped layer is prepared on the intrinsic polysilicon layer, and then the back of the silicon wafer is de-poly-plated and cleaned;

[0015] Step 6: After the processing in step 5, a passivation film layer and an anti-reflection film layer are deposited on the front and back sides of the silicon wafer respectively to form a front passivation film layer, a back passivation film layer and a front anti-reflection film layer, and a back anti-reflection film layer;

[0016] Step seven: printing AgAl paste on the front anti-reflection film layer and the back anti-reflection film layer, and forming a front metal electrode and a back metal electrode after sintering.

[0017] In the present invention, the SiOx mask on the surface of the silicon wafer after texturing can protect the texture structure of the non-contact area of ​​the silicon wafer when the silicon wafer is ablated and polished, and when micro-laser ablation is used, the SiOx mask can be well removed, and then local polishing is performed to form a complete planar structure in the contact area on the silicon wafer. Compared with the prior art, the micro-laser ablation provided in the present invention causes less lattice damage and less battery recombination, so that the charge transfer of the gate line part and the formation of excellent contact between the gate line and the silicon wafer make the recombination lower, thereby improving the conversion efficiency of the TOPCon battery, and the SiOx mask can largely avoid the influence of silicon wafer damage on the battery conversion rate.

[0018] In some embodiments, in step 2, the thickness of the SiOx mask is 40-120 nm.

[0019] In some embodiments, in step three, the parameters of the micro laser are: output power 10-70 W, pulse repetition frequency 5-20 kHz, laser spot diameter 5-15 Pm and laser beam speed 30-60 mm / s.

[0020] In some embodiments, in step 3, the first polishing is performed using an alkali solution, the alkali solution includes a KOH solution, a NaOH solution or an ammonia solution with a concentration of 3 to 8 wt%, and the polishing time is 100s to 500s. After alkali polishing, the contact area on the surface of the silicon wafer forms a polished structure, and the non-contact area maintains a velvet structure. The polishing time is controlled to be 100s to 500s, and the mask can be just removed.

[0021] In some embodiments, in step 4, the boron-doped layer is prepared by using BCl3 as a diffusion source and diffusing on the front side of the silicon wafer, the temperature of BCl3 diffusion is 800-1000°C, and the diffusion square resistance is controlled between 200-300Ω / SP. For example, the diffusion temperature is 800°C, 850°C, 900°C, 950°C or 1000°C, and the diffusion square resistance is controlled to be 200Ω / SP, 250Ω / SP or 300Ω / SP, so that the square resistance size and uniformity of the diffusion area on the silicon wafer meet the requirements for industrial use.

[0022] In some embodiments, in step 4, the second polishing is performed using an alkali solution, the alkali solution includes a KOH solution, a NaOH solution or an ammonia solution with a concentration of 3 to 8 wt%, and the polishing time is 100 s to 500 s. For example, the concentration of the alkali solution is 3 wt%, 4 wt%, 5 wt%, 6 wt%, 7 wt% or 8 wt%; the time is 100 s, 150 s, 200 s, 250 s, 300 s, 350 s, 400 s or 450 s, so that the polishing time is within a suitable range, thereby ensuring the polishing effect and ensuring that the SiOx mask is just removed during this process.

[0023] In some embodiments, in step 5, the thickness of the tunnel oxide layer is 1-3 nm. For example, the thickness of the tunnel oxide layer is 1 nm, 2 nm or 3 nm.

[0024] In some embodiments, in step 5, the thickness of the intrinsic polysilicon layer is 50-150 nm. For example, the thickness of the intrinsic polysilicon film is 50 nm, 100 nm, or 150 nm.

[0025] In some embodiments, in step 5, the phosphorus-doped layer is prepared by diffusing the intrinsic polysilicon layer with POCl3 as a diffusion source, the diffusion temperature of POCl3 is 800-900°C, and the doping concentration is 1-5E20cm -3 For example, the diffusion temperature is 800℃, 820℃, 850℃, 850℃, 900℃; the doping concentration is 1E20cm -3 、2E20cm -3 、3E20cm -3 、4E20cm -3 、5E20cm -3 , in order to form a uniform, high-quality pn junction on the surface of the silicon wafer.

[0026] In some embodiments, in step 5, removing the poly wrap and cleaning includes:

[0027] Step 1: Use HF / H2O to remove the BSG on the front side;

[0028] Step 2: Use NH3 / H2O2 to remove the Poly-Si on the front side;

[0029] Step 3: Use HF / H2O to remove PSG on the front and BSG on the back;

[0030] Among them, the HF / H2O mass fraction in the first step is 5wt%~12wt%; the NH3 / H2O2 volume ratio in the second step is 1:1:5~1:2:7; the HF / H2O mass fraction in the third step is 3wt%~10wt%. These three cleaning solutions are used for de-plating and cleaning silicon wafers.

[0031] In some embodiments, in step six, the thickness of the front passivation film layer and the back passivation film layer is 30 nm to 90 nm; the thickness of the front anti-reflection film layer and the back anti-reflection film layer are both 10 nm to 50 nm.

[0032] In some embodiments, the front passivation film layer is an AlOx film layer and a SiNx film layer, and the back passivation film layer is a SiNx film layer; the front anti-reflection film layer is a SiONx film layer, and the back anti-reflection film layer is a SiNx film layer.

[0033] In some embodiments, the thickness of the AlOx film layer is 3-10 nm; the thickness of the SiNx film layer is 10-80 nm.

[0034] The present invention also provides a TOPCon battery prepared by the method.

[0035] In some embodiments, the TOPCon cell includes: a silicon wafer substrate layer, whose front side includes, from the inside to the outside, a boron-doped layer, a front passivation film layer, a front anti-reflection film layer and a front metal electrode; and whose back side includes, from the inside to the outside, a tunneling oxide layer, a doped polysilicon layer, a back passivation film layer, a back anti-reflection film layer and a back metal electrode.

[0036] Based on the technical solution of the present invention, compared with the prior art, the present invention has the following beneficial effects:

[0037] In the TOPCon battery preparation method provided by the present invention, the entire surface is firstly textured and then partially polished. Specifically, the texture is performed by low-concentration alkali solution, and then a SiOx mask is deposited by PECVD. Then, the contact area is opened by a micro-laser method. Compared with the prior art, the SiOx mask can protect the texture structure of the non-contact area of ​​the silicon wafer when the silicon wafer is ablated and polished, and the SiOx mask can be well removed when micro-laser ablation is used. At the same time, micro-laser ablation causes less lattice damage and less battery recombination, and the micro-laser can better remove the SiOx mask. Then, a high-concentration alkali solution is used to polish the contact area, so that a completely planar structure can be formed in the contact area on the silicon wafer. At the same time, the SiOx mask can be better removed, so that the charge transfer of the gate line part and the excellent contact between the gate line and the silicon wafer are achieved, and the battery recombination is smaller. Compared with the prior art, its conversion efficiency is higher.

[0038] In the present invention, the silicon wafer is mainly textured with a low-concentration alkali solution, and then a SiOx mask is deposited using PECVD. After that, the contact area is opened by a micro-laser method. Only the existing SiOx mask is ablated. The laser causes less damage to the silicon wafer, which can largely avoid the impact of the damage to the silicon wafer on the battery conversion rate.

[0039] In the present invention, in view of the fact that the mixed-grain structure has relatively stringent requirements for the conditions of wet-graining with alkali solution, a method of first making full-graining, opening a window with laser, and partially polishing the grid line contact area is adopted, so that the completely planar structure condition of the contact area is easier to achieve and the window is larger. In the process of polishing the contact area, the SiOx mask is removed at the same time, making the battery preparation process simpler.

[0040] In the present invention, the TOPCon battery preparation method provided by the present invention forms more uniform pyramids on the surface of the silicon wafer, while maintaining improved fill factor and short-circuit current of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is the TOPCon battery preparation flow chart.

[0042] Figure 2 This is a schematic diagram of the TOPCon battery structure.

[0043] Reference numerals:

[0044] 1-silicon wafer substrate layer, 2-boron doped layer, 3-front passivation film layer, 4-front anti-reflection film layer, 5-front metal electrode, 6-tunneling oxide layer, 7-doped polysilicon layer, 8-back passivation film layer, 9-back anti-reflection film layer, 10-back metal electrode. DETAILED DESCRIPTION

[0045] The experimental methods in the following examples of the present invention without specifying specific conditions are usually carried out under conventional conditions or under conditions recommended by the manufacturers.

[0046] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0047] The terms "including" and "having" and any variations thereof of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, device, product or equipment comprising a series of steps is not limited to the listed steps or modules, but may optionally include steps not listed, or may optionally include other steps inherent to these processes, methods, products or equipment.

[0048] In the present invention, the term "multiple" refers to two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0049] The following describes the invention in conjunction with specific embodiments.

[0050] Example 1: A method for preparing a TOPCon battery

[0051] A method for preparing a TOPCon battery (process flow chart as shown in Figure 1 As shown), specifically comprising the following steps:

[0052] S1 texturing: Use low-concentration alkaline solution etching to form a pyramid structure of uniform size on both sides of a single crystal silicon wafer (N-type single crystal silicon wafer, resistivity range of 0.9*10^-4~7.5*10^-4 / (Ω*m), thickness of 145μm, size of 182*183.75mm); the low-concentration alkaline solution is controlled at 2wt%, the texturing time is controlled at 500s, the texturing temperature is controlled at 70℃, and the height is 1.2μm.

[0053] S2 plating mask: PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to coat SiOx film on both sides of the silicon wafer after texturing, and the thickness of the SiOx film is 80nm.

[0054] S3 micro-laser film opening: Use laser to ablate SiOx on the front side of the silicon wafer, and the laser pattern is the front screen grid pattern; the laser parameters are set as follows: output power 40W, pulse repetition frequency 15kHz, laser spot diameter 10Pm and laser beam speed 40mm / s.

[0055] S4 alkali polishing: polish the contact area with high concentration alkali solution and remove the SiOx film at the same time; the high concentration alkali solution is controlled at 5wt%, the alkali polishing temperature is controlled at 65°C, and the polishing time is controlled at 300s, so that the polishing time is within a suitable range, thereby ensuring the polishing effect. In the embodiment, the alkaline solution is a KOH solution.

[0056] S5 Boron Diffusion: Use BCl3 as the diffusion source to diffuse on the front side of the silicon wafer. The diffusion temperature is 900℃ and the diffusion square resistance is controlled between 250Ω / SP.

[0057] S6 polishing: polish the front side with high concentration alkali solution; the high concentration alkali solution is controlled at 6wt%, the alkali polishing temperature is controlled at 65°C, and the polishing time is controlled at 250s.

[0058] S7 deposits tunnel oxide layer and intrinsic polysilicon layer: using LPCVD (Low Pressure Chemical Vapor Deposition) technology, deposits a tunnel oxide layer with a thickness of 2nm on the back of the silicon wafer; and continues to deposit an intrinsic polysilicon film with a thickness of 80nm on the surface of the tunnel oxide layer.

[0059] S8 Phosphorus diffusion: Phosphorus diffusion is performed on the intrinsic polysilicon layer using POCl3 as the diffusion source. The diffusion temperature is 850°C and the doping concentration is 3E20cm -3 .

[0060] S9 Poly wrapping removal and cleaning: Use high concentration HF to remove the back wrapping; Step 1: Use HF / H2O to remove the BSG expanded on the front side, Step 2: Use NH3 / H2O2 to remove the Poly-Si expanded on the front side; Step 3: Use HF / H2O to remove the PSG on the front side and the BSG on the back side; The HF / H2O mass fraction in the first step is 8wt%; The volume ratio of NH3 / H2O2 in the second step is 1:1:6; The HF / H2O mass fraction in the third step is 6wt%.

[0061] S10 Deposition of passivation film and anti-reflection film: A layer of AlOx film is deposited on the boron-doped surface by ALD (Atom Layer Deposition), and the thickness of the AlOx film is 5nm; a SiNx film is deposited on the AlOx film by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the SiNx film is 70nm. The AlOx film and the SiNx film form a front passivation film. A SiNx film is deposited on the back of the silicon wafer by PECVD, and the thickness of the SiNx film is 70nm, forming a back passivation film.

[0062] A SiONx film layer is deposited on the front passivation film layer by PECVD, and the thickness of the SiONx film layer is 10nm to form a front anti-reflection film layer. A SiNx film layer is deposited on the back passivation film layer by PECVD to form a back anti-reflection film layer, and the thickness of the back SiNx film layer is 20nm.

[0063] S11 printing: AgAl paste is printed on the front and back sides of the silicon wafer, and the front and back metal electrodes are formed after sintering.

[0064] The schematic diagram of the structure of the TOPCon battery prepared by the above-mentioned TOPCon battery preparation method is as follows Figure 2The TOPCon cell prepared by the method of this embodiment includes a silicon wafer substrate layer 1, a boron doped layer 2, a front passivation film layer 3, a front anti-reflection film layer 4 and a front metal electrode 5 on the front side from the inside to the outside; and a tunnel oxide layer 6, a doped polysilicon layer 7, a back passivation film layer 8, a back anti-reflection film layer 9 and a back metal electrode 10 on the back side from the inside to the outside.

[0065] Example 2: A method for preparing a TOPCon battery

[0066] A method for preparing a TOPCon battery (process flow chart as shown in Figure 1 As shown), specifically comprising the following steps:

[0067] S1 texturing: Use low-concentration alkaline solution etching to form a pyramid structure of uniform size on both sides of a single crystal silicon wafer (N-type single crystal silicon wafer, resistivity range is 0.9*10^-4~7.5*10^-4 / (Ω*m), thickness is 145μm, size is 182*183.75mm); the low-concentration alkaline solution is controlled at 1wt%, the texturing time is controlled at 500s, the texturing temperature is controlled at 70℃, and the height is 1.2μm.

[0068] S2 plating mask: PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to coat SiOx film on both sides of the silicon wafer after texturing, and the thickness of the SiOx film is 40nm.

[0069] S3 micro-laser film opening: Use laser to ablate SiOx on the front side of silicon wafer, and the laser pattern is the front screen grid pattern; the laser parameters are set as follows: output power 10W, pulse repetition frequency 5kHz, laser spot diameter 5Pm and laser beam speed 30mm / s. Due to the presence of SiOx film layer (SiOx mask), the damage to silicon wafer can be greatly reduced during ablation, and the grid pattern can be formed.

[0070] S4 alkali polishing: polish the contact area with high concentration alkali solution and remove the SiOx film at the same time; the high concentration alkali solution is controlled at 3wt% and the polishing time is controlled at 500s, so that the polishing time is within a suitable range, thereby ensuring the polishing effect. After alkali polishing, the contact area on the surface of the silicon wafer forms a polished structure, and the non-contact area maintains a velvet structure. In this embodiment, the alkaline solution is a NaOH solution.

[0071] S5 Boron Diffusion: Use BCl3 as the diffusion source to diffuse on the front side of the silicon wafer. The diffusion temperature is 800℃ and the diffusion square resistance is controlled at 200Ω / SP.

[0072] S6 Polishing: Polishing the front side with a high concentration of alkaline solution; the high concentration of alkaline solution is controlled at 3wt%, and the polishing time is controlled at 500s. In this embodiment, the alkaline solution is a NaOH solution.

[0073] S7 deposits tunnel oxide layer and intrinsic polysilicon layer: using LPCVD (Low Pressure Chemical Vapor Deposition) technology, deposits a tunnel oxide layer with a thickness of 1 nm on the back of the silicon wafer; and continues to deposit an intrinsic polysilicon film with a thickness of 50 nm on the surface of the tunnel oxide layer.

[0074] S8 Phosphorus diffusion: Phosphorus diffusion is performed on the intrinsic polysilicon layer using POCl3 as the diffusion source. The diffusion temperature is 800°C and the doping concentration is 1E20cm -3 .

[0075] S9 Poly wrapping removal and cleaning: Use high concentration HF to remove the back wrapping; Step 1: Use HF / H2O to remove the BSG expanded on the front side, Step 2: Use NH3 / H2O2 to remove the Poly-Si expanded on the front side; Step 3: Use HF / H2O to remove the PSG on the front side and the BSG on the back side; The HF / H2O mass fraction in the first step is 8wt%; The volume ratio of NH3 / H2O2 in the second step is 1:1:6; The HF / H2O mass fraction in the third step is 6wt%.

[0076] S10 Deposition of passivation film and anti-reflection film: A layer of AlOx film is deposited on the boron-doped surface by ALD (Atom Layer Deposition), and the thickness of the AlOx film is 5nm; a SiNx film is deposited on the AlOx film by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the SiNx film is 70nm. The AlOx film and the SiNx film form a front passivation film. A SiNx film is deposited on the back of the silicon wafer by PECVD, and the thickness of the SiNx film is 70nm, forming a back passivation film.

[0077] A SiONx film layer is deposited on the front passivation film layer by PECVD, and the thickness of the SiONx film layer is 10nm to form a front anti-reflection film layer. A SiNx film layer is deposited on the back passivation film layer by PECVD to form a back anti-reflection film layer, and the thickness of the back SiNx film layer is 20nm.

[0078] S11 printing: AgAl paste is printed on the front and back sides of the silicon wafer, and the front and back metal electrodes are formed after sintering.

[0079] Example 3: A method for preparing a TOPCon battery

[0080] A method for preparing a TOPCon battery (process flow chart as shown in Figure 1 As shown), specifically comprising the following steps:

[0081] S1 texturing: Use low-concentration alkaline solution etching to form a pyramid structure of uniform size on both sides of a single crystal silicon wafer (N-type single crystal silicon wafer, resistivity range of 0.9*10^-4~7.5*10^-4 / (Ω*m), thickness of 145μm, size of 182*183.75mm); the low-concentration alkaline solution is controlled at 3wt%, the texturing time is controlled at 500s, the texturing temperature is controlled at 70℃, and the height is 1.2μm.

[0082] S2 plating mask: PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to coat SiOx film on both sides of the textured silicon wafer, and the thickness of the SiOx film is 120nm.

[0083] S3 micro-laser film opening: Use laser to ablate SiOx on the front of silicon wafer, and the laser pattern is the front screen grid pattern; the laser parameters are set as follows: output power 70W, pulse repetition frequency 20kHz, laser spot diameter 15Pm and laser beam speed 60mm / s. Due to the presence of SiOx film layer (SiOx mask), the damage to silicon wafer can be greatly reduced during ablation, and the grid pattern can be formed.

[0084] S4 alkali polishing: polish the contact area with high concentration alkali solution and remove the SiOx film at the same time; the high concentration alkali solution is controlled at 8wt% and the polishing time is controlled at 100s, so that the polishing time is within a suitable range, thereby ensuring the polishing effect. After alkali polishing, the contact area on the surface of the silicon wafer forms a polished structure, and the non-contact area maintains a velvet structure. In this embodiment, the alkaline solution is ammonia water.

[0085] S5 Boron Diffusion: Use BCl3 as the diffusion source to diffuse on the front side of the silicon wafer. The diffusion temperature is 1000℃ and the diffusion square resistance is controlled at 300Ω / SP.

[0086] S6 Polishing: Polishing the front side with a high concentration of alkaline solution; the high concentration of alkaline solution is controlled at 8wt%, and the polishing time is controlled at 100s. In this embodiment, the alkaline solution is ammonia water.

[0087] S7 deposits tunnel oxide layer and intrinsic polysilicon layer: using LPCVD (Low Pressure Chemical Vapor Deposition) technology, deposits a tunnel oxide layer with a thickness of 3nm on the back of the silicon wafer; and continues to deposit an intrinsic polysilicon film with a thickness of 150nm on the surface of the tunnel oxide layer.

[0088] S8 Phosphorus diffusion: Phosphorus diffusion is performed on the intrinsic polysilicon layer using POCl3 as the diffusion source. The diffusion temperature is 900°C and the doping concentration is 5E20cm -3 .

[0089] S9 Poly wrapping removal and cleaning: Use high concentration HF to remove the back wrapping; Step 1: Use HF / H2O to remove the BSG expanded on the front side, Step 2: Use NH3 / H2O2 to remove the Poly-Si expanded on the front side; Step 3: Use HF / H2O to remove the PSG on the front side and the BSG on the back side; The HF / H2O mass fraction in the first step is 8wt%; The volume ratio of NH3 / H2O2 in the second step is 1:1:6; The HF / H2O mass fraction in the third step is 6wt%.

[0090] S10 Deposition of passivation film and anti-reflection film: A layer of AlOx film is deposited on the boron-doped surface by ALD (Atom Layer Deposition), and the thickness of the AlOx film is 5nm; a SiNx film is deposited on the AlOx film by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the SiNx film is 70nm. The AlOx film and the SiNx film form a front passivation film. A SiNx film is deposited on the back of the silicon wafer by PECVD, and the thickness of the SiNx film is 70nm, forming a back passivation film.

[0091] A SiONx film layer is deposited on the front passivation film layer by PECVD, and the thickness of the SiONx film layer is 10nm to form a front anti-reflection film layer. A SiNx film layer is deposited on the back passivation film layer by PECVD to form a back anti-reflection film layer, and the thickness of the back SiNx film layer is 20nm.

[0092] S11 printing: AgAl paste is printed on the front and back sides of the silicon wafer, and the front and back metal electrodes are formed after sintering.

[0093] Example 4: A method for preparing a TOPCon battery

[0094] A method for preparing a TOPCon battery (process flow chart as shown in Figure 1 As shown), specifically comprising the following steps:

[0095] S1 texturing: Use low-concentration alkaline solution etching to form a pyramid structure of uniform size on both sides of a single crystal silicon wafer (N-type single crystal silicon wafer, resistivity range of 0.9*10^-4~7.5*10^-4 / (Ω*m), thickness of 145μm, size of 182*183.75mm); the low-concentration alkaline solution is controlled at 2wt%, the texturing time is controlled at 500s, the texturing temperature is controlled at 70℃, and the height is 1.2μm.

[0096] S2 plating mask: PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to coat SiOx film on both sides of the silicon wafer after texturing, and the thickness of the SiOx film is 60nm.

[0097] S3 micro-laser film opening: Use laser to ablate SiOx on the front of silicon wafer, and the laser pattern is the front screen grid pattern; the laser parameters are set as follows: output power 50W, pulse repetition frequency 10kHz, laser spot diameter 13Pm and laser beam speed 50mm / s. Due to the existence of SiOx film layer (SiOx mask), the damage to silicon wafer can be greatly reduced during ablation, and the grid pattern can be formed.

[0098] S4 alkali polishing: Use high concentration alkali solution to polish the non-contact area and remove the SiOx film at the same time; the high concentration alkali solution is controlled at 6wt%, and the polishing time is controlled at 200s, so that the polishing time is within a suitable range, thereby ensuring the polishing effect. After alkali polishing, the contact area on the surface of the silicon wafer forms a polishing structure, and the non-contact area maintains a velvet structure. In this embodiment, the alkaline solution is a KOH solution.

[0099] S5 Boron Diffusion: Use BCl3 as the diffusion source to diffuse on the front side of the silicon wafer. The diffusion temperature is 850℃ and the diffusion square resistance is controlled at 250Ω / SP.

[0100] S6 Polishing: Polishing the front side with a high concentration of alkaline solution; the high concentration of the alkaline solution is controlled at 7wt%, and the polishing time is controlled at 150s. In this embodiment, the alkaline solution is a KOH solution.

[0101] S7 deposits tunnel oxide layer and intrinsic polysilicon layer: using LPCVD (Low Pressure Chemical Vapor Deposition) technology, deposits a tunnel oxide layer with a thickness of 2nm on the back of the silicon wafer; and continues to deposit an intrinsic polysilicon film with a thickness of 100nm on the surface of the tunnel oxide layer.

[0102] S8 Phosphorus diffusion: Phosphorus is diffused into the intrinsic polysilicon layer using POCl3 as the diffusion source. The diffusion temperature is 820℃ and the doping concentration is 4E20cm -3 .

[0103] S9 Poly wrap removal and cleaning: Use high concentration HF to remove the back wrap; use HF / H2O2 and NH3 / H2O2 as cleaning solution to remove the wrap and clean the silicon wafer. Step 1: Use HF / H2O to remove the BSG on the front side, Step 2: Use NH3 / H2O2 to remove the Poly-Si on the front side; Step 3: Use HF / H2O to remove the PSG on the front side and the BSG on the back side; The mass fraction of HF / H2O in the first step is 8wt%; The volume ratio of NH3 / H2O2 in the second step is 1:1:6; The mass fraction of HF / H2O in the third step is 6wt%.

[0104] S10 Deposition of passivation film and anti-reflection film: A layer of AlOx film is deposited on the boron-doped surface by ALD (Atom Layer Deposition), and the thickness of the AlOx film is 5nm; a SiNx film is deposited on the AlOx film by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the SiNx film is 70nm. The AlOx film and the SiNx film form a front passivation film. A SiNx film is deposited on the back of the silicon wafer by PECVD, and the thickness of the SiNx film is 70nm, forming a back passivation film.

[0105] A SiONx film layer is deposited on the front passivation film layer by PECVD, and the thickness of the SiONx film layer is 10nm to form a front anti-reflection film layer. A SiNx film layer is deposited on the back passivation film layer by PECVD to form a back anti-reflection film layer, and the thickness of the back SiNx film layer is 20nm.

[0106] S11 printing: AgAl paste is printed on the front and back sides of the silicon wafer, and the front and back metal electrodes are formed after sintering.

[0107] Example 5: A method for preparing a TOPCon battery

[0108] A method for preparing a TOPCon battery (process flow chart as shown in Figure 1 As shown), specifically comprising the following steps:

[0109] S1 texturing: Use low-concentration alkaline solution etching to form a pyramid structure of uniform size on both sides of a single crystal silicon wafer (N-type single crystal silicon wafer, resistivity range is 0.9*10^-4~7.5*10^-4 / (Ω*m), thickness is 145μm, size is 182*183.75mm); the low-concentration alkaline solution is controlled at 1wt%, the texturing time is controlled at 500s, the texturing temperature is controlled at 70℃, and the height is 1.2μm.

[0110] S2 plating mask: PECVD (Plasma Enhanced Chemical Vapor Deposition) is used to coat SiOx film on both sides of the silicon wafer after texturing, and the thickness of the SiOx film is 70nm.

[0111] S3 micro-laser film opening: Use laser to ablate SiOx on the front of silicon wafer, and the laser pattern is the front screen grid pattern; the laser parameters are set as follows: output power 30W, pulse repetition frequency 12kHz, laser spot diameter 8Pm and laser beam speed 45mm / s. Due to the existence of SiOx film layer (SiOx mask), the damage to silicon wafer can be greatly reduced during ablation, and the grid pattern can be formed.

[0112] S4 alkali polishing: Use high concentration alkali solution to polish the non-contact area and remove the SiOx film at the same time; the high concentration alkali solution is controlled at 7wt%, and the polishing time is controlled at 400s, so that the polishing time is in a suitable range, thereby ensuring the polishing effect. After alkali polishing, the contact area on the surface of the silicon wafer forms a polishing structure, and the non-contact area maintains a velvet structure. In this embodiment, the alkaline solution is a KOH solution.

[0113] S5 Boron Diffusion: Use BCl3 as the diffusion source to diffuse on the front side of the silicon wafer. The diffusion temperature is 950°C and the diffusion square resistance is controlled at 250Ω / SP.

[0114] S6 Polishing: Polishing the front side with a high concentration of alkaline solution; the concentration of the high concentration of alkaline solution is controlled at 5wt%, and the polishing time is controlled at 350s. In this embodiment, the alkaline solution is a KOH solution.

[0115] S7 deposits tunnel oxide layer and intrinsic polysilicon layer: using LPCVD (Low Pressure Chemical Vapor Deposition) technology, deposits a tunnel oxide layer with a thickness of 2nm on the back of the silicon wafer; and continues to deposit an intrinsic polysilicon film with a thickness of 100nm on the surface of the tunnel oxide layer.

[0116] S8 Phosphorus diffusion: Phosphorus diffusion is performed on the intrinsic polysilicon layer using POCl3 as the diffusion source. The diffusion temperature is 850°C and the doping concentration is 2E20cm -3 .

[0117] S9 Poly wrapping removal and cleaning: Use high concentration HF to remove the back wrapping; Step 1: Use HF / H2O to remove the BSG expanded on the front side, Step 2: Use NH3 / H2O2 to remove the Poly-Si expanded on the front side; Step 3: Use HF / H2O to remove the PSG on the front side and the BSG on the back side; The HF / H2O mass fraction in the first step is 8wt%; The volume ratio of NH3 / H2O2 in the second step is 1:1:6; The HF / H2O mass fraction in the third step is 6wt%.

[0118] S10 Deposition of passivation film and anti-reflection film: A layer of AlOx film is deposited on the boron-doped surface by ALD (Atom Layer Deposition), and the thickness of the AlOx film is 5nm; a SiNx film is deposited on the AlOx film by PECVD (Plasma Enhanced Chemical Vapor Deposition), and the thickness of the SiNx film is 70nm. The AlOx film and the SiNx film form a front passivation film. A SiNx film is deposited on the back of the silicon wafer by PECVD, and the thickness of the SiNx film is 70nm, forming a back passivation film.

[0119] A SiONx film layer is deposited on the front passivation film layer by PECVD, and the thickness of the SiONx film layer is 10nm to form a front anti-reflection film layer. A SiNx film layer is deposited on the back passivation film layer by PECVD to form a back anti-reflection film layer, and the thickness of the back SiNx film layer is 20nm.

[0120] S11 printing: AgAl paste is printed on the front and back sides of the silicon wafer, and the front and back metal electrodes are formed after sintering.

[0121] Comparative Example 1

[0122] Compared with Example 1, the difference in the preparation method of Comparative Example 1 is that the S5 boron diffusion step is directly performed on the front side of the silicon wafer after the S1 texturing step, and the rest of the methods are the same.

[0123] Comparative Example 2

[0124] Compared with Example 1, the difference in the preparation method of Comparative Example 2 is that the contact area is first etched with a common laser, and then S1 is used for texturing, replacing steps S1-S4 in Example 1, and the rest of the methods are the same.

[0125] The conditions of ordinary laser etching are: output power 70W, laser spot diameter 20μm and laser beam speed 2500mm / s, and repetition frequency is 130KHz.

[0126] Comparative Example 3

[0127] Compared with Example 1, the difference in the preparation method is that in step S2, the thickness of the mask is 130 nm, and the remaining steps are the same as in Example 1.

[0128] Comparative Example 4

[0129] Comparative Example Compared with Example 1, the difference in the preparation method is that in step S4, the polishing time is 600s and the concentration of the alkali solution is 10wt%.

[0130] Comparative Example 5

[0131] Comparative Example Compared with Example 1, the difference in the preparation method is that in S3, the parameters of the laser are set as follows: output power 80W, pulse repetition frequency 30kHz, laser spot diameter 20Pm and laser beam speed 70mm / s.

[0132] TOPCon batteries were prepared using the preparation methods provided in Examples 1 to 5 and Comparative Examples 1 to 5, and the performance of the TOPCon batteries was measured. The results are shown in Table 1.

[0133] Table 1 Test results of battery performance of Examples 1 to 5 and Comparative Examples 1 to 5

[0134] Preparation method Eta(%) Uoc(V) Isc(A) FF(%) RserDf(Ohm) RshuntDf(Ohm) Example 1 26.25 0.7345 14.130 85.60 0.0010 3563 Example 2 25.90 0.7369 13.964 85.18 0.0009 3695 Example 3 26.37 0.7347 14.269 85.14 0.0009 3911 Example 4 25.97 0.7436 13.989 84.36 0.0010 3602 Example 5 25.69 0.7348 13.809 84.11 0.0010 3600 Comparative Example 1 25.19 0.7381 13.874 83.16 0.0016 3915 Comparative Example 2 25.25 0.7349 13.980 83.19 0.0013 3680 Comparative Example 3 21.31 0.7178 12.098 83.09 0.0019 2198 Comparative Example 4 23.32 0.7321 12.980 83.11 0.0023 3650 Comparative Example 5 23.15 0.7359 12.983 82.01 0.0042 2306

[0135] Note: In the table, Eta (efficiency) indicates the ratio of solar energy converted into electrical energy by the cell; Uoc indicates open circuit voltage; Isc indicates short circuit current; FF indicates fill factor; RserDf indicates series resistance; and RshuntDf indicates parallel resistance.

[0136] As shown in Table 1, the solar cells prepared by the methods provided in Examples 1 to 5 have higher efficiencies than those in Comparative Examples 1 to 4, among which the solar cells prepared by the methods provided in the Examples have the best conversion efficiency, and their Isc and FF are both the highest. It can be seen that the methods provided in Examples 1 to 5 of the present invention can all produce solar cells with higher conversion efficiency.

[0137] As shown in Table 1, compared with Example 1, Comparative Example 1 does not have a mask coating step, and the Eta, Isc, FF, and RshuntDf of the prepared battery are all lower than those of Example 1. It can be seen that coating before micro-laser ablation and alkali polishing can protect the velvet surface of the non-contact area on the surface of the silicon wafer, so that the surface of the silicon wafer forms better velvet and non-velvet areas, thereby improving the light absorption of the battery, and then improving the short-circuit current and fill factor of the battery, and improving the conversion efficiency of the battery.

[0138] As shown in Table 1, when ordinary laser is used to etch the contact area and then texturing is used to prepare the mixed texture structure on the surface of the silicon wafer, the Eta, Isc and FF of the obtained cell are lower than those of the cell obtained by the method of Example 1. It can be seen that laser lattice change and then texturing will cause greater damage to the silicon wafer and affect the cell conversion efficiency.

[0139] In the process of preparing solar cells, when the thickness of the mask in S2 is greater than 120 nm, its Eta, Uoc, Isc, FF, and RshuntDf values ​​are significantly lower than those in Example 1. It can be seen that a mask that is too thick is not conducive to the subsequent micro-laser processing of the contact area of ​​the silicon wafer, resulting in poor contact between the emitter and the gate line, and poor passivation in the non-contact area.

[0140] In the process of preparing solar cells, when the concentration of the alkali solution is higher than 8wt% and the texturing time exceeds 500s, the Eta, Uoc, Isc and FF values ​​of the prepared cells are lower than those in Example 1. It can be seen that if the polishing time is too long and the alkali concentration is too high, the protection of the mask on the non-contact area will fail, which will lead to a decrease in current, opening voltage and filling, affecting the cell efficiency.

[0141] During the preparation of solar cells, when the power and frequency parameters of the laser changed, the parameters such as RserDf and opening voltage of the solar cell changed significantly, indicating that the laser parameters were too high, which increased the damage inside the silicon wafer and affected the passivation of the silicon wafer, thereby reducing the conversion rate of the solar cell.

[0142] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a TOPCon battery, characterized in that: include: Step 1: Texturing the silicon wafer; Step 2: Coat SiO on both sides of the silicon wafer treated in step 1 x Mask, get SiO x Mask silicon wafer; Step 3: Use micro laser to ablate SiOx on the silicon wafer treated in step 2. x A gate line contact area is obtained on the front side of the mask silicon wafer, and then the gate line contact area is first polished using an alkaline solution to obtain a polished structure of the gate line contact area; Step 4: After the processing in step 3, a boron-doped layer is prepared on the front side of the silicon wafer, and then the boron-doped layer is polished for a second time; Step 5: After the treatment in step 4, a tunneling oxide layer and an intrinsic polysilicon layer are deposited on the back of the silicon wafer, a phosphorus-doped layer is prepared on the intrinsic polysilicon layer, and then the back of the silicon wafer is de-poly-plated and cleaned; Step 6: After the processing in step 5, a passivation film layer and an anti-reflection film layer are deposited on the front and back sides of the silicon wafer respectively to form a front passivation film layer, a back passivation film layer and a front anti-reflection film layer, and a back anti-reflection film layer; Step seven: printing AgAl paste on the front anti-reflection film layer and the back anti-reflection film layer, and forming a front metal electrode and a back metal electrode after sintering.

2. The preparation method according to claim 1, characterized in that In step 2, SiO x The thickness of the mask is 40 to 120 nm.

3. The preparation method according to claim 1, characterized in that: In step 3, the parameters of the micro laser are: output power 10-70W, pulse repetition frequency 5-20kHz, laser spot diameter 5-15Pm and laser beam speed 30-60mm / s; The first polishing is performed using an alkali solution, which includes a KOH solution, a NaOH solution or an ammonia solution with a concentration of 3 to 8 wt %, and the polishing time is 100 s to 500 s.

4. The preparation method according to claim 1, characterized in that: In step 4, the second polishing is performed using an alkali solution, the alkali solution includes a KOH solution, a NaOH solution or an ammonia solution with a concentration of 3 to 8 wt%, and the polishing time is 100 s to 500 s.

5. The preparation method according to claim 1, characterized in that: In step five, the thickness of the tunnel oxide layer is 1-3 nm.

6. The preparation method according to claim 1, characterized in that: In step five, the thickness of the intrinsic polysilicon layer is 50-150 nm.

7. The preparation method according to claim 1, characterized in that: In step six, the thickness of the front passivation film layer is 30-90 nm, and the thickness of the back passivation film layer is 30-90 nm; the thickness of the front anti-reflection film layer and the back anti-reflection film layer are both 10-50 nm.

8. The preparation method according to claim 7, characterized in that: The front passivation film layer is a double-layer film of AlOx and SiNx, and the back passivation film layer is a SiNx film layer; the front anti-reflection film layer is a SiONx film layer, and the back anti-reflection film layer is a SiNx film layer.

9. A TOPCon battery prepared by the preparation method according to any one of claims 1 to 8.

10. The TOPCon battery according to claim 9, characterized in that include: A silicon wafer substrate layer (1) has a front side which, from the inside to the outside, comprises a boron doped layer (2), a front side passivation film layer (3), a front side anti-reflection film layer (4) and a front side metal electrode (5); and a back side which, from the inside to the outside, comprises a tunneling oxide layer (6), a doped polysilicon layer (7), a back side passivation film layer (8), a back side anti-reflection film layer (9) and a back side metal electrode (10).

Images