Preparation method of solar cell and solar cell

Abstract

The invention discloses a preparation method of a solar cell and the solar cell, and belongs to the photovoltaic field. The preparation method of the solar cell comprises the following steps: forming an alkali-resistant film layer on the front surface of a silicon substrate; forming a first tunneling layer and a first doping layer on the back surface of the silicon substrate; removing the first doping layer, the first tunneling layer and a part of the silicon substrate outside the first region; forming a second tunneling layer and a second doping layer on the back surface, wherein the doping types of the second doping layer and the first doping layer are opposite; removing the second doping layer, the second tunneling layer and a part of the silicon substrate outside the second region; removing the mask layer; and forming a first electrode in contact with the first doped layer in the first region, and forming a second electrode in contact with the second doped layer in the second region. According to the invention, the mask layer protects the front surface in the subsequent polishing process and the like, so that a thinner original silicon wafer can be selected, the two doping layers can be accurately divided and isolated on the back surface, and the purposes of reducing the cost, improving the process yield and improving the cell performance are achieved.

Description

Technical Field

[0001] The present invention relates to the photovoltaic field, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] As the core product of the photovoltaic industry, crystalline silicon solar cells have made continuous progress in recent years in improving photoelectric conversion efficiency, reducing manufacturing costs and improving reliability. With the evolution of technology, from traditional PERC (Passivated Emitter and Rear Cell) cells, TOPCon (Tunnel Oxide Passivated Contact, tunnel oxide layer doped polysilicon) cells to various structurally optimized back contact (BC) cell solutions, they have become the focus of research and industrialization in the industry.

[0003] Among them, the BC battery is a P-type semiconductor structure and an N-type semiconductor structure prepared at intervals on the back of the battery, and the first electrode and the second electrode are formed on them respectively. The positive and negative electrodes of the BC battery are both on the back of the battery, and there is no metal electrode shading on the front, which avoids the metal electrode shading loss, greatly improves the optical absorption of the battery, and achieves a good short-circuit current density; and the BC battery eliminates the front surface emitter, and the front surface recombination loss is reduced.

[0004] TOPCon cells deposit a 1nm to 2nm tunneling layer on the back of the silicon substrate, and then deposit a layer of doped polysilicon. The two together form a passivation contact structure, providing good interface passivation for the back of the silicon substrate. The ultra-thin oxide layer allows electrons to tunnel into the polysilicon layer while blocking the transmission of holes, reducing the recombination current. The lateral transmission characteristics of the doped layer reduce the series resistance. The above two characteristics together improve the open circuit voltage, fill factor and conversion efficiency of solar cells.

[0005] The TOPCon cell is combined with the back BC cell to form a TBC (TOPCon-Back Contact) cell, which fully integrates the advantages of both and is expected to achieve the goal of further improving the photoelectric conversion efficiency and overall cell performance. In practical applications, the high-efficiency and low-cost TBC cell helps reduce component costs and increase power generation revenue in distributed power generation systems and large-scale photovoltaic power stations.

[0006] The inventors found that although the TBC battery integrates the advantages of TOPCon and BC technologies, the existing technology still faces several difficulties. If the patterned P and N regions are directly formed on the back of the silicon substrate, high process precision is required, otherwise it is easy for the P and N regions to be connected at a certain point and leakage occurs. If the traditional TOPCon technology is used to prepare the back structure, it will face multiple double-sided alkaline etching and cleaning to control the quality of the battery and reduce the defect density. The process is bound to have high requirements for the thickness of the silicon wafer. Too thick silicon wafers not only increase material costs, but also indirectly limit the mass production scale and market competitiveness of the battery. At the same time, how to maintain high consistency and yield in the complicated steps of multi-layer film deposition, diffusion, doping, cleaning and texturing is also a challenge that technicians need to face. The TBC battery manufacturing process under the existing technology has not yet reached the ideal level in key indicators such as silicon wafer thinning, reducing fragmentation rate and improving efficiency. It is urgent to solve these problems by optimizing the battery structure and improving the process steps.

[0007] In view of this, it is necessary to provide an improved method for preparing a solar cell and a solar cell to solve the above technical problems. Summary of the invention

[0008] The present invention aims to solve at least one of the technical problems existing in the prior art. The present invention provides a method for preparing a solar cell and a solar cell. An alkali-resistant mask layer is deposited on the front side of a silicon substrate to protect the front side and reduce etching during subsequent polishing and cleaning processes, thereby allowing the use of thinner original silicon wafers without increasing the fragmentation rate, and etching can be performed multiple times on the back side to accurately divide and isolate two doping layers to prevent leakage, ultimately achieving the goals of reducing raw material costs, improving process yields, and enhancing battery performance.

[0009] A method for preparing a solar cell comprises the following steps: forming a mask layer on the front side of a silicon substrate, wherein the mask layer is an alkali-resistant film layer; forming a first tunneling layer and a first doping layer on the back side of the silicon substrate; the back side of the silicon substrate has a first region and a second region which are arranged at intervals, and removing the first doping layer, the first tunneling layer and part of the silicon substrate in the region outside the first region; forming a second tunneling layer and a second doping layer on the back side of the silicon substrate, wherein the doping type of the second doping layer is opposite to that of the first doping layer; removing the second doping layer, the second tunneling layer and part of the silicon substrate in the region outside the second region; removing the mask layer; forming a first electrode in contact with the first doping layer in the first region, and forming a second electrode in contact with the second doping layer in the second region.

[0010] In some embodiments, the mask layer is doped with a gettering element, and the doping content of the gettering element is 1 wt %-4 wt %.

[0011] In some embodiments, the gettering element is a Group III element and / or a Group V element; or the gettering element is phosphorus and / or boron.

[0012] In some embodiments, the mask layer is a single-layer film; or, the mask layer includes a first mask layer formed on the front side of the silicon substrate and a second mask layer formed on a surface of the first mask layer away from the silicon substrate, and the first mask layer is doped with the doping element.

[0013] In some embodiments, the mask layer includes a first mask layer formed on the front side of the silicon substrate and a second mask layer formed on the surface of the first mask layer away from the silicon substrate; the first mask layer is a stacked film of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with an impurity element; and / or the second mask layer is a stacked film of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; and / or the thickness of the first mask layer is less than the thickness of the second mask layer; and / or the thickness of the first mask layer is 10%-40% of the thickness of the entire mask layer.

[0014] In some implementations, “removing the mask layer” includes: removing the mask layer by acid washing, or removing the mask layer by RCA cleaning.

[0015] In some implementations, after removing the mask layer, a textured structure is formed on the front surface of the silicon substrate.

[0016] A solar cell comprises: a silicon substrate, wherein the back side of the silicon substrate comprises a first region, a second region, and a spacer region between the first region and the second region, wherein the width of the spacer region is 30 μm-100 μm, and the thickness of the silicon substrate located in the first region is greater than the thickness of the silicon substrate located in the second region; a first tunneling layer located in the first region, and a first doping layer located on a side of the first tunneling layer away from the silicon substrate, wherein the first doping layer and the silicon substrate have opposite doping types; a second tunneling layer located in the second region, and a second doping layer located on a side of the second tunneling layer away from the silicon substrate, wherein the second doping layer and the silicon substrate have the same doping type; a first electrode, contacting the first doping layer; and a second electrode, contacting the second doping layer.

[0017] In some implementations, a thickness of the silicon substrate located in the first region is 3 μm-8 μm thicker than a thickness of the silicon substrate located in the second region.

[0018] In some embodiments, the ratio of the area of ​​the first region to the area of ​​the second region is 0.5:1-1.5:1; or, the ratio of the width of the first region to the width of the second region is 0.5:1-1.5:1; or, the width of the first region is 200μm-800μm, and the width of the second region is 200μm-800μm.

[0019] In some embodiments, the solar cell further comprises a passivation layer located on the back side of the silicon substrate, the passivation layer contacts the surface of the silicon substrate exposed outward at the spacer region; or, the solar cell further comprises a passivation layer located on the back side of the silicon substrate, the passivation layer contacts the surface of the silicon substrate exposed outward at the spacer region in the spacer region, the passivation layer contacts the surface of the first doped layer away from the silicon substrate and / or the side surface facing the spacer region in the first region, and the passivation layer contacts the surface of the second doped layer away from the silicon substrate and / or the side surface facing the spacer region in the second region.

[0020] In some embodiments, the solar cell further comprises an anti-reflection layer located on the back side of the silicon substrate, the anti-reflection layer contacts the surface of the passivation layer away from the silicon substrate; or, the anti-reflection layer contacts the surface of the first doped layer away from the silicon substrate in the first region, contacts the surface of the second doped layer away from the silicon substrate in the second region, and contacts the outwardly exposed surface of the passivation layer in the spacing region.

[0021] In some implementations, in a direction away from the silicon substrate, the passivation layer directly contacting the back surface of the silicon substrate exposed in the spacer region is an aluminum oxide layer with a thickness of 2 nm to 7 nm.

[0022] In some embodiments, the silicon substrate is an N-type silicon substrate, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer; or, the silicon substrate is an N-type silicon substrate, the first doped layer is a boron-doped polysilicon layer, and the second doped layer is a phosphorus-doped polysilicon layer.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention deposits an alkali-resistant mask layer on the front side of the silicon substrate to protect the front side during subsequent polishing and alkali etching, thereby reducing the etching amount on the side where the front side is located; on the one hand, thinner original silicon wafers can be selected without increasing the fragmentation rate, ultimately achieving the goals of reducing raw material costs, improving process yields, and enhancing battery performance; on the other hand, under the premise of protecting the front side of the silicon substrate, alkali etching can be performed on the back side multiple times, so that the thickness of the silicon substrate located in the first area of ​​the solar cell is greater than the thickness of the silicon substrate located in the second area, and the width of the spacing area is appropriately reduced, so that the first doping structure and the second doping structure are accurately divided and isolated from the extension direction and thickness direction of the silicon substrate, the light absorption area is expanded and leakage is reduced, which is beneficial to improving battery efficiency.

[0024] Furthermore, by utilizing the organic coordination of the mask layer with the impurity gettering function located on the front side and the first doping layer and the second doping layer on the back side, double-sided impurity gettering is achieved, the adverse effects of metal impurities on device performance are reduced, and the open circuit voltage and conversion efficiency are improved; by protecting the front side with the mask layer during the steps of double-sided polishing and alkaline etching to remove the doping layer in the local area, excessive thinning of the front silicon wafer is effectively avoided, so that the present invention can use thinner silicon wafers and reduce costs; at the same time, the process flow of the method has high consistency and scalability, which is convenient for large-scale mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The figure is a flow chart of a method for preparing a solar cell according to one embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram after preparing a mask layer on the front side of a silicon substrate.

[0027] Figure 3 For Figure 2 Schematic diagram after preparing the first tunneling layer, the first doped polysilicon layer and the BSG layer on the back side of the silicon substrate.

[0028] Figure 4 For Figure 3 Schematic diagram after removing the first doping layer and the first tunneling layer in the area outside the first area.

[0029] Figure 5 For Figure 4 Schematic diagram after preparing the second tunneling layer, the second doping layer and the PSG layer on the back side of the silicon substrate.

[0030] Figure 6 For Figure 5 Schematic diagram after removing the second doping layer and the second tunneling layer in the area outside the second region.

[0031] Figure 7 For Figure 6 Schematic diagram after removing the front mask layer.

[0032] Figure 8 For Figure 7 Schematic diagram of the front side of the silicon substrate after texturing.

[0033] Fig. 9 For Figure 8 Schematic diagram after removing the BSG layer in the first area and the PSG layer in the second area.

[0034] Fig.10 For Fig. 9 Schematic diagram after preparing the first electrode and the second electrode on this basis.

[0035] Fig.11 For Fig. 9 Based on this, a schematic diagram is shown after a passivation layer and an anti-reflection layer are sequentially prepared on both sides, and then a first electrode and a second electrode are prepared on the back side.

[0036] Fig.12 yes Fig.11 A partial enlarged view of .

[0037] Fig.13 It is a schematic structural diagram of a solar cell in another embodiment of the present invention.

[0038] Fig.14 for Fig.13 A partial enlarged view of .

[0039] Fig.15 It is a schematic back side view of a solar cell in one embodiment of the present invention.

[0040] Fig.16 for Fig.15 A partial enlarged view of .

[0041] 1-silicon substrate, 11-first region, 12-second region, 13-spacer region, 14-third region, 15-fourth region, 2-mask layer, 31-first tunneling layer, 32-first doping layer, 33-first oxide layer; 41-second tunneling layer, 42-second doping layer, 43-second oxide layer, 5-passivation layer, 6-anti-reflection layer, 7-first electrode, 8-second electrode. DETAILED DESCRIPTION

[0042] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention; any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0043] In the various drawings of the present invention, for the sake of convenience in illustration, some sizes of structures or parts may be exaggerated relative to other structures or parts. Therefore, they are only used to illustrate the basic structure of the subject matter of the present invention.

[0044] Please refer to Figures 1 to 12 As shown, the present invention provides a method for preparing a solar cell, and the solar cell is prepared based on a silicon substrate 1.

[0045] For the convenience of description, with the silicon substrate 1 as a reference, the light-receiving surface (or main light-receiving surface) of the silicon substrate 1 is defined as the front side, and the backlight surface (or secondary light-receiving surface) arranged opposite to the light-receiving surface is defined as the back side. The film layers located on the front side of the silicon substrate 1 are collectively referred to as front film layers, the surface of the front film layer away from or facing away from the silicon substrate 1 is the front side of the corresponding front film layer, and the surface of the front film layer facing the silicon substrate 1 is the back side of the corresponding front film layer. The film layers located on the back side of the silicon substrate 1 are collectively referred to as back film layers, the surface of the back film layer facing the silicon substrate 1 is the front side of the corresponding back film layer, and the surface of the back film layer away from or facing away from the silicon substrate 1 is the back side of the corresponding back film layer.

[0046] The back side of the silicon substrate 1 has a first region 11, a second region 12, and a spacer region 13 between the first region 11 and the second region 12. The first region 11 is used to form a P-type doping structure, referred to as a P region, the second region 12 is used to form an N-type doping structure, referred to as an N region, and the spacer region 13 is used to separate the P region and the N region to prevent leakage.

[0047] The first area 11 , the second area 12 , and the spacer 13 are intended areas. In some implementations, a plurality of the first areas 11 and a plurality of the second areas 12 are arranged alternately, and any adjacent first areas 11 and second areas 12 are separated by the spacer 13 .

[0048] The inventors have found that the area ratio of the first region 11 to the second region 12 will affect the open circuit voltage (Voc) and short circuit current density (Jsc) of the solar cell, thereby affecting the efficiency of the cell. Specifically, if the area of ​​the first region 11 increases, the area of ​​the second region 12 will decrease accordingly, which will reduce the passivation performance of the entire back surface and reduce the open circuit voltage of the cell; conversely, reducing the area of ​​the first region 11 will reduce the short circuit current density of the cell.

[0049] In one embodiment, the ratio of the area of ​​the first region 11 to the area of ​​the second region 12 is 0.5:1-1.5:1, so that the P region and the N region have a good ratio, the short-circuit current density and the open-circuit voltage of the solar cell reach a balance, and the efficiency of the battery is better.

[0050] In one embodiment, the first areas 11 and the second areas 12 are alternately arranged, and in the arrangement direction of the first areas 11 and the second areas 12, the ratio of the width W1 of the first areas 11 to the width W2 of the second areas 12 is 0.5:1-1.5:1, and in the direction perpendicular to the arrangement direction of the first areas 11 and the second areas 12, the sizes of the first areas 11 and the second areas 12 are substantially the same.

[0051] In one embodiment, a width W1 of the first region 11 is 200 μm-800 μm, and a width W2 of the second region 12 is 200 μm-800 μm.

[0052] In one embodiment, if Fig.15 and Fig.16 As shown, in the embodiment, the first region 11 and the second region 12 are preferably distributed in a fork shape, and the spacer 13 separates the two to prevent leakage from the P region and the N region, thereby reducing the battery efficiency. Specifically, the first region 11 and the second region 12 are alternately distributed along the first direction, and the first region 11 and the second region 12 are staggered by a preset distance in a second direction perpendicular to the first direction. Furthermore, the third region 14 extending along the second direction connects a number of the first regions 11, and the third region 14 is used to form a first bus electrode connected in series with the first electrode 7; the fourth region 15 extending along the second direction connects a number of the second regions 12, and the fourth region 15 is used to form a second bus electrode connected in series with the second electrode 8.

[0053] In one embodiment, the width W3 of the spacer region 13 is 30 μm-100 μm, preferably 70 μm±10 μm, to ensure the isolation of the P region and the N region and avoid leakage. In some embodiments, the silicon substrate 1 is an N-type single crystal silicon wafer with a resistivity of 0.5 ohm·m-1.5 ohm·m and a thickness of 140 μm±20 μm. The following description is based on the example that the thickness of the silicon substrate 1 is 140 μm.

[0054] Please refer to Figures 1 to 12As shown, the preparation method of the solar cell includes the following steps: forming a mask layer 2 on the front side of the silicon substrate 1, wherein the mask layer 2 is an alkali-resistant film layer; forming a first tunneling layer 31 and a first doping layer 32 on the back side of the silicon substrate 1, wherein the first doping layer 32 is located on a side of the first tunneling layer 31 away from the silicon substrate 1; removing the first doping layer 32 in an area outside the first area 11; forming a second tunneling layer 41 and a second doping layer 42 on the back side of the silicon substrate 1, wherein the second doping layer 42 is located on a side of the second tunneling layer 41 away from the silicon substrate 1, and the doping type of the second doping layer 42 is opposite to that of the first doping layer 32; removing the second doping layer 42 in an area outside the second area 12; removing the mask layer 2; forming a first electrode 7 in contact with the first doping layer 32 in the first area 11; and forming a second electrode 8 in contact with the second doping layer 42 in the second area 12.

[0055] Please refer to Figure 2 As shown, the present invention forms the mask layer 2 with alkali resistance on the front side of the silicon substrate 1, thereby protecting the front side during subsequent polishing, cleaning and etching, reducing or avoiding etching and thinning of the silicon substrate 1 from the front side, thereby allowing the use of thinner original silicon wafers without increasing the fragmentation rate, and ultimately achieving the goals of reducing raw material costs, improving process yields and enhancing battery performance.

[0056] The thicker the mask layer 2 is, the better the protection effect on the front side of the silicon substrate 1 is, and the corresponding cost will increase. In one embodiment, the thickness of the mask layer 2 is 10nm-100nm. If the thickness of the mask layer 2 is lower than this range, the protection effect on the front side is weakened. If the thickness of the mask layer 2 is too thick, the cost of deposition and removal will increase.

[0057] The inventors have found that in the existing battery manufacturing process, effective gettering can only be achieved on the back side of the silicon substrate 1, but it is impossible to achieve effective gettering on the front side of the silicon substrate 1 without increasing the process complexity and fragmentation rate. The lack of double-sided gettering will make it difficult to fully remove metal impurities in the silicon substrate 1, thereby affecting the open circuit voltage and conversion efficiency of the solar cell.

[0058] In view of this, in some embodiments of the present invention, the mask layer 2 is doped with gettering elements. The gettering elements refer to: elements that can diffuse into the silicon substrate 1, and by utilizing the characteristics of these elements, impurities in the silicon substrate 1 can be removed or reduced when diffusing in the silicon substrate 1. In the subsequent high-temperature steps (such as boron diffusion or phosphorus diffusion), the front side of the silicon substrate 1 can be effectively gettered, that is, the impurities in the silicon substrate 1 are adsorbed from the front side of the silicon substrate 1, thereby further reducing the recombination loss caused by metal impurities and improving the open circuit voltage and conversion efficiency of the solar cell.

[0059] In the present invention, the gettering element is a Group III element and / or a Group V element. In one embodiment, the gettering element is phosphorus and / or boron, which has a good gettering effect and low cost. The following description will be made by taking phosphorus or boron doping as an example.

[0060] The mask layer 2 doped with the gettering element not only has alkali resistance, but also can protect the front side of the silicon substrate 1 from etching when double-sided polishing and alkali etching are used to remove the doped layer in the local area. At the same time, the gettering element inside it interacts with the impurities on the surface of the silicon substrate 1 in the high-temperature step, which helps to achieve double-sided gettering, so that the thickness of the original silicon wafer is reduced while maintaining a high product yield. Adding an appropriate amount of phosphorus to the alkali-resistant mask layer 2 to form a phosphorus-containing mask layer 2, or adding an appropriate amount of boron to form a boron-containing mask layer 2, can achieve the dual effects of resistance to alkali solution etching and gettering.

[0061] In one embodiment, by adding 1wt%-4wt% of the gettering element into the mask layer 2, the finally formed solar cell can obtain a higher open circuit voltage and conversion efficiency, while effectively reducing material and production costs, which is conducive to the large-scale industrialization of high-efficiency solar cells.

[0062] In the present invention, the gettering element may be doped in the entire mask layer 2 or in a portion of the mask layer 2, both of which can achieve the dual effects of alkali resistance and gettering.

[0063] In one embodiment of the present invention, the gettering element is doped in a portion of the mask layer 2 close to the silicon substrate 1 or in contact with the silicon substrate 1 , and the gettering element is not doped in a portion of the mask layer 2 far from the silicon substrate 1 or not in contact with the silicon substrate 1 .

[0064] In one embodiment, the mask layer 2 includes a first mask layer formed on the front side of the silicon substrate 1, and a second mask layer formed on the surface of the first mask layer away from the silicon substrate 1, and only the first mask layer is doped with the doping element, and the second mask layer is not doped with the doping element.

[0065] Through this layered design, the film layer in direct contact with the front side of the silicon substrate 1 contains the gettering element, which can provide a phosphorus source or a boron source for subsequent diffusion, thereby achieving effective gettering on the front side of the silicon substrate 1; it can also maintain excellent corrosion resistance when the doped layer in the local area is removed by double-sided polishing and alkaline etching; the outer film layer is not doped with the gettering element, which helps to reduce the use of materials such as phosphorus source and boron source and maintain the overall film uniformity and etching resistance of the mask layer 2.

[0066] In the specific implementation of the present invention, by using this double-layer mask structure, the thickness of the original silicon wafer can be more effectively reduced without increasing the fragmentation rate, and a good front surface quality can be ensured, thereby achieving an organic unity of double-sided impurity gettering and thinning costs. Experimental results show that the double-layer mask scheme can reduce manufacturing costs and enhance the operability and scalability of the process while maintaining or improving the open-circuit voltage and conversion efficiency of solar cells, providing a better technical path for large-scale mass production of solar cells.

[0067] In a specific embodiment of the present invention, the first mask layer is a stacked film of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with the doping element, and the content of the doping element is controlled in the range of 1wt%-4wt%; and / or the second mask layer is a stacked film of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0068] When the present invention is implemented, by designing the first mask layer as a film layer doped with the doping element, sufficient phosphorus source, boron source, etc. can be provided under high temperature conditions to achieve doping on the front side of the silicon substrate 1, and ensure that the film layer is structurally stable during the heat treatment process. If the second mask layer is designed as a film layer not doped with the doping element, the overall alkali resistance stability and mechanical strength of the mask layer 2 can be further improved, ensuring that the front side of the silicon wafer is protected from etching during double-sided polishing and alkali etching to remove the doping layer in a local area. In a preferred embodiment of the present invention, the number of layers and material combination of the mask layer 2 can be adjusted according to actual production needs, thereby achieving a balance between performance and cost.

[0069] In addition, by making the thickness of the first mask layer smaller than that of the second mask layer, the amount of the impurity elements such as phosphorus source and / or boron source, the film stress and the density of the film can be more effectively controlled, and the stability and consistency of the mask layer 2 in the subsequent process can be ensured, thereby further reducing the thickness of the original silicon wafer and reducing the fragmentation rate. This combined stacking design and thickness matching solution can improve the open circuit voltage and conversion efficiency of the battery while simplifying the process steps and reducing material costs, providing a more robust technical path for the large-scale production of TBC batteries.

[0070] In one embodiment, the thickness of the first mask layer is 10%-40% of the thickness of the entire mask layer 2. This ratio range can achieve a good gettering effect and reduce the cost of the mask layer 2. If the first mask layer is too thin, it will lead to insufficient gettering elements such as phosphorus source or boron source, reducing the gettering effect; if the first mask layer is too thick, it will increase the cost and easily form a dead layer on the front side of the silicon substrate 1.

[0071] When implementing the present invention, a first mask layer containing the gettering element can be first deposited on the front side of the silicon substrate 1. The first mask layer can be formed by one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with the gettering element. The content of the gettering element is controlled within the range of 1wt%-4wt%, so as to achieve effective front gettering in the subsequent high-temperature step. Then, the second mask layer is formed on the first mask layer. The second mask layer is one or more combinations of silicon oxide, silicon nitride, or silicon oxynitride not doped with the gettering element, so as to give the overall mask layer 2 higher alkali resistance and structural stability.

[0072] In one embodiment of the present invention, the mask layer 2 is a single-layer film. When implementing the present invention, if a mask layer 2 with a single-layer structure is selected, 1wt%-4wt% of the gettering element is uniformly doped in the entire mask layer 2 to achieve gettering on the front side of the silicon substrate 1 in the high-temperature step. At the same time, the single-layer film has alkali resistance, which can effectively protect the front side of the silicon substrate 1 when the doping layer in the local area is removed by double-sided polishing and alkali etching, and reduce the increase in the fragmentation rate caused by excessive etching.

[0073] In a single-layer structure, there is no need for layered stacking, and the deposition of the gettering element and the formation of the mask layer 2 can be completed in one film formation, which simplifies the process steps, reduces the material and equipment requirements, and is conducive to reducing defects or stress problems introduced by the film layer interface, thereby ensuring the uniformity and stability of the film layer. While maintaining the effective gettering and protection of the front side of the silicon substrate 1, this single-layer mask solution can achieve the goal of reducing costs and improving efficiency by reducing the initial silicon wafer thickness. Using this method in actual production can significantly shorten the preparation process, improve the flexibility and stability of the production line, and thus facilitate large-scale, low-cost manufacturing of TBC batteries.

[0074] The processes for forming the mask layer 2 include but are not limited to the following two.

[0075] The first method is to prepare a silicon slurry layer on the front side of the silicon substrate 1 by spraying, coating, printing or transfer process, and then dry the silicon slurry layer at a temperature of 100°C-200°C; and cure the silicon slurry layer at a temperature of 300°C-600°C.

[0076] When depositing the mask layer 2 not doped with the gettering element, the silicon slurry comprises silicon powder and an organic carrier. When depositing the mask layer 2 doped with the gettering element, the silicon slurry comprises silicon powder, a gettering element source such as a phosphorus source and / or a boron source, and an organic carrier.

[0077] Taking the formation of phosphorus-doped mask layer 2 as an example, silicon powder, organic carrier and phosphorus source are mixed to form silicon slurry of suitable viscosity, which is uniformly deposited on the front side of the silicon substrate 1 by spraying or printing process, and then the solvent and low-boiling organic components are removed by drying at 100℃-200℃, so that the silicon slurry is initially fixed on the surface of the silicon substrate 1. Subsequently, curing treatment is carried out at 300℃-600℃ to decompose the organic carrier and form a dense, stable, phosphorus-doped film layer. This film layer plays a role in gettingtering in subsequent high-temperature processes and has alkali resistance, effectively protecting the front side from excessive etching when double-sided polishing and alkali etching are used to remove the doping layer in the local area. Through this method, the production process of the mask layer 2 is simplified and flexible, which can adapt to different production line conditions, and effectively control the phosphorus doping concentration and film thickness, so as to achieve the technical goals of double-sided gettering and thinning the thickness of silicon wafers, thereby improving battery efficiency and reducing costs without increasing the fragmentation rate, which is conducive to the large-scale production of TBC batteries. When forming the mask layer 2 not doped with phosphorus, it is only necessary to mix silicon powder and an organic carrier to form a silicon slurry with a suitable viscosity, which will not be described in detail here.

[0078] The silicon powder is a combination of one or more of silicon oxide powder, silicon nitride powder, and silicon oxynitride powder; the phosphorus source is one or more of phosphoric acid, ammonium dihydrogen phosphate, diammonium hydrogen phosphate, and polyphosphoric acid. The organic carrier includes one or more of acrylic resin, ethyl cellulose, diethylene glycol monobutyl ether acetate, ethylene glycol, tributyl citrate, and polyamide wax.

[0079] By properly selecting the phosphorus source and the organic carrier component, a phosphorus-containing silicon slurry film layer can be quickly and evenly prepared on the front side of the silicon substrate 1. In the subsequent drying and curing process, the organic carrier component will decompose, volatilize or solidify to form a stable film layer structure, so that the phosphorus element can be evenly distributed in the film layer. The film layer provides phosphorus elements to play a role in gettingtering in the high-temperature step, and its alkali resistance effectively protects the front side of the silicon substrate 1 when the doping layer in the local area is removed by double-sided polishing and alkali etching.

[0080] In addition, the selection and matching of the organic carrier can ensure good rheology and adhesion of the slurry, so as to form a uniform and dense film layer on the surface of the silicon substrate 1. In this way, by controlling the combination ratio and processing parameters of silicon powder, phosphorus source and organic carrier, the function customization of the mask layer 2 can be flexibly achieved, that is, to ensure good phosphorus diffusion and impurity efficiency, film stability and acid-base tolerance, thereby reducing the fragmentation rate, improving the open circuit voltage and conversion efficiency, and providing better process conditions for reducing the thickness of the original silicon wafer and large-scale production.

[0081] When forming the mask layer 2 doped with boron, it is only necessary to replace the phosphorus source with a boron source. When forming the mask layer 2 doped with boron and phosphorus, it is only necessary to replace the phosphorus source with a mixture of a boron source and a phosphorus source.

[0082] The boron source is one or more of boric acid, elemental boron, methylboric acid, ethylboric acid and phenylboric acid.

[0083] The second method is to form the mask layer 2 by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process.

[0084] When depositing the mask layer 2 doped with phosphorus, appropriate silicon source (such as silane or silane), nitrogen source, oxygen source and other reaction gases can be introduced into the PECVD equipment, and phosphine or other phosphorus-containing precursor gases can be added under process conditions to achieve uniform, controllable and phosphorus-doped film deposition on the front side of the silicon wafer. When depositing the mask layer 2 not doped with phosphorus, no phosphorus-containing gas is introduced into the reaction gas.

[0085] In one embodiment, silicon nitride doped with phosphorus atoms in situ is formed by a PECVD process as the mask layer 2. The temperature of the PECVD process is 400°C-600°C, the silane flow rate is 1000sccm-3000sccm, the ammonia flow rate is 5000sccm-20000sccm, the phosphine flow rate is 300sccm-2000sccm, the pressure is 1000mTorr-3000mTorr, and a single layer of the mask layer 2 is deposited with a thickness of 10nm-100nm.

[0086] In another embodiment, the double-layer mask layer 2 is formed by PECVD, that is, the bottom layer close to the silicon substrate 1 is silicon nitride doped with phosphorus atoms in situ, and the outer layer is a silicon nitride layer. The PECVD process temperature is 400°C-600°C, the silane flow rate is 1000sccm-3000sccm, the ammonia flow rate is 5000sccm-20000sccm, the phosphine flow rate is 300sccm-2000sccm, and the pressure is 1000mTorr-3000mTorr, and the silicon nitride doped with phosphorus atoms is deposited with a thickness of 10nm-30nm. Then, the flow rate of phosphine is adjusted to 0, and other conditions remain unchanged, and the silicon nitride layer with a thickness of 10nm-70nm is continuously deposited.

[0087] Compared with a single-layer film, a double-layer film reduces phosphine consumption and saves costs. During subsequent boron diffusion and phosphorus diffusion, phosphorus atoms in silicon nitride diffuse into the silicon substrate 1, and phosphorus atoms are activated at high temperatures to achieve doping on the front side of the silicon substrate 1.

[0088] In the above two embodiments, only the ammonia gas is replaced by oxygen gas, and other gases and flow rates remain unchanged, so that phosphorus-doped silicon oxide can be obtained as the mask layer 2.

[0089] When depositing the mask layer 2 doped with boron, appropriate silicon source (such as silane or silane), nitrogen source, oxygen source and other reaction gases may be introduced into the PECVD device, and diborane or other boron-containing precursor gases may be added under process conditions to deposit a uniform, controllable and boron-doped film layer on the front side of the silicon substrate 1. When depositing the mask layer 2 not doped with boron, no boron-containing gas is introduced into the reaction gas.

[0090] In one embodiment, a PECVD process is used to form silicon nitride in situ doped with boron atoms as the mask layer 2. The temperature of the PECVD process is 400° C.-600° C., the silane flow rate is 1000sccm-3000sccm, the ammonia flow rate is 5000sccm-20000sccm, the diborane flow rate is 300sccm-2000sccm, the pressure is 1000mTorr-3000mTorr, and the boron-doped silicon nitride is deposited to a thickness of 10nm-100nm.

[0091] In another embodiment, a double-layer mask layer 2 is formed by PECVD, that is, the bottom layer close to the silicon substrate 1 is a silicon nitride layer in situ doped with boron atoms, and the outer layer is a silicon nitride layer. The temperature of the PECVD process is 400°C-600°C, the silane flow rate is 1000sccm-3000sccm, the ammonia flow rate is 5000sccm-20000sccm, the diborane flow rate is 300sccm-2000sccm, and the pressure is 1000mTorr-3000mTorr, and the boron-doped silicon nitride is deposited with a thickness of 10nm-30nm. Then, the flow rate of diborane is adjusted to 0, and other conditions remain unchanged, and the silicon nitride layer with a thickness of 10nm-70nm is continuously deposited.

[0092] Compared with the single-layer film, the double-layer film reduces the consumption of diborane and saves costs. During the diffusion of boron and phosphorus, the boron atoms in the silicon nitride diffuse to the silicon substrate 1, and the boron atoms are activated at high temperature to complete the front-side doping.

[0093] In the above two embodiments, ammonia is replaced by oxygen, and other gases and flow rates remain unchanged, so that boron-doped silicon oxide can be obtained as the mask layer 2.

[0094] When depositing the mask layer 2 containing boron and phosphorus, it is only necessary to add phosphine and diborane together. In one embodiment, the flow rates of the two are the same as those in the above embodiment. In one embodiment, the sum of the flow rates of phosphine and diborane is 300sccm-2000sccm, and the ratio of the two is not limited. Preferably, the flow rate of phosphine is greater than the flow rate of diborane. Phosphorus has a lower activation temperature than boron, which can reduce costs while ensuring the impurity absorption effect.

[0095] When depositing the mask layer 2 containing other gettering elements, it is only necessary to replace phosphine or diborane with a gas containing other gettering elements.

[0096] The mask layer 2 obtained by the PECVD process has high density and excellent adhesion, ensuring effective protection for the front side of the silicon substrate 1 in the subsequent double-sided polishing and alkaline etching steps, avoiding thinning of the silicon substrate 1 from the front side. At the same time, the mask layer 2 doped with phosphorus, boron and other impurity elements can effectively achieve front impurity in the high-temperature step, reduce the carrier recombination caused by metal impurities in the silicon substrate 1, and thus improve the open circuit voltage and conversion efficiency of the battery. The PECVD process has high process repeatability and large-scale mass production characteristics, which is conducive to strictly controlling the film thickness, impurity element content and film uniformity, and meeting the requirements of the TBC battery for the mask layer 2. In an embodiment of the present invention, the mask layer 2 deposited by PECVD can also achieve the goal of thinning the original silicon wafer thickness and maintaining a good yield, providing a stable and efficient mask film forming technology path for the industrial production of TBC batteries.

[0097] After the mask layer 2 is formed by the above method, the silicon substrate 1 is polished to form a planar structure on the back side, which is conducive to forming a high-quality back side film layer. Of course, when the back side of the silicon substrate 1 is a planar structure, polishing is not required.

[0098] The present invention adopts a double-sided polishing process, for example, polishing is performed by polishing alkali solution, the process is mature and does not require a single-sided mask, and the process cost is low.

[0099] In one embodiment, the damaged layer on the surface of the silicon substrate 1 is first removed in a mixed solution of potassium hydroxide (KOH) and hydrogen peroxide (H2O2), and then polished in a sodium hydroxide (NaOH) solution or a potassium hydroxide solution to form a planar structure on the back side of the silicon substrate 1, with a tower base size of 15 μm or more and a reflectivity of about 40%, for example, 35%-40%.

[0100] The plane structure formed by alkaline polishing is not an absolute plane. From a microscopic perspective, the surface has several "pyramid base structures". The height of the base is very low, basically at the nanometer level, so the size of the top and bottom of the base structure is not much different, and the size of the top is usually tested. The base size refers to: the distance between the two farthest points on the edge of the pyramid base structure, or the distance between the two farthest points on the curve after the edge of the pyramid base structure is smoothed into a curve. In general, the projection of the pyramid base structure on the silicon substrate 1 is a quadrilateral, and the base size refers to the distance of the top diagonal.

[0101] In this process, the alkali solution etching depth is 3μm-8μm, for example, about 5μm, which can remove the damaged layer in the original silicon wafer cutting process more thoroughly. After alkali polishing, only the back side of the silicon substrate 1 is thinned, and the front side is not thinned under the protection of the mask layer 2, thereby ensuring the overall thickness of the silicon substrate 1.

[0102] The “alkaline solution etching depth” in the present invention refers to the etching depth of the silicon substrate 1 .

[0103] The first doping layer 32 is a P-type doping layer, such as a boron-doped polysilicon layer. The first tunneling layer 31 and the first doping layer 32 constitute a first doping structure.

[0104] In one embodiment of the present invention, Figure 3 As shown, "forming the first tunneling layer 31 and the first doping layer 32" includes the following steps: forming the first tunneling layer 31; forming a first amorphous silicon layer, using BCl3 or BBr3 as a boron diffusion source, at a temperature of 850°C-1100°C, boron-diffusion of the first amorphous silicon layer to form a first doping layer 32, and forming a first oxide layer 33 on the surface.

[0105] When implementing the present invention, after the deposition and double-sided polishing of the mask layer 2 are completed, the first tunneling layer 31 of about 1nm-2nm can be formed on the back of the silicon wafer by LPCVD (Low Pressure Chemical Vapor Deposition) or thermal oxidation process. The first tunneling layer 31 is a silicon oxide layer or a silicon carbide layer. The first tunneling layer 31 lays the foundation for the subsequent polysilicon passivation contact.

[0106] Subsequently, the first amorphous silicon layer with a thickness of 50nm-500nm is deposited to cover the side of the first tunneling layer 31 away from the silicon substrate 1, and BCl3 or BBr3 is introduced as a boron diffusion source in a tubular diffusion device, and boron diffusion is performed at a high temperature of about 850℃-1100℃ to achieve the transformation of amorphous silicon into boron-doped polysilicon, and at the same time, a first oxide layer 33 is formed on its surface. The first oxide layer 33 is a borosilicate glass layer (Borosilicate Glass, BSG layer) with a thickness of about 30nm-150nm. By controlling the diffusion conditions and time, the surface doping concentration of the first doping layer 32 can reach 2E19atoms / cm 3 -2E20atoms / cm 3 , thereby obtaining a high-quality p-type doped layer.

[0107] In this process, through the doping effect of the mask layer 2 and the precise doping on the back side, the impurity content inside the silicon substrate 1 can be effectively reduced and carrier recombination can be suppressed, so that the solar cell can obtain a higher open circuit voltage. In addition, the stability and uniformity of the first doping layer 32 help to ensure the subsequent distinction between the P region and the N region and the precise layout of the back contact structure, thereby providing a high-quality infrastructure for the final TBC battery. Overall, this step clarifies the specific conditions and parameters for forming the first tunneling layer 31 and the first doping layer 32, so that the TBC battery of the present invention can further improve efficiency without increasing the fragmentation rate, achieving the goal of low cost and high performance.

[0108] In one embodiment of the present invention, Figure 4 The step of "removing the first doping layer 32 outside the first region 11" includes: removing the first oxide layer 33 outside the first region 11 on the back; removing the first oxide layer 33 on the front and side surfaces; and removing the first doping layer 32 outside the first region 11 on the back and the first doping layer 32 on the front by alkali etching. This step retains the first oxide layer 33 in the first region 11 to protect the first doping layer 32 inside in the subsequent texturing step.

[0109] It should be noted that the thickness of the first tunneling layer 31 is less than 3 nm, and can be removed when the first doping layer 32 is removed, without the need for a separate removal step.

[0110] In order to realize the precise functional zoning of different areas on the back side, it is necessary to selectively remove the formed P-type doped layer and related film layers in the designated second area 12 and the spacer area 13. This step can be coordinated with the subsequent chain machine to add acid cleaning (chain pickling) and alkaline etching process through laser film opening. The laser film opening process is first used to clean the first oxide layer 33 of the second area 12 and the spacer area 13 to ensure the subsequent thorough removal of the polysilicon layer in this area. At the same time, due to the expansion phenomenon caused by high-temperature diffusion, the first oxide layer 33 will also have a certain distribution on the front and side. Therefore, chain pickling is used to remove the first oxide layer 33 that expands on the front and side to ensure the final surface quality and uniformity of current transmission. After the first oxide layer 33 is removed, the area outside the first region 11 on the back (the second region 12 and the spacer 13) and the first doping layer 32 deposited on the front are selectively etched and removed by alkaline etching. This step allows the P-type doping layer that originally continuously covers the back to be removed in the second region 12 and the spacer 13, thereby creating conditions for the subsequent N-type doping and back contact structure separated from the P region in this region. Through this selective removal, the P region and the N region can be accurately divided on the back, laying the foundation for realizing double-sided impurity absorption and efficient charge separation of the TBC battery, while maintaining the thickness and quality of the silicon wafer under the protection of the mask layer 2 on the front, thereby achieving the goal of reducing costs and improving efficiency.

[0111] When "removing the first doping layer 32 in the area outside the first area 11", the boron atoms diffused into the silicon substrate 1 will be completely etched away, that is, a portion of the silicon substrate 1 will be etched away, so that in the direction away from the silicon substrate 1, the first area 11 and the area outside the first area 11 form a height difference, that is, the back side S1 of the silicon substrate 1 located in the first area 11 remains unchanged, and a portion of the back side of the area outside the first area 11 is etched away. The back side S2 of the silicon substrate 1 located in the second area 12 and the back side S3 of the silicon substrate 1 located in the spacer 13 are flush, and the thickness of the silicon substrate 1 located in the second area 12 and the spacer 13 is thinner than the thickness of the silicon substrate 1 located in the first area 11, and the thickness difference is about 3μm-8μm, such as Figure 4 shown.

[0112] The second doping layer 42 is an N-type doping layer, such as a phosphorus-doped polysilicon layer. The second tunneling layer 41 and the second doping layer 42 constitute a second doping structure.

[0113] In one embodiment of the present invention, please refer to Figure 5As shown, “forming the second tunneling layer 41 and the second doping layer 42 on the back” includes: forming the second tunneling layer 41; forming a second amorphous silicon layer, using phosphorus oxychloride as a diffusion source, the temperature is 850°C-950°C, diffusing phosphorus into the second amorphous silicon layer to form the second doping layer 42, and forming a second oxide layer 43 on the surface. The second oxide layer 43 is a phosphorosilicate glass (PSG) layer formed on the surface of the second doping layer 42.

[0114] The second tunneling layer 41 is a silicon oxide layer or a silicon carbide layer with a thickness of 1nm-2nm; and / or the surface doping concentration of the second doping layer 42 is 9E19 atoms / cm 3 -9E20atoms / cm 3 , with a thickness of 50nm-500nm; and / or the thickness of the second oxide layer 43 is 10nm-50nm.

[0115] After the first doping layer 32 and related film layers in the second region 12 and the spacer 13 are removed, the second tunneling layer 41 with a thickness of about 1nm-2nm is deposited on the entire back surface. Specifically, the same or similar process and material as the first tunneling layer 31 can be selected, such as silicon oxide or silicon carbide layer.

[0116] Then, a second amorphous silicon layer is formed on the second tunneling layer 41; phosphorus oxychloride (POCl3) is introduced into a tubular diffusion furnace as a phosphorus diffusion source, and the diffusion temperature is controlled to be 850°C-950°C, so that the amorphous silicon layer is converted into an N-type doped layer (here, a phosphorus-doped polysilicon layer), and a PSG layer is formed on the surface at the same time, with a thickness of between 10nm and 50nm. By adjusting the diffusion conditions and time, the surface doping concentration of the second doping layer 42 can reach 9E19atoms / cm 3 -9E20atoms / cm 3 And the thickness of the polysilicon layer is within the range of 50nm-500nm, preferably below 400nm, preferably 80nm-120nm, to ensure excellent conductivity and passivation properties.

[0117] In some embodiments of the present invention, Figure 6As shown, "removing the second doping layer 42 outside the second region 12" includes: removing the second oxide layer 43 outside the second region 12 on the back; removing the second oxide layer 43 around the front and sides; removing the area outside the second region 12 on the back (the first region 11 and the spacer 13) and the second doping layer 42 on the front. In this step, the second oxide layer 43 of the second region 12 is retained to protect the second doping layer 42 inside in the subsequent texturing step. It should be noted that the thickness of the second tunneling layer 41 is less than 3nm, and it can fall off when the second doping layer 42 is removed, and there is no need to set a separate removal step. In the actual process, the second tunneling layer 41 has no effect on the subsequent steps and does not need to be specially removed.

[0118] After the second doping layer 42 and the second oxide layer 43 have been formed on the back side, in order to achieve precise control of the alternating distribution of the P region / N region in the final battery structure, it is necessary to selectively remove the N-type doping layer and the second oxide layer 43 thereon in the first region 11 .

[0119] Specifically, the second doping layer 42 and the second oxide layer 43 are removed by laser film opening, chain pickling and alkaline etching processes. By laser film opening, the second oxide layer 43 of the first region 11 and the spacer 13 is firstly removed. Then, the PSG layer generated by the front and side expansion is removed by chain pickling. Subsequently, the first region 11, the spacer 13 and the second doping layer 42 of the front are selectively removed by an alkaline etching process to remove these N-type doping layers. At this time, the first region 11 is protected by the first oxide layer 33 to protect the internal P-type doping layer.

[0120] By precisely removing the second oxide layer 43 and the N-type doping layer, a back contact structure with P regions and N regions regularly alternating is finally presented on the back side, thereby improving the charge separation and collection efficiency. Thus, under the double-sided doping and protection of the front mask, a TBC battery with high open circuit voltage and high conversion efficiency is obtained with a thinner silicon substrate 1 and a lower fragmentation rate, which is conducive to the stable controllability of the process and large-scale industrial production.

[0121] Based on the above steps, the first doped layer 32 (p-type) and the second doped layer 42 (n-type) are alternately distributed on the back side, thereby realizing a back contact cell design. This N-type doped layer is spaced apart from the previously formed P-type doped layer, which greatly improves the efficiency of charge separation and collection.

[0122] At the same time, since there is the mask layer 2 on the front side, double-sided gettering is achieved during boron diffusion and phosphorus diffusion, and the front side of the silicon substrate 1 is protected from being etched when part of the doping layer is removed, ensuring that the minority carrier lifetime on the front side is maintained at a high level and thinner original silicon wafers can be used, which is conducive to reducing costs and improving conversion efficiency. In actual preparation, by strictly controlling the diffusion parameters and film quality, a back-contact TBC cell with excellent electrical performance and repeatability can be obtained, laying a solid foundation for high efficiency, low cost and large-scale mass production.

[0123] After the P region and the N region are formed based on the above steps, the mask layer 2 on the front side can be removed. Figure 7 As shown, "removing the mask layer 2" includes using acid to remove the mask layer 2, or using RCA cleaning (Radio Corporation of America Clean) to remove the mask layer 2. Preferably, a chain machine is used for single-side cleaning to retain the first oxide layer 33 located in the first area 11 and the second oxide layer 43 located in the second area 12.

[0124] Specifically, after double-sided polishing, the first tunneling layer 31 and the first doping layer 32 are formed, and the first doping layer 32 in the area outside the first area 11 is removed; the second tunneling layer 41 and the second doping layer 42 are formed, and the second doping layer 42 in the area outside the second area 12 is removed, the mask layer 2 on the front side needs to be completely removed to ensure that the front surface of the finished battery is flat and clean and suitable for subsequent texturing, passivation and electrode formation. By using acid pickling or RCA cleaning, the remaining mask layer 2 can be effectively removed, thereby exposing the smooth surface of the silicon substrate 1, creating ideal conditions for the subsequent texturing, deposition of passivation film (such as aluminum oxide film), and anti-reflection layer 6 (such as silicon nitride film).

[0125] In this process, the pickling process (such as HF solution treatment) can quickly dissolve and remove the silicon oxide, silicon nitride or silicon oxynitride components in the mask layer 2, while RCA cleaning can remove organic residues and metal ion contamination through a standardized cleaning process. Due to the presence of the mask layer 2 on the front side, the silicon substrate 1 is effectively protected in the polishing and alkali etching steps, thereby achieving appropriate thinning of the initial silicon wafer thickness and reducing the fragmentation rate, and effectively reducing the influence of metal impurities in the double-sided impurity absorption process. Through the cleaning of this step, the front side is finally clean, providing excellent interface conditions for the subsequent preparation of high-efficiency TBC batteries.

[0126] like Figure 8 As shown, the method for preparing a solar cell of the present invention further includes: after removing the mask layer 2, a velvet structure is formed on the front side of the silicon substrate 1, and a pyramid velvet structure is also formed in the spacer area 13 on the back side.

[0127] The base size of the pyramid velvet structure refers to the width of the pyramid base. The pyramid base is a square, and the diagonal of the square is called the base width or base size in the industry. In some embodiments, the base size of the velvet structure is not greater than 5 μm, or not greater than 4 μm, or not greater than 3 microns, preferably 1 μm-3 μm.

[0128] The pyramid velvet structure can reduce the reflectivity of the front side to 10% or less, for example, 7%-10%.

[0129] The texturing process is to etch from the surface of the silicon substrate 1 toward the inside of the silicon substrate 1. In some embodiments, Fig.11 and 12 As shown, the back side S3 of the silicon substrate 1 in the spacer 13 is flush with the back side S2 of the silicon substrate 1 in the second region 12. Alternatively, etching may also cause the thickness of the silicon substrate 1 in the spacer 13 to be slightly thinned, so that there is a certain height difference between the back side S3 of the silicon substrate 1 in the spacer 13 and the back side S2 of the silicon substrate 1 in the second region 12, and the side surface S5 of the silicon substrate 1 in the second region 12 is exposed outwardly toward the spacer 13. The solar cell finally formed is as shown in FIG. Fig.12 and Fig.13 shown.

[0130] Please refer to Fig. 9 and Fig.10 As shown, after texturing, acid pickling or RCA cleaning is used to remove the first oxide layer 33 located in the first area 11 and the second oxide layer 43 located in the second area 12, and subsequent steps, such as preparing the first electrode 7 and the second electrode 8, can be performed.

[0131] Please refer to Figures 11 to 14 As shown, in one embodiment of the present invention, before forming the first electrode 7 and the second electrode 8, the method for preparing a solar cell further includes forming a passivation layer 5 on both sides of the solar cell, and the thickness of the passivation layer 5 is 2nm-7nm.

[0132] An aluminum oxide layer may be formed on both sides by an ALD (Atomic Layer Deposition) process as the passivation layer 5. The aluminum oxide layer may provide excellent charge compensation and surface passivation effects at the interface, thereby helping to reduce surface recombination and increase the open circuit voltage.

[0133] In one embodiment of the present invention, before forming the first electrode 7 and the second electrode 8, the method for preparing a solar cell further includes forming an anti-reflection layer 6 on both sides of the solar cell, which can construct an optical interface with low reflectivity on the surface of the cell to maximize the coupling and absorption of incident light.

[0134] In one embodiment, the anti-reflection layer 6 is a laminated film of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and / or the thickness of the anti-reflection layer 6 is 60nm-130nm. The anti-reflection layer 6 can be deposited by PECVD process.

[0135] In one embodiment of the present invention, the passivation layer 5 is first deposited on both sides by the above process, and then the anti-reflection layer 6 is deposited on both sides by the above process. Through the dual effects of the passivation layer 5 and the anti-reflection layer 6, the present invention further reduces surface recombination and improves optical efficiency, so that the open circuit voltage and fill factor of the solar cell are enhanced. In addition, the advantages of front-side impurity gettering and thin-film production ultimately enable the finished TBC battery to achieve higher conversion efficiency and stable performance under low-cost conditions, providing reliable technical guarantees for large-scale mass production.

[0136] The first electrode 7 and the second electrode 8 can be prepared by, but not limited to, a process commonly used in the art. In the present invention, the first electrode 7 and the second electrode 8 are formed by screen printing and sintering.

[0137] The solar cell obtained by the above method has a high open circuit voltage, fill factor and conversion efficiency. The preparation method of the solar cell of the present invention and the solar cell obtained by the preparation are described in detail below with a specific embodiment.

[0138] The present invention also provides a solar cell, which can be prepared by the above preparation method or by other methods.

[0139] Please refer to Figures 10 to 14 As shown, the solar cell includes a silicon substrate 1, a first doping structure located on the back side of the silicon substrate 1, a second doping structure located on the back side of the silicon substrate 1 and spaced apart from the first doping structure, a first electrode 7 in contact with the first doping structure, and a second electrode 8 in contact with the second doping structure.

[0140] One of the first doping structure and the second doping structure has the same doping type as the silicon substrate 1, and the other has a doping type opposite to the silicon substrate 1. One of the first doping structure and the second doping structure is a P-type doping structure, and the other is an N-type doping structure.

[0141] The back side of the silicon substrate 1 has a first region 11, a second region 12, and a spacer region 13 located between the first region 11 and the second region 12. The first doping structure is located in the first region 11, and the second doping structure is located in the second region 12. Therefore, the area, width, thickness and other parameters of the silicon substrate 1 located in the first region 11, the second region 12 and the spacer region 13 respectively have a great influence on the performance of the battery. Changing any one of the parameters can optimize the battery efficiency.

[0142] In one embodiment, the ratio of the area of ​​the first region 11 to the area of ​​the second region 12 is 0.5:1-1.5:1, so that the P region and the N region have a good ratio, the short-circuit current density and the open-circuit voltage of the battery reach a balance, and the efficiency of the battery is optimal. If the ratio is too small, the area of ​​the first region 11 is too large and the area of ​​the second region 12 is too small, which will reduce the passivation performance of the entire back side and reduce the open-circuit voltage of the battery. If the ratio is too large, the area of ​​the first region 11 is too small and the area of ​​the second region 12 is too large, which will reduce the area of ​​the PN junction, which is not conducive to the generation and separation of carriers and reduces the short-circuit current density of the battery.

[0143] In one embodiment, the first areas 11 and the second areas 12 are alternately arranged, and in the arrangement direction of the first areas 11 and the second areas 12, the ratio of the width W1 of the first areas 11 to the width W2 of the second areas 12 is 0.5:1-1.5:1, and in the direction perpendicular to the arrangement direction of the first areas 11 and the second areas 12, the sizes of the first areas 11 and the second areas 12 are substantially the same.

[0144] In one embodiment, a width W1 of the first region 11 is 200 μm-800 μm, and a width W2 of the second region 12 is 200 μm-800 μm.

[0145] In one embodiment, the width W1 of the first region 11 is smaller than the width W2 of the second region 12. The width W1 of the first region 11 is 300 μm±100 nm, and the width W2 of the second region 12 is 420 μm±100 nm.

[0146] The width W3 of the spacer 13 is 30 μm-100 μm, preferably 70 μm±10 μm, and the first doping structure and the second doping structure are insulated and isolated in the lateral direction. If the spacer 13 is too wide, the width of the first region 11 and / or the second region 12 will be reduced, and the efficiency of the battery will be reduced. If the spacer 13 is too narrow, electrical isolation cannot be achieved.

[0147] In addition, a thickness d1 of the silicon substrate 1 in the first region 11 is greater than a thickness d2 of the silicon substrate 1 in the second region 12. In the thickness direction of the silicon substrate 1, the first doping structure and the second doping structure are insulated and isolated.

[0148] In one embodiment, the thickness d1 of the silicon substrate 1 located in the first region 11 is 3 μm-8 μm greater than the thickness d2 of the silicon substrate 1 located in the second region 12, preferably about 5 μm; so that the P region and the N region are staggered in the thickness direction of the silicon substrate 1 to avoid leakage in the two regions.

[0149] The present invention improves the insulation isolation between the first doping structure and the second doping structure by comprehensively adjusting the width of the spacer 13 and the thickness difference between the first region 11 and the second region 12, thereby avoiding leakage points and improving battery efficiency.

[0150] The first doping structure includes a first tunneling layer 31 located in the first region 11 and a first doping layer 32 located on a side of the first tunneling layer 31 away from the silicon substrate 1 . The first doping layer 32 has a doping type opposite to that of the silicon substrate 1 . The first electrode 7 contacts the first doping layer 32 .

[0151] The second doping structure includes a second tunneling layer 41 located in the second region 12 and a second doping layer 42 located on a side of the second tunneling layer 41 away from the silicon substrate 1 . The second doping layer 42 has the same doping type as the silicon substrate 1 , and the second electrode 8 contacts the second doping layer 42 .

[0152] In one embodiment, the silicon substrate 1 is an N-type silicon substrate, the first doped layer 32 is a P-type doped layer, and the second doped layer 42 is an N-type doped layer. In the direction away from the silicon substrate 1, the P-type doped layer is higher than the N-type doped layer, and its back and side surfaces can receive sunlight, thereby increasing the light absorption area and improving the battery efficiency.

[0153] In a specific embodiment, the first doping layer 32 is a boron-doped polysilicon layer, and its surface doping concentration reaches 2E19 atoms / cm 3 -2E20atoms / cm 3 , the thickness is 50nm-500nm, preferably less than 400nm, preferably 80nm-120nm.

[0154] The second doping layer 42 is a phosphorus-doped polysilicon layer, and its surface doping concentration reaches 9E19atoms / cm 3 -9E20atoms / cm 3, the thickness is in the range of 50nm-500nm, preferably below 400nm, preferably 80nm-120nm.

[0155] In one embodiment, the solar cell further comprises a passivation layer 5 located on the back side of the silicon substrate 1 to passivate the back structure and increase the open circuit voltage. The passivation layer 5 is an aluminum oxide layer with a thickness of 2nm-7nm.

[0156] In one embodiment, if Figures 10 to 12 As shown, the passivation layer 5 contacts the surface of the silicon substrate 1 exposed outward at the spacer 13. The surface includes the back surface S3 of the silicon substrate 1 located in the spacer 13 and the side surface S4 of the silicon substrate 1 located in the first region 11 facing the spacer 13.

[0157] In another embodiment, if Fig.13 and Fig.14 As shown, the thickness of the silicon substrate 1 located in the spacer area 13 is less than the thickness of the silicon substrate 1 located in the second area 12, and the surface includes the back side S3 of the silicon substrate 1 located in the spacer area 13, the side surface S4 of the silicon substrate 1 located in the first area 11 facing the spacer area 13, and the side surface S5 of the silicon substrate 1 located in the second area 12 facing the spacer area 13.

[0158] In addition, Figures 10 to 13 As shown, the side surface of the first doping structure facing the spacer 13 is substantially the same as the side surface S4 of the silicon substrate 1 located in the first region 11 facing the spacer 13, and is also exposed outward at the spacer 13 and covered by the passivation layer 5. Fig.13 and Fig.14 As shown, the side surface of the second doping structure facing the spacer 13 and the side surface S5 of the silicon substrate 1 located in the second region 12 facing the spacer 13 are substantially one surface, and are also exposed outwardly at the spacer 13 and covered by the passivation layer 5. Specifically, the passivation layer 5 is in contact with the surface of the silicon substrate 1 exposed outwardly at the spacer 13 in the spacer 13, the passivation layer 5 is in contact with the surface of the first doping layer 32 away from the silicon substrate 1 and / or the side surface facing the spacer 13 in the first region 11, and the passivation layer 5 is in contact with the surface of the second doping layer 42 away from the silicon substrate 1 and / or the side surface facing the spacer 13 in the second region 12.

[0159] In another embodiment, the passivation layer 5 contacts the surface exposed outward at the spacer region 13 in the spacer region 13, the passivation layer 5 contacts the surface of the first doped layer 32 away from the silicon substrate 1 in the first region 11, and the passivation layer 5 contacts the surface of the second doped layer 42 away from the silicon substrate 1 in the second region 12.

[0160] In a specific embodiment, in a direction away from the silicon substrate 1, the passivation layer 5 that is in direct contact with the back side S3 of the silicon substrate 1 exposed in the spacer area 13 is a 2nm-7nm aluminum oxide layer, which ensures the passivation effect of the spacer area 13 and improves the open circuit voltage.

[0161] In one embodiment, the solar cell further comprises an anti-reflection layer 6 located on the back side of the silicon substrate 1 to reduce light reflection on the back side. The anti-reflection layer 6 is a laminated film of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and / or the thickness of the anti-reflection layer 6 is 60nm-130nm.

[0162] In one embodiment, the passivation layer 5 only covers the surface of the spacer region 13 or covers the entire back surface, and the anti-reflection layer 6 is in contact with the surface of the passivation layer 5 away from the silicon substrate 1 .

[0163] In another embodiment, the passivation layer 5 only covers the entire surface of the spacer 13, the anti-reflection layer 6 contacts the surface of the first doping layer 32 away from the silicon substrate 1 in the first region 11, contacts the surface of the second doping layer 42 away from the silicon substrate 1 in the second region 12, and contacts the surface of the passivation layer 5 exposed outward in the spacer 13. The surface of the passivation layer 5 exposed outward is the surface of the passivation layer 5 away from the silicon substrate 1, away from the first doping structure, and away from the second doping structure.

[0164] In addition, the characteristic parameters of the solar cell mentioned above in the present invention are applicable to the corresponding structure in the method for preparing the solar cell; the characteristic parameters of the method for preparing the solar cell mentioned above are applicable to the corresponding characteristics of the solar cell. The solar cell can be prepared by the method for preparing the solar cell mentioned above, or by other preparation methods.

[0165] Hereinafter, specific embodiments will be provided to explain in detail the method for preparing the solar cell of the present invention.

[0166] Example An N-type single crystal silicon wafer is selected as the silicon substrate 1, with a resistivity of 1Ω·cm and an initial thickness of about 140 μm.

[0167] First, a double-layer mask layer 2 is formed on the front side of the silicon substrate 1 by spraying or printing. The bottom layer is a phosphorus-doped silicon oxide film with a phosphorus content of 3wt%; the outer layer is non-phosphorus-doped silicon oxide. The mask layer 2 is dried at 150°C and then cured at 400°C to obtain a dense, alkali-resistant film layer that can achieve doping in subsequent high-temperature steps. The mask layer 2 provides stable protection for the front side of the silicon substrate 1 during double-sided polishing, etching and cleaning, so that the front side is not affected by alkali etching, so that thinner original silicon wafers can be used without increasing the fragmentation rate, thereby reducing costs.

[0168] After forming the mask layer 2, the double-sided silicon wafer is polished to remove the damaged layer and obtain a flat and smooth back side. The damaged layer on the surface of the silicon wafer is first removed in a mixed solution of KOH and H2O2, and then alkaline polishing is performed in a sodium hydroxide solution or a potassium hydroxide solution. The tower base size on the back of the silicon wafer is 15μm, the reflectivity is 40%, and the alkaline solution etching depth is about 5μm, which can remove the damage caused by the cutting process of the original silicon wafer more thoroughly. The thickness of the silicon substrate 1 after double-sided alkaline polishing is 135μm.

[0169] Then, about 1.5nm SiOx and 300nm intrinsic amorphous silicon layer are deposited on the back of the silicon wafer by LPCVD process. Boron is diffused into the amorphous silicon layer with BCl3 or BBr3 as diffusion source at 850℃-1050℃ to convert it into a p-type doped layer (boron-doped polysilicon layer), and a 60nm thick first oxide layer 33 (BSG layer) is formed on the surface with a doping concentration of 8E19atoms / cm 3 At this time, the mask layer 2 can simultaneously achieve gettering of the front side of the silicon wafer during the high temperature treatment, which helps to reduce metal impurities and increase the open circuit voltage.

[0170] The first oxide layer 33 outside the first region 11 is removed by laser film opening. The laser is a green picosecond laser with a power of 50W. The first oxide layer 33 on the front and side is removed by chain pickling. The acid is HF with a concentration of 9%. Then, the second region 12, the spacer 13 and the p-type doped layer on the front are removed by using a slot-type alkali etching device. That is, alkali solution is added to the slot machine. The alkali solution is a sodium hydroxide solution or a potassium hydroxide solution. The etching depth of the alkali solution is about 5μm. The boron atoms in the silicon substrate 1 are completely etched away to avoid leakage caused by PN contact. After this step, the thickness of the silicon substrate 1 is reduced to about 130μm; the tower base size of the second region 12 is 30μm. This step completes the preliminary isolation preparation of the P region and the N region on the back.

[0171] 1.5nm silicon oxide and 20nm amorphous silicon layer are deposited on the entire back side; a tubular diffusion device is used to diffuse phosphorus at 850℃-950℃ with POCl3 as the diffusion source to form an N-type doped layer (phosphorus-doped polysilicon layer with a surface doping concentration of 8E20atoms / cm 3 ) and a 50nm thick second oxide layer 43 (PSG layer).

[0172] Laser film opening is used to remove the second oxide layer 43 outside the second region 12. The laser is a purple picosecond laser with a power of 10 W. A chain machine is used for pickling to remove the second oxide layer 43 on the front and side surfaces. A slot machine is used for alkaline etching to remove the N-type doping layer outside the second region 12 and on the front surface, so that the back surface finally presents a back contact structure in which the p-type doping layer and the n-type doping layer are alternately distributed.

[0173] After the P region and N region structure division is completed, the mask layer 2 on the front side is pickled by a chain machine to completely remove the mask layer 2. At this time, the front surface of the silicon substrate 1 remains clean and flat, and the impurity concentration has been effectively reduced during the double-sided diffusion and impurity gettering process.

[0174] Then, a texturing alkali solution is used to form a pyramid texture structure on the front surface of the silicon substrate 1, with a pyramid base size of 2 μm and a reflectivity of 8%.

[0175] After texturing, the first oxide layer 33 remaining in the first region 11 is removed, and the second oxide layer 43 remaining in the second region 12 is removed.

[0176] Subsequently, aluminum oxide with a thickness of about 4 nm is deposited on both the front and back surfaces by using an ALD process as the passivation layer 5 .

[0177] The PECVD process is used to deposit an 80nm silicon nitride layer on both the front and back surfaces as the anti-reflection layer 6, which significantly improves the surface passivation effect and the incident light absorption rate.

[0178] Interdigitated electrodes are formed by screen printing and sintering in the electrode area of ​​the first region 11 and the electrode area of ​​the second region 12 to complete the preparation of the solar cell.

[0179] Comparative Example The only difference from the present embodiment is that: the initial thickness of the silicon wafer is 150μm, and the front and back sides are both thinned by 5μm during double-sided polishing. After polishing, the thickness of the silicon substrate 1 is about 140μm; when removing the area outside the first area 11 on the back side and the P-type doped layer on the front side, the double sides of the silicon substrate 1 are thinned, and the thickness of the silicon substrate 1 located in the second area 12 and the spacer area 13 becomes about 130μm; when removing the area outside the second area 12 on the back side and the N-type doped layer on the front side, a texturing alkali solution is directly used to form a velvet structure on the front side of the silicon substrate 1 and the spacer area 13 that is the same as that in the embodiment, and the thickness of the silicon substrate 1 finally retained is basically the same as that in the embodiment.

[0180] The solar cells obtained in the examples and comparative examples were tested, and the results are shown in Table 1.

[0181] Table 1

[0182] Note: Voc represents open circuit voltage, Jsc represents short circuit current density, FF represents fill factor, and EFF represents conversion efficiency.

[0183] From the experimental results, the embodiment uses a 140μm original silicon wafer. Since the front side is protected by the mask layer 2 during alkali polishing and cleaning, the silicon substrate 1 is only etched on the back side, and the final remaining thickness of the silicon substrate 1 is about 130μm. The comparative example uses a 150μm original silicon wafer, which is etched on both sides during alkali polishing and cleaning, and the final remaining thickness of the silicon substrate 1 is about 130μm. It can be seen that compared with the comparative example, the thickness of the original silicon wafer in the embodiment is thinner by 10μm, saving the cost of the silicon wafer.

[0184] In the embodiment, the mask layer 2 doped with the doping element has a double-sided doping effect, so that the metal impurities in the silicon wafer are significantly reduced, and a better passivation effect is achieved, which effectively reduces the recombination caused by metal impurities; the comparative example is a single-sided doping on the back side, and the open circuit voltage, fill factor, etc. are significantly lower.

[0185] In summary, compared with the comparative example, the embodiment of the present invention can still obtain a higher open circuit voltage and fill factor, and the efficiency is increased by 0.17%, while maintaining a good fragmentation rate and yield. It can be seen that the preparation method of the present invention can reduce the thickness of the original silicon wafer by about 10 μm under the same final thickness and structural conditions, and improve the conversion efficiency, reflecting a significant cost reduction and efficiency improvement advantage, which is more conducive to the large-scale and stable mass production of solar cells.

[0186] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method may also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0187] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention; they are not intended to limit the scope of protection of the present invention; any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: Forming a mask layer (2) on the front surface of a silicon substrate (1), wherein the mask layer (2) is an alkali-resistant film layer; forming a first tunneling layer (31) and a first doping layer (32) on the back side of the silicon substrate (1); The back side of the silicon substrate (1) comprises a first region (11) and a second region (12) which are arranged at intervals, and the first doping layer (32), the first tunneling layer (31) and a part of the silicon substrate (1) in the region outside the first region (11) are removed; forming a second tunneling layer (41) and a second doping layer (42) on the back side of the silicon substrate (1), wherein the doping type of the second doping layer (42) is opposite to that of the first doping layer (32); removing the second doping layer (42), the second tunneling layer (41) and a portion of the silicon substrate (1) in an area outside the second area (12); removing the mask layer (2); A first electrode (7) in contact with the first doped layer (32) is formed in the first region (11), and a second electrode (8) in contact with the second doped layer (42) is formed in the second region (12).

2. The method for preparing a solar cell according to claim 1, characterized in that: The mask layer (2) is doped with a gettering element, and the doping content of the gettering element is 1wt%-4wt%.

3. The method for preparing a solar cell according to claim 2, characterized in that: The gettering element is a third main group element and / or a fifth main group element.

4. The method for preparing a solar cell according to claim 2, characterized in that: The mask layer (2) is a single-layer film; Alternatively, the mask layer (2) comprises a first mask layer formed on the front surface of the silicon substrate (1), and a second mask layer formed on a surface of the first mask layer away from the silicon substrate (1), and the first mask layer is doped with the gettering element.

5. The method for preparing a solar cell according to claim 1, characterized in that: The mask layer (2) comprises a first mask layer formed on the front surface of the silicon substrate (1), and a second mask layer formed on a surface of the first mask layer away from the silicon substrate (1); The first mask layer is a laminated film of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride doped with gettering elements; And / or, the second mask layer is a stacked film of one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride; and / or, the thickness of the first mask layer is less than the thickness of the second mask layer; And / or, the thickness of the first mask layer is 10%-40% of the thickness of the entire mask layer (2).

6. The method for preparing a solar cell according to claim 1, characterized in that: Removing the mask layer (2) comprises: removing the mask layer (2) by pickling, or removing the mask layer (2) by RCA cleaning.

7. The method for preparing a solar cell according to claim 1, characterized in that: After the mask layer (2) is removed, a velvet structure is formed on the front surface of the silicon substrate (1).

8. A solar cell, characterized in that: include: A silicon substrate (1), wherein the back side of the silicon substrate (1) comprises a first region (11), a second region (12), and a spacer region (13) located between the first region (11) and the second region (12), the width of the spacer region (13) being 30 μm-100 μm, and the thickness of the silicon substrate (1) located in the first region (11) being greater than the thickness of the silicon substrate (1) located in the second region (12); a first tunneling layer (31) located in the first region (11), and a first doping layer (32) located on a side of the first tunneling layer (31) away from the silicon substrate (1), the first doping layer (32) having a doping type opposite to that of the silicon substrate (1); a second tunneling layer (41) located in the second region (12), and a second doping layer (42) located on a side of the second tunneling layer (41) away from the silicon substrate (1), the second doping layer (42) having the same doping type as the silicon substrate (1); A first electrode (7) in contact with the first doped layer (32); A second electrode (8) is in contact with the second doping layer (42).

9. The solar cell according to claim 8, characterized in that: The thickness of the silicon substrate (1) located in the first region (11) is 3 μm-8 μm greater than the thickness of the silicon substrate (1) located in the second region (12).

10. The solar cell according to claim 8, characterized in that: The ratio of the area of ​​the first region (11) to the area of ​​the second region (12) is 0.5:1-1.5:1; Or, the ratio of the width of the first region (11) to the width of the second region (12) is 0.5:1-1.5:1; Alternatively, the width of the first region (11) is 200 μm-800 μm, and the width of the second region (12) is 200 μm-800 μm.

11. The solar cell according to any one of claims 8 to 10, characterized in that: It also includes a passivation layer (5) located on the back side of the silicon substrate (1), the passivation layer (5) being in contact with the surface of the silicon substrate (1) exposed outward at the spacer region (13); Alternatively, the solar cell further comprises a passivation layer (5) located on the back side of the silicon substrate (1), the passivation layer (5) in the spacer region (13) being in contact with the surface of the silicon substrate (1) exposed outwardly in the spacer region (13), the passivation layer (5) in the first region (11) being in contact with the surface of the first doped layer (32) away from the silicon substrate (1) and / or the side surface facing the spacer region (13), and the passivation layer (5) in the second region (12) being in contact with the surface of the second doped layer (42) away from the silicon substrate (1) and / or the side surface facing the spacer region (13).

12. The solar cell according to claim 11, characterized in that: It also includes an anti-reflection layer (6) located on the back side of the silicon substrate (1), The anti-reflection layer (6) is in contact with a surface of the passivation layer (5) away from the silicon substrate (1); Alternatively, the anti-reflection layer (6) contacts a surface of the first doped layer (32) away from the silicon substrate (1) in the first region (11), contacts a surface of the second doped layer (42) away from the silicon substrate (1) in the second region (12), and contacts an outwardly exposed surface of the passivation layer (5) in the spacing region (13).

13. The solar cell according to claim 11, characterized in that: In a direction away from the silicon substrate (1), the passivation layer (5) directly in contact with the back surface of the silicon substrate (1) exposed in the spacer region (13) is an aluminum oxide layer with a thickness of 2 nm to 7 nm.

14. The solar cell according to claim 11, characterized in that: The silicon substrate (1) is an N-type silicon substrate, the first doping layer (32) is a P-type doping layer, and the second doping layer (42) is an N-type doping layer; Alternatively, the silicon substrate (1) is an N-type silicon substrate, the first doped layer (32) is a boron-doped polysilicon layer, and the second doped layer (42) is a phosphorus-doped polysilicon layer.

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